REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change case outline X to case outline Q. Add case outline Y. Delete group C programmability test and add margin test. Convert to military drawing format. 86-09-23 M. A. Frye B Add vendor CAGE 34335. Add device type 02. Change drawing CAGE number. Editorial changes throughout. 88-05-26 M. A. Frye C Changes made in accordance with NOR 5962-R038-93 92-12-09 Monica L. Poelking D Incorporated Revision C. Updated drawing to Q level. Updated boilerplate to MIL-PRF-38535 requirements. – LTG 01-12-03 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED REV SHEET REV D D D D D D D SHEET 15 16 17 18 19 20 21 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Greg A. Pitz STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil CHECKED BY Ray Monnin APPROVED BY Michael A. Frye DRAWING APPROVAL DATE MICROCIRCUIT, DIGITAL, N-CHANNEL, MOS 8-BIT MICROCOMPUTER WITH 32 K-BIT UVEPROM, MONOLITHIC SILICON 85-06-24 AMSC N/A REVISION LEVEL D SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 84190 21 5962-E086-02 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84190 Drawing number 01 Q X Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Frequency 01 8751H-8 8-bit microcomputer with 32 K-bit UVEPROM 8.0 MHz max 02 8751H 8-bit microcomputer with 32 K-bit UVEPROM 12.0 MHz max 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Q Y Descriptive designator Terminals GDIP1-T40 or CDIP2-T40 CQCC1-N44 Package style 1/ 40 44 Dual-in-line package Square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Voltage on any pin (except VPP) 2/ ......................................... Voltage (VPP) ........................................................................... Power dissipation (PD)............................................................. Storage temperature range ..................................................... Junction temperature (TJ)........................................................ Lead temperature (soldering, 5 seconds) ............................... Thermal resistance, junction-to-case (θJC): Cases Q and Y ...................................................................... -0.5 V dc to +7.0 V dc 21.5 V dc 2.0 W -65°C to +150°C +165°C +260°C See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage (VCC)................................................................ 4.5 V dc to 5.5 V dc Program voltage (VPP) ............................................................. 21.0 V dc ±0.5 V dc Case operating temperature range (TC) .................................. -55°C to +125°C 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ All voltages referenced to VSS. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the qualifying activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Programmed EPROM device. The requirements for supplying programmed EPROM devices are not part of this drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 3 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturer’s QM plan, the “QD” certification mark shall be used in place of the "Q" or "QML" certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.10.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 and table III. 3.10.3 Verification of erasure of programmability of EPROMS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that al bits are in the proper state. Any bit that does not verify to be the proper state shall constitute a device failure, and shall be removed from the lot. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55°C ≤ TC ≤ +125°C VCC = 5.0 V ±10% unless otherwise specified Group A subgroups Device type Limits Min Unit Max Input low voltage Input high voltage (except XTAL2, RST) VIL 1, 2, 3 All 0.7 VIH 1, 2, 3 All 2.2 V Input high voltage to XTAL2, RST Output low voltage ports 1, 2, 3 Output low voltage port 0 ALE, PSEN VIH1 XTAL1 = VSS 1, 2, 3 All 2.5 V VOL IOL = 1.2 mA 1, 2, 3 All VOL1 IOL = 2.8 mA 1, 2, 3 All Output high voltage ports 1, 2, 3 Output high voltage port 0 (in external bus mode), ALE, PSEN Logical 0 input current P1, P2, P3 Logical 0 input current to EA/VPP Logical 0 input current to XTAL2 Input leakage current to port 0 Logical input current to EA/VPP Input current to RST/VPD to activate reset VOH IOH = -60 µA 1, 2, 3l All 2.4 V VOH1 IOH = -300 µA 1, 2, 3 All 2.4 V IIL VIN = 0.45 V 1, 2, 3 All -500 µA IIL1 VIN = 0.45 V 1, 2, 3 All -15 mA IIL2 XTAL1 = VSS, VIN = 0.45 V 1, 2, 3 All -4.5 mA ILI 0.45 V < VIN < VCC 1, 2, 3 All ±125 µA IIH VIN = 2.4 V 1, 2, 3 All 500 µA IIH1 VIN < (VCC –1.5 V) 1, 2, 3 All 500 µA Power supply current ICC 1, 2, 3 All 275 mA Capacitance of I/O buffers CI/O All outputs disconnected, EA = VCC fc = 1 MHz, TC = +25°C See 4.3.1c 4 All 30 pF IOL = 2.4 mA V 0.45 V 0.60 V 0.45 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol Oscillator period High time 1/ 3/ tCLCL tCHCX Low time 1/ 3/ tCLCX Rise time 1/ 3/ tCLCH Fall time 1/ 3/ tCHCL ALE pulse width tLHLL Address valid to ALE Address hold after ALE ALE to valid instr in ALE to PSEN Conditions -55°C ≤ TC ≤ +125°C VCC = 5.0 V ±10% unless otherwise specified tAVLL tLLAX tLLIV tLLPL PSEN to valid instr in Input instr hold after PSEN Input instr float after PSEN 1/ PSEN to address valid tPLIV Device type Limits Max Min Max 01 125 286 tCLCL tCLCL 02 83 286 tCLCL tCLCL 9, 10, 11 All 20 9, 10, 11 All 20 9, 10, 11 All All 9, 10, 11 01 195 02 112 01 70 02 28 01 75 02 33 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 20 335 02 168 01 85 02 43 01 300 02 175 210 02 85 All tPXIZ 9, 10, 11 01 90 02 48 0 100 02 58 20 ns ns ns ns 4tCLCL -165 4tCLCL -165 tCLCL -40 tCLCL -40 3tCLCL -75 3tCLCL -75 01 01 ns 2tCLCL -55 2tCLCL -55 tCLCL -55 tCLCL -55 tCLCL -50 tCLCL -50 9, 10, 11 9, 10, 11 ns 20 20 01 ns 3tCLCL -165 3tCLCL -165 0 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 tCLCL -35 tCLCL -35 DSCC FORM 2234 APR 97 84190 D ns ns SIZE REVISION LEVEL ns ns tCLCL -25 tCLCL -25 A ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING ns ns 20 9, 10, 11 9, 10, 11 20 tPXIX tPXAV Unit Limits 2/ Min 9, 10, 11 CL (Port 0, ALE, PSEN) = 100 pF CL (all others) = 80 pF fMAX = 8 MHz device 01 fMAX = 12 MHz device 02 See figures 3 and 4 4/ tPLPH PSEN pulse width Group A subgroups SHEET 6 TABLE I. Electrical performance characteristics - Continued Test Symbol Conditions -55°C ≤ TC ≤ +125°C VCC = 5.0 V ±10% unless otherwise specified Group A subgroups Device type Limits Min Address to valid instr in Address float to PSEN 1/ RD pulse width WR pulse width Address hold after ALE tAVIV tAZPL tRLRH 9, 10, 11 CL (Port 0, ALE, PSEN) = 100 pF CL (all others) = 80 pF fMAX = 8 MHz device 01 fMAX = 12 MHz device 02 See figures 3 and 4 4/ tWLWH tLLAX RD to valid data in Data hold after RD Data float after RD 1/ ALE to valid data in Address to valid data in tRLDV Address to WR or RD Data valid to WR transition 01 460 02 252 0 ns 9, 10, 11 01 650 ns 02 400 01 650 02 400 01 75 02 33 6tCLCL -100 6tCLCL -100 6tCLCL -100 6tCLCL -100 tCLCL -50 tCLCL -50 9, 10, 11 9, 10, 11 9, 10, 11 01 440 02 232 tRHDZ 9, 10, 11 01 165 02 82 01 830 02 496 01 940 02 565 tAVWL tQVWX 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 0 ns ns 5tCLCL -185 5tCLCL -185 0 01 310 440 02 185 315 01 355 02 188 01 40 02 0 3tCLCL -65 3tCLCL -65 4tCLCL -145 4tCLCL -145 tCLCL -85 tCLCL -85 2tCLCL -85 2tCLCL -85 8tCLCL -170 8tCLCL -170 9tCLCL -185 9tCLCL -185 3tCLCL +65 3tCLCL +65 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 D ns ns ns ns 84190 REVISION LEVEL ns ns SIZE A ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING ns 0 All tAVDV Max 5tCLCL -165 5tCLCL -165 All 9, 10, 11 tLLDV Min 9, 10, 11 tRHDX tLLWL ALE to WR or RD Max Unit Limits 2/ SHEET 7 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions -55°C ≤ TC ≤ +125°C VCC = 5.0 V ±10% unless otherwise specified Group A subgroups Device type Limits Min Data setup to WR high tQVWH Data held after WR RD low to address float 1/ RD or WR high to ALE high tWHQX tRLAZ 9, 10, 11 CL (Port 0, ALE, PSEN) = 100 pF CL (all others) = 80 pF fMAX = 8 MHz device 01 fMAX = 12 MHz device 02 See figures 3 and 4 4/ tWHLH Max 01 800 02 508 01 60 02 18 9, 10, 11 All 0 9, 10, 11 01 60 190 02 18 148 9, 10, 11 Unit Limits 2/ Min 7tCLCL -75 7tCLCL -75 tCLCL -65 tCLCL -65 Max ns ns 0 tCLCL -65 tCLCL -65 ns tCLCL +65 tCLCL +65 ns 1/ Tested only initially and after any design changes. 2/ Variable oscillator equations provided for design purposes. 3/ Required external clock drive characteristics (XTAL2). 4/ AC testing: Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at 2.0 V for a logic “1” and 0.8 V for a logic “0”. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 8 Device types Case outline Terminal numbers 1 Terminal symbols P1.0 All Q Terminal numbers 21 Terminal symbols P2.0 2 P1.1 22 P2.1 3 P1.2 23 P2.2 4 P1.3 24 P2.3 5 P1.4 25 P2.4 6 P1.5 26 P2.5 7 P1.6 27 P2.6 8 P1.7 28 P2.7 9 RST 29 PSEN 10 P3.0/RXD 30 ALE/PROG 11 P3.1/TXD 31 EA/VPP 12 P3.2/INT0 32 P0.7 13 P3.3/INT1 33 P0.6 14 P3.4/T0 34 P0.5 15 P3.5/T1 35 P0.4 16 P3.6/WR 36 P0.3 17 P3.7/RD 37 P0.2 18 XTAL2 38 P0.1 19 XTAL1 39 P0.0 20 VSS 40 VCC FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 9 Device types Case outline Terminal numbers 1 Terminal symbols NC All Y Terminal numbers 23 Terminal symbols NC 2 P1.0 24 P2.0 3 P1.1 25 P2.1 4 P1.2 26 P2.2 5 P1.3 27 P2.3 6 P1.4 28 P2.4 7 P1.5 29 P2.5 8 P1.6 30 P2.6 9 P1.7 31 P2.7 10 RST 32 PSEN 11 P3.0/RXD 33 ALE/PROG 12 NC 34 NC 13 P3.1/TXD 35 EA/VPP 14 P3.2/INT0 36 P0.7 15 P3.3/INT1 37 P0.6 16 P3.4/T0 38 P0.5 17 P3.5/T1 39 P0.4 18 P3.6/WR 40 P0.3 19 P3.7/RD 41 P0.2 20 XTAL2 42 P0.1 21 XTAL1 43 P0.0 22 VSS 44 VCC NC = No connection FIGURE 1. Terminal connections – Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 10 FIGURE 2. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 11 FIGURE 3. AC timing circuits. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 12 FIGURE 4. Clock waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 13 PROGRAMMING FIGURE 5. Programming logic. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 14 PROGRAM VERIFICATION FIGURE 5. Programming logic – Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 15 SECURITY BIT PROGRAMMING FIGURE 5. Programming logic – Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 16 FIGURE 6. Programming waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 17 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps. (1) Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.10.2). The remaining cells shall provide a worst case speed pattern. (2) Bake, unbiased, for 72 hours at +140°C to screen for data retention lifetime. (3) Perform a margin test using Vm = +5.9 V at +25°C using loose timing (i.e., TACC = 1 µs). (4) Perform dynamic burn-in (see 4.2a). (5) Margin at Vm = 5.9 V. (6) Perform electrical tests (see 4.2). (7) Erase (see 3.10.1), except devices submitted for groups A, B, C, and D testing. (8) Verify erasure (see 3.10.3). 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 shall be measured only for the initial test and after process or design changes which may affect input capacitance. A minimum sample size of 5 devices with zero failures shall be required. d. All devices selected for testing shall have the EPROM programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified (except devices submitted for groups C and D testing). e. Subgroups 7 and 8 shall consist of verifying the EPROM pattern specified and the instruction set. The instruction set forms a part of the vendors test tape and shall be maintained and available from the approved source of supply. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 18 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) Group A test requirements (method 5005) Groups C and D end-point electrical parameters (method 5005) Subgroups (in accordance with MIL-STD-883, method 5005, table I) 1/ 2/ 3/ 4/ --1*, 2, 3, 7, 9 1, 2, 3, 7, 8, 9, 10, 11 2, 8A, 10 or 1, 2, 3 1/ * PDA applies to subgroup 1. 2/ Any or all subgroups may be combined when using a high speed tester. 3/ Subgroups 7 and 8 shall consist of verifying the EPROM pattern specified and the instruction set. 4/ For all electrical tests, the device shall be programmed to the pattern specified (see 4.3.1d). 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA = +125°C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. (4) All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified. 4.4 Erasing procedure. The device is erased by exposure to high intensity short wave ultraviolet light at a wavelength 2 of 253.7 mm. The recommended integrated dose (i.e., UV intensity X exposure time) is 15 W-s/cm . An example of an ultraviolet source which can erase the device in 30 minutes is the Model S52 short wave ultraviolet lamp. The lamp should be used without short wave filters and the EPROM should be placed about 1 inch from the lamp tubes. After erasures, all bits are in the high state. 4.5 Programming procedures for method A. The programming characteristics in table III and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration (see figure 5) for programming the waveforms of figure 6 and programming characteristics of table III shall apply. b. Initially and after each erasure, all bits are in the high “H” state. Information is introduced by selectively programming “L” into the desired bit locations. A programmed “L” can be changed to an “H” by ultraviolet light erasure (see 4.4). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 19 TABLE III. Programming characteristics. Parameter Programming supply voltage Programming current Oscillator frequency Symbol VPP IPP 1/tCLCL tAVGL Conditions VCC = 5.0 V ±10% TC = +25°C Min 20.5 Max 21.5 30.0 6.0 4.0 48tCLCL Units V mA MHz ns Address setup to PROG tGHAX 48tCLCL ns tDVGL 48tCLCL ns tGHDX 48tCLCL ns tEHSH 48tCLCL ns tSHGL 10.0 µs tGHSL 10.0 µs tGLGH 45.0 Address hold after PROG Data setup to PROG Data hold after PROG ENABLE high to VPP VPP setup to PROG VPP hold after PROG PROG width Address to data valid tAVQV tELQV 55.0 ms 48tCLCL 48tCLCL ns ns 48tCLCL ns ENABLE to data valid 0 tEHQZ Data float after ENABLE 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0547. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 20 6.6 Symbols, definitions, and functional descriptions. The symbol, definitions, and functional description for this device shall be as follows: Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order address and data bus during accesses to external memory. It also receives the instruction bytes during EPROM programming, and outputs instruction bytes during program verification. (External pull-ups are required during program verification). Port 0 can sink (and in bus operations can source) eight LS TTL inputs. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. It receives the low-order address byte during EPROM programming and program verification. Port 1 can sink/source four LS TTL inputs. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. It emits the high-order address byte during accesses to external memory. It also receives the high-order address bits during EPROM programming and program verification. Port 2 can sink/source four LS TTL inputs. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. It also serves the functions of various special features as listed below: Port pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate function RXD (serial input port) TXD (serial output port) INT0 (external interrupt) INT1 (external interrupt) T0 (timer/counter 0 external input) T1 (timer/counter 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) Port 3 can sink/source four LS TTL inputs RST A high on this pin for two machine cycles while the oscillator is running resets the device. A small external pulldown resistor (8.2 kΩ) from RST to VSS permits power-on reset when a capacitor (10 µF) is also connected from this pin to VCC. ALE/PROG Address latch enable output for latching the low byte of the address during accesses to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during external data memory access at which time one ALE pulse is skipped. ALE can sink/source 8 LS TTL inputs. This pin is also the program pulse input (PROG) during EPROM programming. PSEN Program store enable output is the read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. (However, even when executing out of external program memory two activations of PSEN are skipped during each access to external data memory). PSEN is not activated during fetches from internal program memory. PSEN can sink/source 8 LS TTL inputs. EA/VPP When EA is held high, the device executes out of internal program memory (unless the program counter exceeds 0FFFH). When EA is held low, the device executes only out of external program memory. This pin also receives the 21 V programming supply voltage (VPP) during EPROM programming. This pin should not be floated during normal operation. XTAL1 Input to the inverting amplifier that forms the oscillator, XTAL1 should be grounded when an external oscillator is used. XTAL2 Output of the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external oscillator signal when an external oscillator is used. 6.7 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 84190 A REVISION LEVEL D SHEET 21 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 01-12-03 Approved sources of supply for SMD 84190 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ 8419001QA 8419001YX 8419002QX Vendor CAGE number 3V146 3/ 3/ Vendor similar PIN 2/ MD8751H-8/BQA MR8751H-8B 8751H/BQA 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ No approved source of supply. Vendor CAGE number 3V146 Vendor name and address Rochester Electronics Inc. 10 Malcolm Hoyt Drive Newburyport, MA 01950 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.