3.3V 12BIT 2MSPS DAC
dac1330x
GENERAL DESCRIPTION
FEATURES
The dac1330x is a CMOS 12-bit D/A converter for
general applications. The maximum conversion rate of
dac1330x is 2MSPS and supply voltage is 3.3V.
•
•
•
•
•
TYPICAL APPLICATIONS
Resolution : 12Bit
Differential Linearity Error : ± 1.0 LSB
Integral Linearity Error : ± 4.0 LSB
Settling Time : 500ns
Low Power Consumption : 2.9mA
(including Analog, Digital and Reference current)
• Hard Disk Drive (HDD)
• Motor Control Systems
• General Applications
• Power Down Mode
• Operation Temperature Range : -40 ~ 85ºC
• Power Supply : 3.3V Single
FUNCTIONAL BLOCK DIAGRAM
AVDD33A
AVSS33A
AVDD33D
AVSS33D
AVBB
12
D[11:0]
N
M
SEL
1-of-2N 1-of-2M
Decoder Decoder
Dout
SW
Dout
2N
2M
SELB
_
VRT
VRB
PWDNA
AMP
R-String
SW
+
PWDN
SEL
CNTRL
NOBUF
SELB
PWDNA
BIAS GEN
NBIAS
Ver 1.0 (May 2002)
This datasheet is a preliminary version. No responsibility is
assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The
content of this datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
VOUT
dac1330x
3.3V 12BIT 2MSPS DAC
CORE PIN DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
D[11:0]
DI
phicc_abb
Digital Input Data (12bit)
D[11] : MSB , D[0] : LSB
PWDN
DI
phicc_abb
Power Down (Active High)
NOBUF
AB
phia_abb
Buffer Mode Selection
NOBUF=0 : Normal Operation
NOBUF=1 : Amp → power down
VOUT = R-string output
VRT
AB
phia_abb
Voltage Reference Top (3.25V)
VRB
AB
phia_abb
Voltage Reference Bottom (0.05V)
VOUT
AO
phoa_abb
Analog Voltage Output
NBIAS
AB
phoa_abb
Bias Generator Output
AVDD33A
AP
AVSS33A
AG
AVDD33D
DP
AVDD33D
DG
vssth_abb
Digital Ground (0.0V)
AVBB
AG
vbbh_abb
Analog Sub Bias (0.0V)
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP
DP
AG
DG
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
vdd33th_abb Analog Power (+3.3V)
vssth_abb
Analog Ground (0.0V)
vdd33th_abb Digital Power (+3.3V)
CORE CONFIGURATION
AVDD33A AVSS33A AVDD33D AVSS33D
AVBB
D[11:0]
dac1330x
VOUT
PWDN
VRT
SEC ASIC
VRB
NOBUF
2 / 11
NBIAS
ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
VDD (AVDD33A,AVDD33D)
4.5
V
Analog Output Voltage
VOUT
AVSS33A to AVDD33A
V
Digital Input Voltage
D[11:0]
AVSS33D to AVDD33D
V
Reference Voltage
VRT
VRB
AVDD33A
AVSS33A
V
Operating Temperature Range
Topr
-40 to 85
°C
Supply Voltage
NOTES :
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition
value is applied with the other values kept within the following operating conditions and function operation under any
of these conditions is not implied.
2. All voltages are measured with respect to VSS(AVSS33A or AVSS33D or AVBB33A or AVBB33D)
unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage
AVDD33A - AVSS33A
AVDD33D - AVSS33D
3.0
3.3
3.6
V
Supply Voltage Difference
AVDD33A - AVDD33D
-0.1
0.0
0.1
V
Reference Voltage
VRT
VRB
AVSS33A
3.25
0.05
AVDD33A
-
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
0.7×VDD
-
0.3×VDD
-
V
Operating Temperature
Topr
-40
-
85
°C
Characteristics
NOTE :
1. It is strongly recommended that to avoid power latch-up all the supply pins (AVDD33A , AVDD33D)
be driven from the same source.
2. Digital Input : VDD → AVDD33D
SEC ASIC
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ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD33D=AVDD33A=3.3V, AVSS33D=AVSS33A=AVBB=0V,
PWDN=Low, NOBUF=Low, Top=25°C, VRT=3.25V, VRB=0.05V unless otherwise specified.)
Symbol
Min
Typ
Max
Unit
Bit
-
12
-
Bits
-
Differential Linearity Error
DLE
-
±1
-
LSB
-
Integral Linearity Error
ILE
-
±4
-
LSB
-
Zero Scale Error1
VZSE
-
±15
-
mV
Full Scale Voltage Error2
VFSE
-
±15
-
mV
Maximum Output Voltage
VoMAX
-
3.249
-
V
VLSB
-
0.781
-
mV
Characteristics
Resolution
LSB Size
NOTE
Conditions
-
VoMAX = VOUT(D[11:0]=High)
VLSB = (VoMAX - VOUT(D[11:0]=Low)) / 4095
1 : VZSE=VOUT(D[11:0]=Low) - VRB
2 : VFSE=VOUT(D[11:0]=High) - {(VRT-VRB) × 4095/4096 + VRB}
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD33D=AVDD33A=3.3V, AVSS33D=AVSS33A=AVBB=0V, Load Capacitance ≤ 25pF
PWDN=Low, NOBUF=Low, Top=25°C, VRT=3.25V, VRB=0.05V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Supply Current
(Average Current)
Ivdd1
-
2
-
mA
Ivdd1 = IAVDD33A + IAVDD33D
Data Rate = 2MHz
Supply Current
(Power Down Mode)
Ivdd2
-
-
10
uA
Ivdd2 = IAVDD33A + IAVDD33D
Data Input : All Low or All High
PWDN=HIGH
Reference Current
IVRT
-
0.9
-
mA
Analog Output Delay
td
-
100
-
ns
Data Rate = 2MHz
Data : All LOW → All HIGH
Analog Output Rise Time
tr
-
130
-
ns
Data Rate = 2MHz
Data : All LOW → All HIGH
Analog Output Fall Time
tf
-
120
-
ns
Data Rate = 2MHz
Data : All HIGH → All LOW
Analog Output
Settling Time
tset
-
500
-
ns
Data Rate = 2MHz
Data : All LOW → All HIGH
Power Down On Time
ton
-
1
-
us
PWDN : LOW → HIGH
Power Down Off Time
toff
-
1
-
us
PWDN : HIGH → LOW
SEC ASIC
4 / 11
ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
TIMING DIAGRAM
Digital Input
(D[11:0])
111111111111
000000000000
111111111111
(< ± 0.5 LSB)
90%
Analog Output
(VOUT)
50%
td
10%
tset
tr
tf
50%
50%
PWDN
(< ± 0.5 LSB)
Analog Output
(VOUT)
(< ± 0.5 LSB)
ton
0.0V
toff
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The dac1330x has a 12bit R-string block, two decoders, and an OP amp.
2. The digital outputs of two decoders decide the voltage level of R-string block.
VRT − VRB 12
VRstring =
12
∑
2
n=0
(2 × D[n])+ VRB
n
3. The VOUT pin is dependent of digital input values.
4. Power Down Mode reduces only analog currents (IAVDD33A) and reference current (IVRT) is always dissipated.
SEC ASIC
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ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
CORE EVALUATION GUIDE
HOST
DSP
CORE
12
12
MUX
TEST PATH
12
Cc
Ct
3.3V GND 3.3V GND
Cc
Ct
AVDD33D AVSS33D AVDD33A AVSS33A
D[11:0]
AVBB
NBIAS
dac1330x
VRB
Ct
NOBUF
PWDN
VRT
Ct
Cc
0.05V GND
Cc
3.25V GND
floated
In normal condition
VOUT
VOUT
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
TESTABILITY
Whether you use MUX or the internal logic for testability, it is required to be able to select
the values of digital inputs ( D[11:0] ).
See above figure. Only if it is, you can check the main function. ( Linearity )
Normal Test Condition : VRT=3.25V , VRB=0.05V , PWDN=Low , NOBUF = Low
SEC ASIC
6 / 11
ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
PHANTOM CELL INFORMATION
NOBUF
NBIAS
AVDD33A
AVSS33A
AVBB
AVDD33A
AVSS33A
AVBB
VOUT
dac1330x
Property
Pin Usage
D[11:0]
DI
Internal / External
PWDN
DI
Internal / External
NOBUF
DI
Internal / External
VRT
AB
External
VRB
AB
External
VOUT
AO
Internal / External
NBIAS
AB
External / Floated
AVDD33A
AP
External
AVSS33A
AG
External
AVDD33D
DP
External
AVSS33D
DG
External
AVBB
AG
External
VRT
Pin Name
VRB
AVSS33D
PWDN
D[11:0]
AVDD33D
Pin Layout Guide
1. Digital Input Signal lines must have same length to
reduce propagation delay.
1. Voltage reference lines (VRT and VRB) must be wide metal
to reduce voltage drop of metal lines.
2. VOUT signal should not be crossed by any signals and
should not run next to digital signals to minimize capacitive
coupling between the two signals.
1. It is recommended that you use thick analog power metal.
When connected to PAD, the path should be kept as short
as possible.
2. Digital power and analog power are separately used.
1. When the core block is connected to other blocks, it must be double guard-ring using N-well and
P+ active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
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ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
PACKAGE CONFIGURATION
1
NC
NC
48
2
NC
NC
47
3
NC
NC
46
4
NC
NC
45
5
NC
NC
44
6
NC
NC
43
7
NC
AVDD33D
42
D[11]
8
D[11]
AVSS33D
41
D[10]
9
D[10]
AVBB
40
D[9]
10
D[9]
AVSS33A
39
D[8]
11
D[8]
AVSS33A
38
D[7]
12
D[7]
AVDD33A
37
+
Ct
Cc
13
D[6]
D[5]
14
D[5]
D[4]
15
D[4]
D[3]
16
D[2]
DAC1330X
D[6]
L2
L1
(VSS)
0.0V
Ct
+
Cc
AVDD33A
36
NC
35
NC
34
D[3]
NC
33
17
D[2]
NC
32
D[1]
18
D[1]
NC
31
D[0]
19
D[0]
NC
30
PWDN
20
PWDN
NC
29
21
NC
NC
28
NOBUF
22
NOBUF
VOUT
27
NBIAS
23
NBIAS
NC
26
24
VRB
VRT
25
3.3V
(VDD)
(0.0V in normal operation)
(0.0V in normal operation)
VRB
(0.05V Typ.)
+
Cc
Ct
SEC ASIC
VOUT
(3.25V Typ.)
Ct
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
L1~L2
FERRITE BEAD ( 0.1mh )
8 / 11
VRT
+
Cc
ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
PACKAGE PIN DESCRIPTION
NAME
PIN NO
I/O TYPE
PIN DESCRIPTION
D[11:0]
8~19
DI
Digital Input Data
PWDN
20
DI
Power Down Mode (Active High)
NOBUF
21
DI
NOBUF Mode
NOBUF=0 : Normal Operation
NOBUF=1 : R-string Output → VOUT
Amp → Power Down
NBIAS
23
AB
Bias Generator Output (floated in normal operations)
VRB
24
AB
Voltage Reference Bottom (0.05V)
VRT
25
AB
Voltage Reference Top (VDD-0.05V)
VOUT
27
AO
Analog Voltage Output
AVDD33A
36,37
AP
Analog Power (3.3V)
AVSS33A
38,39
AG
Analog Ground (0.0V)
AVBB
40
AG
Analog Sub Bias (0.0V)
AVSS33D
41
DG
Digital Ground (0.0V)
AVDD33D
42
DP
Digital Power (3.3V)
NC
1,2,3,4,5,6,7,21
26,28,29,30,31
32,33,34,35,43
44,45,46,47,48
AO
No Connection
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP :
DP :
AG :
DG :
Analog Power
Digital Power
Analog Ground
Digital Ground
SEC ASIC
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ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
PC BOARD LAYOUT CONSIDERATION
1. PC Board Considerations
To minimize noise on the power lines and the ground lines, the digital inputs
need to be shielded and decoupled. This trace length between groups
of VDD (AVDD33A, AVDD33D) and VSS (AVSS33A, AVSS33D) pins should be as short as possible
so as to minimize inductive ringing.
2. Supply Decoupling and Planes
For the decoupling capacitor between the power line and the ground line, 0.1uF
ceramic capacitor is used in parallel with a 10uF tantalum capacitor.
The digital power plane(AVDD33D) and analog power plane(AVDD33A) are connected
through a ferrite bead, and also the digital ground plane(AVSS33D) and the analog
ground plane(AVSS33A). This ferrite bead should be located within 3inches of
the DAC1330X. The analog power plane supplies power to the DAC1330X of
the analog output pin and related devices.
SEC ASIC
10 / 11
ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
FEEDBACK REQUEST
We appreciate your interest in out products.
If you have further questions, please specify in the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
°C
Output Load Capacitor
pF
Output Load Resistor
kΩ
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
Digital Input Format
V
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
-
Analog Output Maximum Current
mA
Analog Output Maximum Signal Frequency
kHz
Reference Voltage
V
External Resistor for Current Setting(RSET)
kΩ
Pipeline Delay
sec
Do you want to Power down mode?
Do you want to Internal Reference Voltage(BGR)?
Which do you want to serial input data type or parallel input data type?
Do you need 5V power supply in your system?
SEC ASIC
11 / 11
ANALOG
dac1330x
3.3V 12BIT 2MSPS DAC
HISTORY CARD
Version
Ver 1.0
Date
Modified Items
Comments
02.05.14 Preliminary Version
SEC ASIC
ANALOG