AMD AM79D2251JC

Intelligent Access™ Voice Solutions
Am79D2251
Dual Intelligent Subscriber Line Audio-Processing Circuit (ISLAC)
DISTINCTIVE CHARACTERISTICS
■ High performance digital signal processor
provides programmable control of all major
linecard functions
— 32 and 24 kb/s ADPCM to G726, as well as
A-law/µ-law and linear codec
— Transmit and receive gain
— Two-wire AC impedance
— Transhybrid balance
— Equalization
— DC loop feeding
— Tone generation
— Metering generation at 12 kHz and 16 kHz
— Envelope shaping and level control
■ Selectable PCM/MPI or GCI digital interfaces
— Supports most available master clock
frequencies from 512 kHz to 8.196 MHz
■ 0 to 70°C commercial operation
— –40°C to 85°C extended temperature range
available
■ +3.3 V DC operation
— Smooth or abrupt polarity reversal
— Loop supervision
— Off-hook debounce circuit
— Ground-key and ring-trip filters
— Ringing generation and control
■ Exceeds LSSGR and ITU requirements
■ Supports external ringing with on-chip ring-trip
circuit
— Automatic or manual ring-trip modes
■ DTMF detection according to Q.24
— Adaptive hybrid balance
■ 2100 Hz modem tone detection according to V.25
— Line and circuit testing
BLOCK DIAGRAM
7
A1
4
VCCA
LD1
ISLIC
VCCD
VREF
B1
DGND1
RC
Networks
and
Protection
AGND1
DGND2
AGND2
TSCA/G
A2
3
P1-P3
7
DRA/DD
ISLIC
LD2
B2
RREF
5
Ring-Trip
Sense
Resistors
Dual
ISLAC
DXA/DU
DCLK/S0
PCLK/FS
5
MCLK
RSHB
BATH
RSLB
FS/DCL
CS/RST
BATL
DIO/S1
RSPB
BATP
INT
Pub. # 22829 Rev: C Amendment: /0
Issue Date: December 1999
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Distinctive Characteristics of The Intelligent Access™ Voice chipset . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Intelligent Access™ Voice Chipsets Environmental Ranges . . . . . . . . . . . . . . . . . . . . 14
Electrical Maximum Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Intelligent Access™ Voice Chipsets System Target Specifications . . . . . . . . . . . . . . . . . . . 15
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transmission and Signaling Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transmit and Receive Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Gain Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Total Distortion Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PCM Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GCI Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision A to Revision B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision B to Revision C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
Am79D2251
The dual ISLAC device, in combination with an ISLIC™ device, implements a two channel
universal telephone line interface. This enables the design of a single, low cost, high performance,
fully software programmable line interface for multiple country applications worldwide. All AC, DC,
and signaling parameters are fully programmable via microprocessor or GCI interfaces. Additionally,
the dual ISLAC device has integrated self-test and line-test capabilities to resolve faults to the line
or line circuit. The integrated test capability is crucial for remote applications where dedicated test
hardware is not cost effective.
DISTINCTIVE CHARACTERISTICS OF THE INTELLIGENT ACCESS™ VOICE CHIPSET
■ Performs all battery feed, ringing, signaling,
hybrid and test (BORSCHT) functions
■ Exceeds LSSGR and CCITT central office
requirements
■ Two chip solution supports high density, multichannel architecture
■ Selectable PCM or GCI interface
■ Single hardware design meets multiple country
requirements through software programming
of:
— Ringing waveform and frequency
— Supports most available master clock
frequencies from 512 kHz to 8.192 MHz
■ On-hook transmission
■ Power/service denial mode
— DC loop-feed characteristics and current-limit
■ Line-feed characteristics independent of battery
voltage
— Loop-supervision detection thresholds
■ Only 5 V, 3.3 V and battery supplies needed
— Off-hook debounce circuit
■ Low idle-power per line
— Ground-key and ring-trip filters
■ Linear power-feed with intelligent powermanagement feature
— Off-hook detect de-bounce interval
— Two-wire AC impedance
■ Compatible with inexpensive protection
networks; Accommodates low-tolerance fuse
resistors while maintaining longitudinal balance
— Transhybrid balance
— Transmit and receive gains
— Digital I/O pins
■ Monitors two-wire interface voltages and
currents for subscriber line diagnostics
— A-law/µ-law and linear selection
■ Built-in voice-path test modes
— Equalization
■ Supports internal and external battery-backed
ringing
— Self-contained ringing generation and control
■ Power-cross, fault, and foreign voltage
detection
■ Integrated line-test features
— Supports external ringing generator and ring
relay
— Leakage
— Ring relay operation synchronized to zero
crossings of ringing voltage and current
— Loop resistance
— Integrated ring-trip filter and software enabled
manual or automatic ring-trip mode
■ Supports metering generation with envelope
shaping
■ Smooth or abrupt polarity reversal
■ Adaptive transhybrid balance
— Continuous or adapt and freeze
■ Supports both loop-start and ground-start
signaling
— Line and ringer capacitance
■ Integrated self-test features
— Echo gain, distortion, and noise
■ 0 to 70°C commercial operation
— –40°C to 85°C extended temperature range
available
■ Small physical size
■ Up to three relay drivers per ISLIC™ device
— Configurable as test load switches
Am79D2251
3
Figure 1. Dual ISLAC Block Diagram
IREF
VHL1
Clock and
Reference
Circuits
VLB1
VOUT1
VINI1
VSAB1
VIMT1
VREF
Ch 1
Converter
Block
PCM
and
GCI
Interface
and
Time Slot
Assigner
VILG1
XSB1
MCLK
FS/DCL
PCLK/FS
DXA/DU
DRA/DD
TSCA/G
VHL2
DCLK/S0
VLB2
VOUT2
VINI2
VSAB2
VIMT2
Ch 2
Converter
Block
Digital
Signal
Processor
GCI Control
Logic and
Microprocessor
Interface
DIO/S1
CS/RST
INT
VILG2
XSB2
LD1
ISLIC
Control
Logic
LD2
P1
P2
P3
Common
External
Sense
Inputs
4
Am79D2251
XSC
SHB
SLB
SPB
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The ordering
number (valid combination) is formed by a combination of the elements below. Two ISLIC devices
need to be used with this part.
Am79D2251
J
C
TEMPERATURE RANGE
C= Commercial (0°C to +70°C)
PACKAGE TYPE
J = 44-pin plastic leaded chip carrier (PL044)
V = 44-pin thin plastic quad flat pack (PQT044)
DEVICE NAME/DESCRIPTION
Am79D2251
Advanced Dual Intelligent Subscriber Line AudioProcessing Circuit
Valid Combinations
Valid Combinations
Am79D2251
JC
Am79D2251
VC
Valid combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability
of specific valid combinations, and to check on
newly released valid combinations.
Am79D2251
5
CONNECTION DIAGRAMS
XSC
VREF
IREF
XSB1
VLB1
VIMT1
5
SHB
6
SLB
VLB2
XSB2
VIMT2
Figure 2. 44-Pin PLCC Connection Diagram
3
2
1
44
43
42
41
40
4
AGND1
7
39
AGND2
VILG2
8
38
VILG1
VSAB2
9
37
VSAB1
VCCA2
10
36
VCCA1
VHL2
11
35
VHL1
VIN2
12
34
VIN1
VOUT2
13
33
VOUT1
SPB
14
32
DGND2
DGND1
15
31
LD1
LD2
16
30
CS/RST
P3
17
29
DCLK/S0
23
24
25
26
27
28
FS/DCL
DRA/DD
DXA/DU
TSCA/G
DIO/S1
22
PCLK/FS
21
MCLK
INT/S2
P1
19 20
P2
18
VCCD
Dual ISLAC
44-Pin PLCC
6
VIMT2
VLB2
XSB2
SLB
SHB
XSC
VREF
IREF
XSB1
VLB1
VIMT1
Figure 3. 44-Pin TQFP Connection Diagram
44
43
42
41
40
39
38
37
36
35
34
AGND1
1
33
AGND2
VILG2
2
32
VILG1
VSAB2
3
31
VSAB1
VCCA2
4
30
VCCA1
VHL2
5
29
VHL1
VIN2
6
28
VIN1
VOUT2
7
27
VOUT1
SPB
8
26
DGND2
DGND1
9
25
LD1
LD2
10
24
CS/RST
P3
11
23
DCLK/S0
19
20
21
22
DIO/S1
MCLK
18
TSCA/G
INT/S2
17
DXA/DU
P1
16
DRA/DD
15
FS/DCL
14
VCCD
13
PCLK/FS
12
P2
Dual ISLAC
44-Pin TQFP
Am79D2251
PIN DESCRIPTIONS
Pin
Pin Name
I/O
Description
AGND1,
AGND2
Analog Ground
O
Analog circuitry ground returns
DCLK/S0
Data Clock/GCI
Address Strap 0
I
Provides data control for MPI interface control. For GCI operation, this pin is device address
bit 0. 5 V tolerant.
DGND1–
DGND2
Digital Ground
DIO/S1
Data I/O/GCI Address
Strap 1
I/O
For PCM backplane operation, control data is serially written into and read out of the ISLAC
device via the DIO pin with the MSB first. The data clock (DCLK) determines the data rate.
DIO is high impedance except when data is being transmitted from the ISLAC device under
control of CS/RST. For GCI operation, this pin is device address bit 1. 5 V tolerant.
DRA/DD
RX Path A Backplane
Data/ GCI data
Downstream, Receive
Path B backplane data
I
For the PCM highway, the receive PCM data is input serially through the DRA ports. The
data input is received every 125 µs and is shifted in, MSB first, in 8-bit PCM or 16-bit linear
bursts at the PCLK rate. The receive port can receive information for direct control of the
ISLIC device. This mode is selected in Device Configuration Register 2 (RTSEN = 1,
RTSMD = 1). When selected, this data is received in an independently programmable
timeslot from the PCM data. For the GCI mode, downstream receive and control data is
accepted on this pin. 5 V tolerant.
DXA/DU
TX Path A Backplane
Data/GCI Data
Upstream, TX Path B
Backplane Data
O
For the PCM highway, the transmit PCM data is transmitted serially through the DXA port.
The transmission data output is available every 125 µs and is shifted out, MSB first, in 8-bit
PCM or 16-bit linear bursts at the PCLK rate. DXA is high impedance between bursts and
while the device is in the inactive mode. Can also select a mode (RTSEN = 1, RTSMD = 1
or 0 in Device Configuration Register 2) that transmits the Signaling Register MSB contents
first, in an independently programmable timeslot from the PCM data. This data is transmitted
in all modes except disconnect. For the GCI mode, upstream transmit and signaling data is
transferred on this pin. 5 V tolerant.
FS/DCL
Frame sync/GCI
Downstream Clock
I
For PCM operation, pin is Frame Sync. PCM operation is selected by the presence of an
8 kHz Frame Sync signal on this pin in conjunction with the PCLK on the PCLK/FS pin
(see below). This 8 kHz pulse identifies the beginning of a frame. The ISLAC device
references individual timeslots with respect to this input, which must be synchronized to
PCLK. GCI operation is selected by the presence of the downstream clock DCL, on this
pin in conjunction with the presence of a FS on the PCLK/FS pin. In GCI mode, the rate
at which data is shifted into or out of the PCM ports is a derivative of this DCL clock as
selected in Device Configuration Register 1. 5 V tolerant.
INT/S2
Interrupt/GCI Address
Strap 2
O
For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to
interrupt a higher level processor. Several registers work together to control operation of
the interrupt: Signaling and Global Interrupt Registers with their associated Mask
Registers, and the Interrupt Register. See the description at configuration register 6 (Mask)
for operation. Logic drive is selectable between open drain and TTL-compatible outputs.
The S2 function is only available on the dual ISLAC device. For GCI operation, it is the
device address bit 2.
IREF
Current Reference
I
External resistor (RREF) connected between this pin and analog ground generates an
accurate, on-chip reference current for the A/D's and D/A's on the ISLAC chip.
LD1–LD2
Register Load
O
The LD pins output 3-level voltages. When LDn is a logic 0, the destination of the code on
P1–P3 is the relay control latches in the ISLIC control register. When LDn is a logic 1, the
destination of P1–P3 is the mode control latches. LDn is driven to VREF when the contents
of the ISLIC control register must not change.
MCLK
Master Clock
I
For PCM backplane operation, a DSP master clock connects here. A signal is required
only for PCM backplane operation when PCLK is not used as the master clock. MCLK can
be a wide variety of frequencies. Upon initialization the MCLK input is disabled, and relevant
circuitry is driven by a connection to PCLK. The MCLK connection may be re-established
under user control. 5 V tolerant.
PCLK/FS
PCM Clock/Frame
Sync
I
For PCM operation, this is PCM Clock. PCM operation is selected by the presence of a
PCLK signal on this pin in conjunction with the FS on the FS/DCL pin (see below). For
PCM backplane operation, connect a data clock, which determines the rate at which PCM
data is serially shifted into or out of the PCM ports. PCLK can be any multiple of the FS
frequency. The minimum clock frequency for linear/ companded data plus signaling data
is 256 kHz. For GCI operation, this pin is Frame Sync. The FS signal is an 8 kHz pulse
that identifies the beginning of a frame. The ISLAC device references individual timeslots
with respect to this input, which must be synchronized to DCL. 5 V tolerant.
P1–P3
ISLIC Control
O
Control the operating modes of the two ISLIC devices connected to the dual ISLAC device.
Digital ground returns
Am79D2251
7
Pin
8
I/O
Description
CS/RST
Chip Select/Reset
Pin Name
I
For PCM backplane operation, a logic low on this pin for 15 or more DCLK cycles resets
the sequential logic in the ISLAC device into a known mode. A logic low placed on this pin
for less than 15 DCLK cycles is a chip select and enables serial data transmission into or
out of the DIO port. For GCI operation, a logic low on this pin—for 1 ms or longer—resets
the sequential logic into a known mode. See Table 2-4 in the Technical Reference for
details. 5 V tolerant.
SHB, SLB,
SPB
Battery Sense
I
Resistors that sense the high, low and positive battery voltages connect here. If only one
negative battery is used, connect both resistors at the supply. If the positive battery is not
used, leave the pin unconnected. These pins are current inputs whose voltage is held at
VREF.
TSCA/G,
Timeslot Control A/GCI
Mode, Time Slot
Control B
O
(PCM)
I
(GCI)
For PCM backplane operation, TSCA is active low when PCM data is output on the DXA
pin. The outputs are open-drain and are normally inactive (high impedance). Pull-up loads
should be connected to VCCD. When GCI mode is selected, one of two GCI modes may
be selected by connecting TSCA/G to DGND or VCCD.
VSAB1–
VSAB2
Loop voltage sense
VCCA1–
VCCA2
Power Supply
+3.3 VDC supplies to the analog sections in each of the two channels.
VCCD
Power Supply
+3.3 VDC supply to all digital sections.
VREF
Analog Reference
O
This pin provides a 1.4 V, single-ended reference to the two ISLIC devices to which the
ISLAC device is connected.
VHL1–
VHL2
High Level D/A
O
High-level loop control voltages on these pins are used to control DC-feed, internal ringing,
metering and polarity reversal for each ISLIC device.
VIN1–
VIN2
TX Analog
I
Analog transmit signals (VTX) from each ISLIC device connect to these pins. The ISLAC
device converts these signals to digital words and processes them. After processing, they
are multiplexed into serial time slots and sent out of the DXA/DU pin.
VLB1–
VLB2
Longitudinal
Reference
O
Normally connected to VCCA internally. They supply longitudinal reference voltages to the
ISLIC devices during certain test procedures. These outputs are connected internally to
VCCA during ISLIC Active, Standby, Ringing, and Disconnect modes. During test modes,
it can be connected to the receive D/A.
VIMT1–
VIMT2,
VILG1–
VILG2
Sense
I
The IMT and ILG pins of two ISLIC devices connect to the VIMT1–VIMT4 and VILG1–
VILG4 pins of the ISLAC chip. These pins are voltage inputs referenced to VREF. They
require external resistors connected between each pin and VREF to convert IMTn and
ILGn into voltages.
VOUT1–
VOUT2
RX Analog
O
The ISLAC device extracts and processes voice data from time slots on DRA/DD serial
data port. After processing, the ISLAC device converts the voice data to analog signals
that are sent out of these pins to each respective ISLIC device.
XSB1–
XSB2
External Sense
I
External resistors connect here that sense an external voltage. In a linecard with external
ringing, they are used to sense the voltage at the line side of the ring-feed resistor. These
pins are current inputs whose voltage is held at VREF. An internal resistor converts currents
flowing in these pins into voltages to be sampled by the A/D.
XSC
Common External
Sense
I
An external resistor connects here that senses a common reference for external voltages
sensed by resistors connected to XSB1–XSB4. This pin is a current input whose voltage
is held at VREF. An internal resistor converts current flowing in this pin into a voltage to
be sampled by the A/D. This pin is intended for sensing external ringer supply voltages.
However, it can also be used to sense other test points when internal ringing is used.
I
Connect to the VSAB pins of two ISLIC devices.
Am79D2251
GENERAL DESCRIPTION
The Intelligent Access voice chipsets integrate all functions of the subscriber line for two subscriber
lines. One or more of two chip types are used to implement the linecard; an ISLIC device and a dual
ISLAC device. These provide the following basic functions:
1. The ISLIC device: A high voltage, bipolar IC that drives the subscriber line, maintains
longitudinal balance and senses line conditions.
2. The dual ISLAC device: A low voltage CMOS IC that provides conversion and DSP functions
for 2 channels.
Complete schematics of linecards using the Intelligent Access voice chipsets for internal and external
ringing are shown in Figure 4 and Figure 5.
The ISLIC device uses reliable, bipolar technology to provide the power necessary to drive a wide
variety of subscriber lines. It can be programmed by the ISLAC device to operate in eight different
modes that control power consumption and signaling modes. This enables it to have full control over
the subscriber loop. The ISLIC device is customized to be used exclusively with the ISLAC device
as part of a multiple-line chipset. The ISLIC device requires only +5 V power and the battery supplies
for its operation.
The ISLIC device implements a linear loop-current feeding method with the enhancement of
intelligent thermal management in a controlled manner. This limits the amount of power dissipated
on the ISLIC chip by dissipating excess power in external resistors.
Each ISLAC device contains high-performance codec circuits that provide A/D and D/A conversion
for voice (codec), DC-feed and supervision signals for two subscriber channels. The ISLAC device
contains a DSP core that handles signaling, DC-feed, supervision and line diagnostics for both
channels.
The DSP core selectively interfaces with three types of backplanes:
■ Standard PCM/MPI
■ Standard GCI
■ Modified GCI with a single analog line per GCI channel
The Intelligent Access voice chipset provides a complete software configurable solution to the
BORSCHT functions as well as complete programmable control over subscriber line DC-feed
characteristics, such as current limit and feed resistance. In addition, these chipsets provide system
level solutions for the loop supervisory functions and metering. In total, they provide a programmable
solution that can satisfy worldwide linecard requirements by software configuration.
Software programmed filter coefficients, DC-feed data and supervision data are easily calculated
with the WinSLAC software. This PC software is provided free of charge. It allows the designer to
enter a description of system requirements. WinSLAC then computes the necessary coefficients
and plots the predicted system results.
The ISLIC interface unit inside the ISLAC device processes information regarding the line voltages,
loop currents and battery voltage levels. These inputs allow the ISLAC device to place several key
ISLIC performance parameters under software control.
Am79D2251
9
The main functions that can be observed and/or controlled through the ISLAC backplane interface are:
■ DC-feed characteristics
■ Ground-key detection
■ Off-hook detection
■ DTMF detection
■ Modem tone (2100 Hz) detection
■ Metering signal
■ Longitudinal operating point
■ Subscriber line voltage and currents
■ Ring-trip detection
■ Abrupt and smooth battery reversal
■ Subscriber line matching
■ Ringing generation
■ Sophisticated line and circuit tests
To accomplish these functions, the ISLIC device collects the following information and feeds it, in
analog form, to the ISLAC device:
■ The metallic (IMT) and longitudinal (ILG) loop currents
■ The AC (VTX) and DC (VSAB) loop voltage
The outputs supplied by the ISLAC device to the ISLIC device are then:
■ A voltage (VHLi) that provides control for the following high-level ISLIC device outputs:
—DC loop current
—Internal ringing signal
—12 or 16 kHz metering signal
■ A low-level voltage proportional to the voice signal (VOUTi)
■ A voltage that controls longitudinal offset for test purposes (VLBi)
The ISLAC device performs the codec and filter functions associated with the four-wire section of
the subscriber line circuitry in a digital switch. These functions involve converting an analog voice
signal into digital PCM samples and converting digital PCM samples back into an analog signal.
During conversion, digital filters are used to band-limit the voice signals.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing
function, permit adjustment of the two-wire termination impedance and provide frequency
attenuation adjustment (equalization) of the receive and transmit paths. Adaptive transhybrid
balancing is also included. All programmable digital filter coefficients can be calculated using
WinSLAC software. The PCM codes can be either 16-bit linear two’s-complement or 8-bit
companded A-law or µ-law, with the further option of 32 or 24 kb/s ADPCM compression.
Besides the codec functions, the Intelligent Access voice chipset provides all the sensing, feedback,
and clocking necessary to completely control ISLIC device functions with programmable parameters.
System-level parameters under programmable control include active loop current limits, feed
resistance, and feed mode voltages.
The ISLAC device supplies complete mode control to the ISLIC device using the control bus (P1-P3)
and tri-level load signal (LDi).
The Intelligent Access voice chipset provides extensive loop supervision capability including off-hook,
DTMF, ring-trip and ground-key detection. Detection thresholds for these functions are programmable.
A programmable debounce timer is available that eliminates false detection due to contact bounce.
For subscriber line diagnostics, AC and DC line conditions can be monitored using built in test tools.
Measured parameters can be compared to programmed threshold levels to set a pass/fail bit. The
user can choose to send the actual PCM measurement data directly to a higher level processor by
way of the voice channel. Both longitudinal and metallic resistance and capacitance can be
measured, which allows leakage resistance, line capacitance, and telephones to be identified.
10
Am79D2251
Figure 4. Internal Ringing Linecard Schematic
+5 V
VCC
RSAi
3.3 V
CREF
SA
RRXi
VOUTi
RSN
DGND
RHLai
RFAi
A
CHLbi
AD
RHLbi
VHLi
RHLci
RTESTMi
U3
D1
RTi
RHLdi
CHLdi
AGND
VREF
CADi
VCCA
VSABi
VSAB
CHPi
BATH
VCC
+3.3VDC
VCCD
HPA
CS
DT1i
VTX
VINi
VLB
VLBi
IMT
VIMTi
HPB
D2
U4
CSSi
B
RFBi
BD
RSBi
SB
CBDi
TMS
RMTi
U1
Am79R241
U2
ISLAC
VREF
RMGPi
VILGi
ILG
DT2i***
BACK
PLANE
TMP
RLGi
TMN
VREF
RMGLi
DHi
BATH
VREF
VBH
VREF
DLi
BATL
VBL
LD
LDi
SPB
P1
P1
SLB
P2
P2
P3
P3
GND
CBATHi
CBATLi
RSVD
BATL
RSLB
BATH
SHB
RSHB
RYE
IREF
R2
RREF
RTESTLi
R3
R1
* CSS required for > 2.2 Vrms metering
** Connections shown for one channel
*** DT2i diode is optional - should be
connected if there is a chance that this chip
may be replaced by Am79R251.
BGND
RSVD
Am79D2251
11
Figure 5. External Ringing Linecard Schematic
RSAi
+5 V
3.3 V
VCC
SA
CREF
RRXi
RSN
VOUTi
DGND
RHLai
RFAi
A
1
8
RHLbi
CHLbi
AD
KRi(A)
AGND
VHLi
RHLci
CADi
6
7
RTESTMi
RTi
U5
RHLdi
CHLdi
VREF
VCCA
VSAB
2
CHPi
HPA
VSABi
VTX
VINi
VLB
VLBi
IMT
VIMTi
VCC
+3.3 VDC
VCCD
DT1i
BATH
CS
HPB
CSSi
RFBi
B
KRi (B)
4
5
CBDi
BD
RSBi
RMTi
SB
TMS
U1
Am79231
VREF
VILGi
ILG
U2
ISLAC
RMGPi
DT2i***
RLGi
BACK
PLANE
TMP
VREF
TMN
VREF
VREF
RMGLi
DHi
BATH
VBH
LDi
GND
DLi
BATL
VBL
CBATHi
LD
CBATLi
P1
P1
P2
P2
P3
P3
SPB
SLB
BATL
RSLB
RSVD2
SHB
IREF
R2H
RREF
RTESTLi
R3H
R1
RGFDLi
KRi
+5 V
Ring Bus
BGND
RSVD
* CSS required for > 2.2 Vrms metering
** Connections shown for one channel
*** DT2i is optional - Should be put if there is a chance that
this chip may be replaced by Am79R251.
RSRBi
RSRC
12
BATH
RSHB
RYE
Am79D2251
XSBi
XSC
LINECARD PARTS LIST
The following list defines the parts and part values required to meet target specification limits for
channel i of the linecard (i = 1, 2)
Item
Type
Value
Tol.
Rating
Comments
U1
Am79R241
U2
Am79X22xx
U3, U4
P1001SC
100 V
TECCOR Battrax protector
U5
TISP61089
80 V
Transient Voltage Suppresser, Power
Innovations
D1, D2
DHi, DLi, DT1i, DT2i
4
ISLIC device
ISLAC device
Diode
1A
100 V
Diode
100 mA
100 V
RFAi, RFBi
Resistor
50 Ω
2%
2W
RSAi, RSBi
Resistor
200 kΩ
2%
1/4 W
RTi
Resistor
80.6 kΩ
1%
1/8 W
RRXi
Resistor
100 kΩ
1%
1/8 W
RREF
Resistor
69.8 kΩ
1%
1/8 W
RMGLi, RMGPi
Resistor
1 kΩ
5%
1W
RSHB, RSLB
Resistor
750 kΩ
1%
1/8 W
RHLai
Resistor
40.2 kΩ
1%
1/10 W
50 ns
Fusible PTC protection resistors
Sense resistors
Current reference
Thermal management resistors
RHLbi
Resistor
4.32 kΩ
1%
1/10 W
RHLci
Resistor
2.87 kΩ
1%
1/10 W
RHLdi
Resistor
2.87 kΩ
1%
1/10 W
CHLbi
Capacitor
3.3 nF
10 %
10 V
Not Polarized
Ceramic
CHLdi
Capacitor
0.82 µF
10 %
10 V
RMTi
Resistor
3.01 kΩ
1%
1/8 W
RLGi
Resistor
6.04 kΩ
1%
1/8 W
RTESTMi
Resistor
2 kΩ
1%
1W
Metallic test
Longitudinal test
RTESTLi
Resistor
2 kΩ
1%
1W
Capacitor
22 nF
10%
100 V
Ceramic, not voltage sensitive
CBATHi, CBATLi
Capacitor
100 nF
20%
100 V
Ceramic
CHPi
Capacitor
22 nF
20%
100 V
Ceramic
Capacitor
100 nF
20%
100 V
Protector speed up capacitor
Capacitor
56 pF
5%
100 V
Ceramic
1.2 W typ
CADi, CBDi
CSi
1
1
CSSi3
Components for External Ringing
RGFDi
Resistor
510 Ω
2%
2W
RSRBi, RSRc
Resistor
750 kΩ
2%
1/4 W
KRi
Relay
5 V Coil
Matched to within 0.2% for initial tolerance
and 0 to 70° C ambient temperature range.2
17 mW typ
DPDT
Notes:
1. Value can be adjusted to suit application.
2. Can be looser for relaxed ring-trip requirements. 1% match (each resistor ±1%) gives 1.275 mA uncertainty in ringing current
sensing.
3. Required for metering > 2.5 Vrms, otherwise may be omitted.
4. DT2i is optional - Should be put if there is a chance that this chip may be replaced by Am79R251.
Am79D2251
13
ELECTRICAL CHARACTERISTICS
Power Dissipation
Description
Dual ISLAC Power
Dissipation
Typ
Max
One channel activated
Test Conditions
Min
TBD
TBD
All channels active
TBD
TBD
All channels inactive
Unit
mW
TBD
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device
failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings
for extended periods can affect device reliability.
Storage Temperature
–60°C ≤ TA ≤ +125°C
Ambient Temperature, under Bias
–40°C ≤ TA ≤ +85°C
Ambient relative humidity (non condensing)
5 to 100%
VCCA with respect to DGND
–0.4 V to + 3.47 V
VCCD with respect to DGND
–0.4 V to + 3.47 V
VIN with respect to DGND
–0.4 V to VCCA + 0.4 V
5 V tolerant pins
–0.4 to Vcc + 2.25 or 5.25 V,
whichever is less
AGND
DGND ±0.4 V
Latch up immunity (any pin)
±100 mA
Any other pin with respect to DGND
–0.4 V to VCC
Operating Ranges
Operating ranges define those limits over which the functionality of the device is guaranteed by 100
percent production testing. Specifications outside of the 0 to 70°C range (–40 to 85°C) are
guaranteed through characterization and sample-lot testing production devices at the temperature
extremes.
Intelligent Access™ Voice Chipsets Environmental Ranges
Ambient Temperature
–40 to +85°C Commercial
Ambient Relative Humidity
15 to 85%
Electrical Maximum Ranges
14
Analog Supply VCCA
+3.3 V ± 5%
Digital Supply VCCD
+3.3 V ± 5%
DGND
0V
AGND
DGND ±50 mV
Am79D2251
PERFORMANCE SPECIFICATIONS
The performance targets defined in this section are for the entire linecard comprised of both chips
in the Intelligent Access voice chipsets unless otherwise noted. Specifications for the individual chips
in the set will be published separately (see note 1). TA = 0 to 70°C unless otherwise noted.
Intelligent Access™ Voice Chipsets System Target Specifications
Item
Condition
Min
Typ
Max
Unit
Peak Ringing Voltage
Active Ringing mode,
RLOAD = 1500 Ω,
VBH = 80 V
70
V
Output Impedance during
internal ringing
Active Ringing mode, Dual
ISLAC generating internal
ringing
200
Ω
Sinusoidal Ringing THD
Active Ringing mode,
RLOAD = 1500 Ω,
VBH = 80 V, ISLAC
generating internal
sinusoidal ringing
2
%
PSRR (VBH, VBL)
Loop open, in anti-sat
f = 50 Hz
f = 200 to 3400 Hz
2
12
dB
Note
1, 2
Notes:
1. Not tested or partially-tested in production.
2. These numbers are only valid when an ISLIC device operates with an ISLAC device, because the ISLAC
generates the anti-sat feed characteristic. When the Intelligent Access voice chipsets operate in the normal
feed region, the performance is controlled by the ISLIC device. See appropriate ISLIC data sheet for
specific PSRR.
Am79D2251
15
DC Specifications
No.
Item
Condition
Typ
Max
1
Input Low Voltage,
All other digital inputs
–0.05
–0.50
1.36 V
0.80 V
2
Input High Voltage,
All other digital inputs
2.36
2.0
Vcc+0.4
5.25
4
Input Leakage Current
All digital inputs except MCLK
MCLK
Input hysteresis (PCLK/FS, FS/DCL,
MCLK, DIO, DRA)
Ternary output voltages, LD1–2
High voltage
Low voltage
Output current
–10
+10
–120
+180
5
6
0.15
Iout = ±200 µA
Iout = 2 mA
Mid level
0.225
0.3
—
0.4
+10
VCC–0.45
—
–10
7
Output Low Voltage (DXA/DU, DIO,
INT, TSCA)
Iol = 2 mA
0.4
8
Output Low Voltage
(INT, TSCA)
Output High Voltage (All digital
outputs except INT in open drain
mode and TSCA)
Input Leakage Current (VIN1–2,
VSAB1–2, VILG1–2, VIMT1–2)
Input Leakage Current ( VSAB1–2)
Iol = 10 mA
1.0
9
10
11
12
13
Input voltage (VIN1–2)
µ-law
A-law
Unit
Note
V
µA
V
2
V
V
µA
V
Ioh = 400 µA
3.205 dBm0
3.14 dBm0 to insertion
loss in ADC
|Vov–VREF| where Vov is
input overload voltage
14
Input Voltage (VSAB 1–2 or VIMT1–2
or VILG1–2)
Offset voltage allowed on VIN1–2
15
16
VHL output offset voltage
VOUT1–2 offset Voltage
17
Output voltage, VREF
18
Capacitance load on VREF or
VOUT1–2
19
Output drive current, VOUT1–2 or
VLB1–2
20
21
Output leakage current
VOUT1–2 or VLB1–2
Maximum output voltage on VOUT
22
VLB1–2 operating voltage
23
Maximum output voltage on VHL
(KRFB)
|VHL–VREF| with peak
digital input
24
25
Gain from VSAB to VHL
Gain from VSAB to VHL
VFD = 1
VFD = 0
26
% error of VLB voltage (For VLB
equation, see Am79R2xx/
Am79D2251 Technical Reference)
27
Capacitance load on VLB1–2
16
Min
DISN off
DISN on
VCC–0.4
VREF
–1.02
0.99
µA
TBD
µA
1.02
VREF
+1.02
1.05
–50
+50
–40
–80
+40
+80
Load current = 0 to 10 mA
Source or Sink
Source or Sink
TBD
1.4
–1
0.99
VREF
–1.02
9
200
pF
2
+1
mA
2
mA
1.05
VREF
+1.02
9
V
0.97
1.00
1.03
V
4.9
–0.0255
5
–0.025
5.1
–0.0245
V/V
V/V
+5
%
120
pF
–5
Am79D2251
1.02
mV
V
TBD
|VOUT–VREF| with peak
digital input
Source current < 250 µA
or sink current < 25 µA.
V
9
5
No.
28
Item
Condition
Min
Typ
Max
Unit
Note
400
pF
5
Capacitance load on XSB1–2, XSC
Transmission and Signaling Specifications
Table 1. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
Signal at Digital Interface
Transmit
Receive
A-law digital mW or equivalent (0 dBm0)
0.5026
0.5026
µ-law digital mW or equivalent (0 dBm0)
0.4987
0.4987
±5,800 peak linear coded sine wave
0.5026
0.5025
No.
1
Item
Condition
Min
Typ
Max
–0.25
0
+0.25
–0.25
0
+0.25
–0.15
0
+0.015
–0.1
0
+0.1
Vrms
Unit
Note
Input: 1014Hz, –10dBm0
RG = AR = AX = GR = GX = 0 dB,
AISN, R, X, B and Z filters disabled
Insertion Loss
A-D
D-A
A-D + D-A
A-D + D-A
Temperature = 70°C
Variation over temperature
2
Level set error (Error between
setting and actual value)
A-D AX + GX
D-A AR + GR
–0.1
0.1
3
DR to DX gain in full digital
loopback mode
DR Input: 1014 Hz, –10 dBm0
RG=AR=AX=GR=GX=0 dB,
DISN, R, X, B and Z filters disabled
–0.3
+0.3
4
Idle Channel Noise,
Psophometric Weighted (A-law)
Off-hook and On-hook
AX = 0dB
AR = 0dB
A-D (PCM output)
D-A (VOUT)
5
Unit
Idle Channel Noise,
C Message weighted (µ-law)
6
dB
dBm0p
11
–69
–78
Off-hook and On-hook
AX = 0dB
AR = 0dB
A-D (PCM output)
D-A (VOUT)
dBrnC0
+19
11
+12
6
Coder Offset decision value, Xn
A-D, Input signal = 0V
7
GX step size
0 ≤ GX < 12 dB
0.1
5
8
GR step size
–12 ≤ GR ≤ 0 dB
0.1
5
9
PSRR (VCC)
Image frequency
Input: 4.8 to 7.8 kHz, 200 mV p-p
Measure 8000 Hz-Input frequency
A-D
D-A
10
DISN gain accuracy
Gdisn = ±0.9375 Vin = 0 dBm0
Gdisn = –0.9375 to 0.9375
11
End-to-end group delay
12
Crosstalk
same channel
TX to RX
RX to TX
–7
+7
Bits
dB
5
5
37
37
+0.25
dB
2
1014 Hz; –10 dBmO
B = Z = 0; X = R = 1
525
µS
13,
12,
5
0 dBm0
0 dBm0
–75
–75
dBm0
300 Hz to 3400 Hz
300 Hz to 3400 Hz
Am79D2251
–0.25
17
No.
13
Item
Condition
Crosstalk between channels
TX or RX to TX
TX or RX to RX
Min
Typ
Max
Unit
–76
–78
dBm0
Note
0 dBm0
1014 Hz
1014 Hz
Notes:
1.
These tests are performed with the following load impedances:
Frequency < 12 kHz – Longitudinal impedance = 500 Ω; metallic impedance = 300 Ω
Frequency > 12 kHz – Longitudinal impedance = 90 Ω; metallic impedance = 135 Ω
18
2.
Not tested or partially tested in production. This parameter is guaranteed by characterization or
correlation to other tests.
3.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by
characterization.
4.
When the Intelligent Access voice chipset is in the anti-sat operating region, this parameter will be
degraded. The exact degradation will depend on system design.
5.
Guaranteed by design.
6.
Overall 1.014 kHz insertion loss error of the Intelligent Access voice chipset is guaranteed to be ≤
0.34 dB
7.
These SBAT, PSRR specifications are valid only when the ISLIC is used with the ISLAC, which
generates the anti-sat reference. Since the anti-sat reference depends upon the battery voltage sensed
by the VHB, VLB, and VPB pins of the ISLAC, the PSRR of the kit depends upon the amount of battery
filtering provided by CB.
8.
Must meet at least one of these specifications.
9.
These voltages are referred to VREF
10.
These limits refer to the 2-wire output of an ideal ISLIC but reflect only the capabilities the ISLAC.
11.
When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from
0 to 12 dB or (AR + GR + RG) from 0 to –12 dB.
12.
Group delay spec valid only when Channels 1–2 occupy consecutive slots in the frame. Programming
channels in non-consecutive timeslots adds 1 frame delay in the Group delay measurements.
13.
The Group delay specification is defined as the sum of the minimum values of the group delays for
transmit and the receive paths when the B, X, R, and Z filters are disabled with null coefficients. See
Figure 15-3 for Group Delay Distortion.
14.
These limits reflect only the capabilities of the dual ISLAC device.
Am79D2251
Transmit and Receive Paths
In this section, the transmit path is defined as the analog input to the ISLAC device (VINn) to the
PCM voice output of the ISLAC A-law/µ law speech compressor (See Figure 7-1 in the Am79R2xx/
Am79D2251x Technical Reference). The receive path is defined as the PCM voice input to the
ISLAC speech expander to the analog output of the ISLAC device (VOUTn). All limits defined in this
section are tested with B = 0, Z = 0 and X = R = RG = 1.
When RG is enabled, a gain of –6.02 dB is added to the digital section of the receive path.
When AR is enabled, a nominal gain of –6.02 dB is added to the analog section of the receive path.
When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path.
When relative levels (dBm0) are used in any of the following transmission characteristics, the
specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to –12 dB.
These transmission characteristics are valid for 0 to 70°C.
Am79D2251
19
Attenuation Distortion
The attenuation of the signal in either path is nominally independent of the frequency. The deviations
from nominal attenuation will stay within the limits shown in Figure 6. The reference frequency is
1014 Hz and the signal level is –10 dBm0.
Figure 6. Transmit and Receive Path Attenuation vs. Frequency
2
Dual ISLAC Specification
Attenuation (dB)
1
0.80
0.65
0.6
0.2
0.125
0
Receive path
-0.125
3400
3200
3000
Frequency (Hz)
600
200
300
0
Minimum transmit attenuation at 60 Hz is 24 dB
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in
Figure 7. The minimum value of the group delay is taken as the reference. The signal level should
be –10 dBm0.
Figure 7. Group Delay Distortion
420
Dual ISLAC Specification
(Either Path)
Delay (µS)
150
20
Am79D2251
2800
Frequency (Hz)
2600
1000
600
0
500
90
Single Frequency Distortion
The output signal level, at any single frequency in the range of 300 to 3400 Hz, other than that due
to an applied 0 dBm0 sine wave signal with frequency f in the same frequency range, is less than
–46 dBm0. With f swept between 0 to 300 Hz and 3.4 to 12 kHz, any generated output signals other
than f are less than –28 dBm0. This specification is valid for either transmission path.
Intermodulation Distortion
Two sine wave signals of different frequencies, f1 and f2 (not harmonically related) in the range 300
to 3400 Hz and of equal levels in the range –4 to –21 dBm0, do not produce 2 • f1 – f2 products
having a level greater than –42 dB, relative to the level of the two input signals.
A sine wave signal in the frequency band 300 to 3400 Hz with input level –9 dBm0 and a 50 Hz
signal with input level –23 dBm0 does not produce intermodulation products exceeding a level of
–56 dBm0. These specifications are valid for either transmission path.
Am79D2251
21
Gain Linearity
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 8 (A-law) and
Figure 9 (µ-law) for either transmission path when the input is a sine wave signal of 1014 Hz.
Figure 8. A-law Gain Linearity with Tone Input (Both Paths)
Dual ISLAC Specification
1.5
0.55
0.25
Gain (dB)
0
-55 -50
-40
-10
0 +3
Input
Level
(dBm0)
-0.25
-0.55
-1.5
Figure 9. µ-law Gain Linearity with Tone Input (Both Paths)
Dual ISLAC Specification
1.4
0.45
0.25
Gain (dB)
0
-55 -50
-37
-10
-0.25
-0.45
-1.4
22
Am79D2251
0
+3
Input
Level
(dBm0)
Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 10 for either path when the
input signal is a sine wave signal of frequency 1014 Hz.
Figure 10. Total Distortion with Tone Input, Both Paths
Dual ISLAC Specification
B
A
A
B
C
D
C
D
A-Law
35.5dB
35.5dB
30dB
25dB
µ-Law
35.5dB
35.5dB
31dB
27dB
Signal-to-Total
Distortion (dB)
-45
-40
-30
0
Input Level (dBm0)
Overload Compression
Figure 11 shows the acceptable region of operation for input signal levels above the reference input
power (0 dBm0). The conditions for this figure are:
(1) 1 dB < GX ≤ +12 dB; (2) –12 dB ≤ GR < –1 dB; (3) Digital voice output connected to digital voice
input; and (4) measurement analog to analog.
Figure 11. A/A Overload Compression
9
8
7
6
Fundamental
Output Power
(dBm0)
5
Acceptable
Region
4
3
2.6
2
1
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Am79D2251
23
Discrimination against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be
frequency components below 4 kHz at the digital output which are caused by the out-of-band signal. These
components are at least the specified dB level below the level of a signal at the same output originating from a
1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are
shown in the following table.
Frequency of Out-of-Band Signal
Amplitude of Out-of-Band Signal
Level below A
16.6 Hz < f < 45 Hz
–25 dBm0 < A ≤ 0 dBm0
18 dB
45 Hz < f < 65 Hz
–25 dBm0 < A ≤ 0 dBm0
25 dB
65 Hz < f < 100 Hz
–25 dBm0 < A ≤ 0 dBm0
10 dB
3400 Hz < f < 4600 Hz
–25 dBm0 < A ≤ 0 dBm0
see Figure 12
4600 Hz < f < 100 kHz
–25 dBm0 < A ≤ 0 dBm0
32 dB
0
ISLAC Device Specification
–10
–20
Level (dB)
–28 dBm
–30
–32 dB, –25 dBm0 < input < 0 dBm0
–40
–50
3.4
4.0
4.6
Frequency (kHz)
Note:
The attenuation of the waveform below amplitude A between
3400 Hz and 4600 Hz is given by the formula:
π ( 4000 – f )
Attenuation (db) = 14 – 14 sin -------------------------1200
Figure 12. Discrimination Against Out-of-Band Signals
24
Am79D2251
19256A-012
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied
to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.
Frequency
Level
4.6 kHz to 40 kHz
–32 dBm0
40 kHz to 240 kHz
–46 dBm0
240 kHz to 1 MHz
–36 dBm0
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to
the digital input, the level of the signals at the analog output are below the limits in Figure 13. The amplitude of the
spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula:
π ( f – 4000 )
A = – 14 – 14 sin ---------------------------- dBm0
1200
0
ISLAC Device Specification
–10
–20
Level (dBm0)
–28 dB
–30
–32 dB
–40
–50
3.4
4.0
4.6
Frequency (kHz)
19256A-013
Figure 13. Spurious Out-of-Band Signals
Am79D2251
25
SWITCHING CHARACTERISTICS
PCM Switching Characteristics
Figure 14. PCM Switching Characteristics
VCC = 3.3 V +5%, AGND = DGND = 0 V
TBD
TBD
TBD
TBD
TEST
POINTS
TBD
TBD
Microprocessor Interface
Min and max values are valid for all digital outputs with a 100 pF load, except DIO,DXA, INTL, and
TSCA which are valid with 150 pF loads.
No.
Symbol
Parameter
Min
Typ
Max
1
tDCY
Data clock period
122
2
tDCH
Data clock HIGH pulse width
48
1
3
tDCL
Data clock LOW pulse width
48
1
4
tDCR
Rise time of clock
15
5
tDCF
Fall time of clock
15
6
tICSS
Chip select setup time, Input
mode
30
7
tICSH
Chip select hold time, Input mode
0
8
tICSL
Chip select pulse width, Input
mode
9
tICSO
Chip select off time, Input mode
10
tIDS
Input data setup time
25
11
tIDH
Input data hold time
30
30
tDCY–10
Unit
Note
ns
tDCH–20
8tDCY
1, 6
5
12
26
13
tOCSS
Chip select setup time, Output
mode
14
tOCSH
Chip select hold time, Output
mode
15
tOCSL
Chip select pulse width, Output
mode
16
tOCSO
Chip select off time, output Mode
17
tODD
Output data turn on delay
18
tODH
Output data hold time
19
tODOF
Output data turn off delay
20
tODC
Output data valid
0
21
tRST
Reset pulse width
50
Am79D2251
tDCY–10
tDCH–20
8tDCY
ns
50
3
50
50
µs
1, 6
PCM Interface
No.
Symbol
22
tPCY
PCM clock period
Parameter
Min.
Typ
23
tPCH
PCM clock HIGH pulse width
48
24
tPCL
PCM clock LOW pulse width
48
25
tPCF
Fall time of clock
15
26
tPCR
Rise time of clock
15
27
tFSS
FS setup time
30
28
tFSH
FS hold time
50
29
tTSD
Delay to TSCA valid
5
30
tTSO
Delay to TSCA off
5
0.122
Max
Unit
Note
7.8125
µs
2
ns
tPCY–30
80
3
4
31
tDXD
PCM data output delay
5
70
32
tDXH
PCM data output hold time
5
70
33
tDXZ
PCM data output delay to high-Z
10
70
34
tDRS
PCM data input setup time
25
35
tDRH
PCM data input hold time
5
36
tFST
PCM or frame sync jitter time
–97
97
Master Clock
For 2.048 MHz ±100 PPM, 4.096 MHz ±100 PPM, or 8.192 MHz ±100 PPM operation:
No.
Symbol
Parameter
Min
Typ
Max
37
tMCY
Period: 2.048 MHz
Period: 4.096 MHz
Period: 8.192 MHz
488.23
244.11
122.05
488.28
244.14
122.07
488.33
244.17
122.09
38
tMCR
Rise time of clock
15
39
tMCF
Fall time of clock
15
40
tMCH
MCLK HIGH pulse width
48
41
tMCL
MCLK LOW pulse width
48
Unit
No
2
ns
Notes:
1.
DCLK may be stopped in the HIGH or LOW state indefinitely without loss of information. When CS
makes a transition to the High state, the last byte received will be interpreted by the Microprocessor
Interface logic.
2.
The PCM clock (PCLK or MCLK) frequency must be an integer multiple of the frame sync (FS)
frequency with an accuracy of 100 PPM. This allowance includes any jitter that may occur between
the PCM signals (FS, PCLK) and MCLK. The actual PCLK rate is dependent on the number of channels
allocated within a frame. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be
used for standard U.S. transmission systems.
3.
TSCA is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock
slot register.
4.
tTSO is defined as the time at which the output driver turns off. The actual delay time is dependent on
the load circuitry. The maximum load capacitance on TSCA is 150 pF and the minimum pull-up
resistance is 360 Ω.
5.
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs
last.
6.
The ISLAC device requires 2.0 µs between SIO operations. If the MPI is being accessed while the
MCLK (or PCLK if combined with MCLK) input is not active, a Chip Select Off time of 20 µs is required
when accessing coefficient RAM.
Am79D2251
27
PCM Switching Waveforms
Figure 15. Master Clock Timing
37
41
V
V
IH
IL
40
38
39
Figure 16. Microprocessor Interface (Input Mode)
1
2
5
VIH
VIH
DCLK
VIL
VIL
3
7
9
4
CS
6
8
10
DIO
28
Data
Valid
11
Data
Valid
Data
Valid
Am79D2251
Figure 17. Microprocessor Interface (Output Mode)
VIH
DCLK
VIL
14
13
16
15
CS
20
18
17
DIO
19
VOH Data
VOL Valid
Three-State
Data
Valid
Data
Valid
Three-State
Figure 18. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge))
Time Slot Zero, Clock Slot Zero
27
22
26
25
VIH
PCLK
VIL
23
24
28
FS
30
29
TSCA
See Note 4
31
32
33
VOH
DXA
First
Bit
VOL
35
34
VIH
DRA
First
Bit
Second
Bit
VIL
Am79D2251
29
Figure 19. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero, Clock Slot Zero
27
22
26
25
VIH
PCLK
VIL
23
24
FS
28
30
29
TSCA
See Note 4
31
32
33
VOH
DXA
First
Bit
VOL
35
34
VIH
First
Bit
DRA
Second
Bit
VIL
GCI Timing Specifications
Symbol
Signal
Parameter
tR, tF
DCL
Rise/fall time
tDCL
DCL
Period, FDCL = 2048 kHz
Min
Typ
Max
Unit
60
FDCL = 4096 kHz
478
239
90
tWH, tWL
DCL
Pulse width
tR, tF
FS
Rise/fall time
tSF
FS
Setup time
70
tHF
FS
Hold time
50
130
498
249
60
tDCL–50
tWFH
FS
High pulse width
tDDC
DU
Delay from DCL edge
100
tDDF
DU
Delay from FS edge
150
tSD
DD
Data setup
twH+20
tHD
DD
Data hold
50
ns
Notes:
1. The Data Clock (DCL) can be stopped in the high or low state without loss of information.
2. A temporary stoppage of DCL must not put the ISLAC into a state in which it does not respond to a software
reset command.
3. All frequency-dependent specifications are guaranteed for clock frequencies within ±100 PPM from
nominal.
30
Am79D2251
GCI Waveforms
DCL
FS
BIT
7
BIT
6
DD,
DU
DETAIL A
tr
tf
DCL**
tWH
tDCL
tWL
FS
tSF
tHF
tWFH
tDDF
DU
tDDC
tSD
tHD
DD
** Timing diagram valid for
FDCL = 2048 or 4096 KHz
Am79D2251
31
PHYSICAL DIMENSIONS
44-Pin PLCC
.685
.695
.042
.056
.650
.656
.062
.083
Pin 1 I.D.
.685
.695
.650
.656
.500 .590
REF .630
.013
.021
.026
.032
.009
.015
.050 REF
TOP VIEW
.090
.120
.165
.180
SEATING PLANE
SIDE VIEW
44-Pin TQFP
44
1
11.80
12.20
9.80
10.20
9.80
10.20
11.80
12.20
11° – 13°
0.95
1.05
1.20 MAX
1.00 REF.
32
0.30
0.45
0.80 BSC
Am79D2251
11° – 13°
16-038-PQT-2
PQT 44
7-11-95 ae
16-038-SQ
PL 044
DA78
6-28-94 ae
REVISION SUMMARY
Revision A to Revision B
•
Revision A was a condensed version of the datasheet while Revision B contains the full version.
Revision B to Revision C
• Page 13, Linecard Parts List, Rows CHLbi and CHLdi: switched the numbers in the “Values” column.
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
© 1999 Advanced Micro Devices, Inc.
All rights reserved.
Trademarks
AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Intelligent Access and WinSLAC are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79D2251
33
Am79D2251
34