N CLC431/432 Dual Wideband Monolithic Op Amp with Disable General Description Features The CLC431 and CLC432 current-feedback amplifiers provide wide bandwidths and high slew rates for applications where board density and power are key considerations. These amplifiers provide DCcoupled small signal bandwidths exceeding 92MHz while consuming only 7mA per channel. Operating from ±15V supplies, the CLC431/ 432’s enhanced slew rate circuitry delivers large-signal bandwidths with output voltage swings up to 28Vpp. A wide range of bandwidthinsensitive gains are made possible by virtue of the CLC431 and CLC432’s current-feedback topology. ■ The large common-mode input range and fast settling time (70ns to 0.05%) make these amplifiers well suited for CCD & data telecommunication applications. The disable of the CLC431 can accommodate ECL or TTL logic levels or a wide range of user definable inputs. With its fast enable/disable time (0.2µs/1µs) and high channel isolation of 70dB at 10MHz, the CLC431 can easily be configured as a 2:1 MUX. Many high performance video applications requiring signal gain and/or switching will be satisfied with the CLC431/432 due to their very low differential gain and phase errors (less than 0.1% and 0.1°; Av = +2V/V at 4.43MHz into 150Ω load). ■ ■ ■ ■ ■ Wide bandwidth: 92MHz (AV=+1) 62MHz (Av=+2) Fast slew rate: 2000V/µs Fast disable: 1µs to high-Z output High channel isolation: 70dB at 10MHz Single or dual supplies: ±5V to ±16.5V Applications ■ ■ ■ ■ Video signal multiplexing Twisted-pair differential driver CCD buffer & level shifting Discrete gain-select amplifier Transimpedance amplifier CLC431/432 Dual Wideband Monolithic Op Amp with Disable June 1999 Quick 8ns rise and fall times on 10V pulses allow the CLC431/432 to drive either twisted pair or coaxial transmission lines over long distances. The CLC431/432's combination of low input voltage noise, wide common-mode input voltage range and large output voltage swings make them especially well suited for wide dynamic range signal processing applications. Typical Application Discrete Gain Select Amplifier Pinout PDIP & SOIC Rg 500Ω Rf Channel 1 (Gain = 2) CLC431 500Ω Vinv1 1 Ri 50Ω ½CLC431 Vnon-inv1 2 50Ω Rs SELECT 1Vpp @ 5MHz ½CLC431 50Ω 50Ω RL Rg 125Ω DIS1 3 12 DIS1 -Vcc 4 11 +Vcc Vout1 1 DIS2 5 10 DIS2 Vinv1 2 50Ω 500Ω Rf Channel 2 (Gain = 5) Vnon-inv2 6 Vinv2 7 1999 National Semiconductor Corporation Printed in the U.S.A. 13 VRTTL1 Vout 50Ω Ri 14 Vout1 9 VRTTL2 8 Vout2 CLC432 Vnon-inv1 -Vcc 3 4 + + 8 +Vcc 7 Vout2 6 Vinv2 5 Vnon-inv2 http://www.national.com CLC431/432 Electrical Characteristics (V CC PARAMETERS Ambient Temperature CONDITIONS CLC431 & CLC432 FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 4.0Vpp Vout < 4.0Vpp VCC = ±5V Vout < 10Vpp gain flatness Vout < 4.0Vpp peaking DC to 100MHz rolloff DC to 20MHz linear phase deviation DC to 30MHz differential gain 4.43MHz, RL=150Ω differential phase 4.43MHz, RL=150Ω TIME DOMAIN RESPONSE rise and fall time 10V step overshoot 2V step settling time 2V step to 0.05% slew rate Vout = ±10V DISTORTION AND NOISE RESPONSE 2Vpp, 1MHz 2nd harmonic distortion 2Vpp, 1MHz 3rd harmonic distortion equivalent input noise voltage >1MHz current, inverting >1MHz current, non-inverting >1MHz STATIC DC PERFORMANCE input offset voltage average drift bias current, non-inverting average drift bias current, inverting average drift power supply rejection ratio DC common-mode rejection ratio DC supply current RL= ∞, per channel CLC431 disabled RL= ∞, per channel MISCELLANEOUS PERFORMANCE input voltage range common mode resistance non-inverting capacitance non-inverting output current voltage range RL≥5kΩ RL=100Ω SWITCHING PERFORMANCE (CLC431) switching time turn on turn off DIS logic levels single-ended mode high input voltage (VIH) low input voltage (VIL) maximum current input VIH > DIS > VIL differential mode |DIS-DIS | minimum differential voltage ISOLATION crosstalk, input referred off isolation 10MHz 10MHz TYP +25 Ω; RL = 100Ω Ω; unless noted) = ±15V; AV= +2; Rf = Rg =750Ω +25 MIN/MAX RATINGS 0 to +70 -40 to +85 UNITS °C NOTES 1 62 62 28 42 37 36 21 20 20 MHz MHz MHz 0.05 0.0 0.3 0.12 0.12 0.5 0.8 1.8 0.18 0.18 0.7 0.8 2.0 0.2 0.23 0.7 0.8 2.1 0.2 0.25 dB dB ° % ° 8 5 70 2000 12 10 100 1500 13 12 110 1450 13 12 110 1400 ns % ns V/ms 2 dBc dBc 6 6 - 65 - 75 3.3 13 2.0 4.2 16 2.5 4.4 17 2.6 4.5 18 2.8 nV/√Hz pA/√Hz pA/√Hz 3 20 2 25 2 8 64 63 7.1 0.8 6 --8 --6 --59 58 7.9 1.2 7 50 10 100 6 25 59 57 8.5 1.3 7 50 16 150 8 40 59 56 9.6 1.45 mV µV/°C µA nA/°C µA nA/°C dB dB mA mA ± 12.2 24 0.5 ± 60 ± 14.0 ± 6.0 ± 12.0 16 1 ± 38 ± 13.6 ± 3.7 ± 11.8 10 1 ± 35 ± 13.4 ± 3.7 ± 11.6 6 1 ± 30 ± 13.2 ± 2.9 0.1 0.7 0.15 1.0 0.155 1.2 0.165 1.2 2 2 A A A A A V MΩ pF mA V V µs µs 3 > 2.0 < 0.8 150 > 2.0 < 0.8 180 > 2.0 < 0.8 190 > 2.0 < 0.8 205 V V µA 0.3 0.4 0.4 0.4 V 70 64 64 60 64 60 64 60 dB dB 4 5 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage short circuit current common-mode input voltage differential input voltage maximum junction temperature storage temperature lead temperature (soldering 10 sec) http://www.national.com ±16.5V 100mA ±Vcc ±10V +150°C -65°C to+150°C +300°C Notes 1) Tested and guaranteed with Rf = 866Ω. CLC432 tested and guaranteed with Rf = 750Ω. 2) Spec is guaranteed for RL ≥ 500Ω. 3) VRTTL= 0, See text for single-ended mode of operation. 4) VRTTL= NC, See text for differential mode of operation 5) Spec is guaranteed for AJE; AJP & AIB yield 7dB lower. 6) Spec is tested with 2Vpp, 10MHz and RL= 100Ω. A) J-level: spec is 100% tested at +25°C. 2 3 http://www.national.com Application Discussion Typical Performance plots are valid for both devices under the specified conditions. Generally, lowering Rf from its recommended value will peak the frequency response and extend the bandwidth while increasing its value will roll off the response. Reducing the value of Rf too far below its recommended value will cause overshoot, ringing and eventually oscillation. For more information see Application Note OA-20 and OA-13. Introduction The CLC431 and the CLC432 are dual wideband currentfeedback op amps that operate from single (+10V to +33V) or dual (±5V to ±16.5) power supplies. The CLC431 is equipped with a disable feature and is offered in 14-pin DIP and SOIC packages. The CLC432 is packaged in a standard 8-pin dual pinout and is offered in an 8-pin DIP and SOIC. Evaluation boards are available for each version of both devices. The evaluation boards can assist in the device and/or application evaluation and were used to generate the typical device performance plots on the preceding pages. In order to optimize the devices' frequency and phase response for gains other than +2V/V it is recommended to adjust the value of the feedback resistor. The two plots found in the Typical Performance section entitled "Recommended Rf vs. Gain" provide the means of selecting the feedback-resistor value that optimizes frequency and phase response over the CLC431/ CLC432's gain range. Both plots show the value of Rf approaching a nonzero minimum at high non-inverting gains, which is characteristic of current-feedback op amps and yields best results. The linear portion of the two Rf vs. Inverting-gain curves results from the limitation placed on Rg (i.e. Rg ≥ 50Ω) in order to maintain an adequate input impedance for the inverting configuration. It should be noted that for stable operation a noninverting gain of +1 requires an Rf equal to 1kΩ for both the CLC431 and the CLC432. Each of the CLC431/CLC432's dual channels provide closely matched DC & AC electrical performance characteristics making them ideal choices for wideband signal processing. The CLC431, with its disable feature, can easily be configured as a 2:1 mux or several can be used to form a 10:1 mux without performance degradation. The two closely-matched channels of the CLC432 can be combined to form composite circuits for such applications as filter blocks, integrators, transimpedance amplifiers and differential line drivers and receivers. Feedback Resistor Selection The loop gain and frequency response for a currentfeedback operational amplifier is determined largely by the feedback resistor (Rf). Package parasitics also influence ac response. Since the package parasitics of the CLC431 and the CLC432 are different, the optimum frequency and phase responses are obtained with different values of feedback resistor (for AV=+2; CLC431: Rf=866Ω, CLC432: Rf=750Ω). The Electrical Characteristics and http://www.national.com CLC431 Disable Feature The CLC431 disable feature can be operated either single-endedly or differentially thereby accommodating a wide range of logic families. There are three pins associated with the disable feature of each of the CLC431's two amplifiers: DIS, DIS and VRTTL (please see pinout on 4 front page). Also note that both amplifiers are guaranteed to be enabled if all three of these pins are unconnected. Fig. 2 illustrates the differential mode of the CLC431's disable feature for ECL-type logic. In order for this mode to operate properly, VRTTL must be left floating while DIS and DIS are to be connected directly to the ECL gate as illustrated. Applying a differential logic "high" (DIS - DIS ≥ 0.4Volts) switches the tail current of the differential pair from Q2 to Q1 and results in the disabling of that CLC431 channel. Alternatively, applying a differential logic "low" (DIS - DIS ≤ -0.4Volts) switches the tail current of the differential pair from Q1 to Q2 and results in the enabling of that same channel. The internal clamp, mentioned above, also protects against excessive differential voltages up to 30Volts while limiting input currents to <3mA. Fig. 1 illustrates the single-ended mode of the CLC431's disable feature for logic families such as TTL and CMOS. In order to operate properly, VRTTL must be grounded, thereby biasing DIS to approximately +1.4V through the two internal series diodes. For single-ended operation, DIS should be left floating. Applying a TTL or CMOS logic "high" (i.e. >2.0Volts) to DIS will switch the tail current of the differential pair to Q1 and "shut down" Q2 which results in the disabling of that channel of the CLC431. Alternatively, applying a logic "low" (i.e. <0.8Volts) to DIS will switch the tail current from Q1 to Q2 effectively enabling that channel. If DIS is left floating under singleended operation, then the associated amplifier is guaranteed to be disabled. Vnon-inv + Vinv +VCC Vout +VCC Voffset = ± Ibn ∗R s +VCC 100kΩ DIS Q1 Q2 VRTTL ½CLC431 The disable feature of the CLC431 is such that DIS and DIS have common-mode input voltage ranges of (+VCC) to (-VCC+3V) and are so guaranteed over the commercial temperature range. Internal clamps (not shown) protect the DIS input from excessive input voltages that could otherwise cause damage to the device. This condition occurs when enough source current flows into the node so as to allow DIS to rise to VCC. This clamp is activated once DIS exceeds DIS by 1.5Volts and guarantees that VDIS (ground referenced) does not exceed 4.7Volts. + Vinv +VCC Applications Circuits 2:1 Video Mux (CLC431) Fig. 3 illustrates the connections necessary to configure the CLC431 as a 2:1 multiplexer in a 75Ω system. Each of the two CLC431's amplifiers is configured with a noninverting gain of +2V/V using 634Ω feedback (Rf) and gain-setting (Rg) resistors. The feedback resistor value is lower than that recommended in order to compensate for the reduction of loop-gain that results from the inclusion of the 50Ω resistor (Ri) in the feedback loop. This 50Ω resistor serves to isolate the output of the active channel from the impedance of the inactive channel yet does not affect the low output impedance of the active channel. Notice that for proper operation VRTTL 1 (pin 13) is grounded and VRTTL 2 (pin 9) is unconnected. The pins associated with the disable feature are to be connected as follows: DIS1 and DIS2 (pins 3 & 10) are connected together as well as DIS2 and DIS1 (pins 5 & 12). Channel 1 is selected with the application of a logic "low" to SELECT while a logic "high" selects Channel 2. Vout +VCC +VCC 100kΩ 100kΩ DIS DIS Q1 Q2 ECL 510Ω -5V ½CLC431 R 1 + f + Ibi ∗R f R g Layout Considerations It is recommended that the decoupling capacitors (0.1µF ceramic and 6.8µF electrolytic) should be placed as close as possible to the power supply pins to insure a proper high-frequency low impedance bypass. Careful attention to circuit board layout is also necessary for best performance. Of particular importance is the control of parasitic capacitances (to ground) at the output and invering input pins. See CLC431/432 Evaluation Board literature for more information. Fig. 1 Vnon-inv R 1 + f + Vio R g The input resistor Rs is that resistance seen when looking from the non-inverting input back towards the source. For inverting DC-offset calculations, the source resistance seen by the input resistor Rg must be included in the output offset calculation as a part of the non-inverting gain equation. Application note OA-7 gives several circuits for DC offset correction. 100kΩ DIS TTL CMOS DC Performance A current-feedback amplifier’s input stage does not have equal nor correlated bias currents, therefore they cannot be cancelled and each contributes to the total DC offset voltage at the output by the following equation: VRTTL 510Ω -5V Fig. 2 5 http://www.national.com Rg Twisted-Pair Driver. Twisted-pair cables are used in many applications such as telephony, video and data communications. The CLC432's two matched channels make it well suited for such applications and is illustrated in Fig. 5. 634Ω Rf 634Ω 75Ω ½CLC431 Channel 1 3 12 Ri 13 ½R 50Ω Rs SELECT NC 10 Channel 2 5 ½CLC431 75Ω Vout 75Ω Ri ½Ro 9 ½CLC432 RL 75Ω 50Ω 634Ω Ro Optional Vin Rf Rg R 1kΩ 634Ω ½CLC432 ½Ro -15V Fig. 3 R R The optional 1kΩ pull-down resistor connected from the output of the 2:1 mux to the negative power supply (-VCC) results in improved differential gain and phase performance (0.02% and 0.01°) at PAL video levels. Fig. 5 CCD Amplifier. The CLC432 can easily be configured as 10MSPS CCD amplifier with DC level shifting as illustrated in Fig 6. Notice that one of the CLC432's channels buffers the CCD output while the other channel is configured with both an inverting DC gain and an AC gain in order to achieve the overall transfer function shown in Fig. 6. Switched Gain Amplifier (CLC431) As seen from the front page, the CLC431 can also be configured as a switched-gain amplifier that is similar to the 2:1 mux. Configuring each of the two CLC431's amplifiers with different non-inverting gains and tying the two inputs together (eliminating one of the input-terminating resistors) allows the CLC431 to switch an input signal between two different gains. Vin Vin R Inactive Channel Impedances (CLC431) The impedance that is seen when looking into the output of a disabled CLC431 is typically represented as 1MΩ||16pF. The inverting input impedance becomes very high, essentially open. Therefore, the impedance presented by a disabled channel is (R f +R g )|| (Ri+(1MΩ||16pF)) as illustrated in Fig. 4. It should also be noted that any trace capacitance that is associated with the common output connection will add in parallel to that presented by the CLC431's inactive channel. ½CLC432 Vout ½CLC432 1kΩ Vref Rx Vout Vin R s = 1+ f Rg s + 1 R gC g Rf Rg 0.1µF Vref Rx = − Vout R x >> for R x >> R g DC Rf 1 2πfin C g Fig. 6 Rg Ordering Information Rf Impedance Presented by Disabled CLC431 Ri 1MΩ 16pF Vin Active Channel Model Impedance Presented by Inactive Channel Ri Rs Vout RL Rf Rg Fig. 4 http://www.national.com Temperature Range Description CLC431AJP -40°C to +85°C CLC431AJE -40°C to +85°C CLC431ALC -40°C to +85°C CLC431A8B -55°C to +125°C CLC431AMC -55°C to +125°C CLC432AJP -40°C to +85°C CLC432AJE -40°C to +85°C CLC432ALC -40°C to +85°C CLC432A8B -55°C to +125°C CLC432AMC -55°C to +125°C DESC SMD numbers: 5962-94725. 6 14-pin PDIP 14-pin SOIC dice 14-pin CerDIP, MIL-STD-883 dice, MIL-STD-883 8-pin PDIP 8-pin SOIC dice 8-pin CerDIP, MIL-STD-883 dice, MIL-STD-883 Reliability Information Transistor count Package Thermal Resistance 37 CLC431 Package θ JC θJA AJP AJE CERDIP 55°C 35°C 25°C 100°C 105°C 80°C 55°C 40°C 25°C 110°C 115°C 115°C CLC432 Package AJP AJE CERDIP 7 http://www.national.com CLC431/432 Dual Wideband Monolithic Op Amp with Disable Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 8