N CLC430 General Purpose 100MHz Op Amp with Disable General Description Features The CLC430 is a low-cost, wideband monolithic amplifier for general purpose applications. The CLC430 utilizes National’s patented current feedback circuit topology to provide an op amp with a slew rate of 2000V/µs, 100MHz unity-gain bandwidth and fast output disable function. Like all current feedback op amps, the CLC430 allows the frequency response to be optimized (or adjusted) by the selection of the feedback resistor. For demanding video applications, the 0.1dB bandwidth to 20MHz and differential gain/phase of 0.03%/0.05° make the CLC430 the preferred component for broadcast quality NTSC and PAL video systems. ■ ■ ■ ■ ■ ■ ■ ■ Applications ■ The large voltage swing (28Vpp), continuous output current (85mA) and slew rate (2000V/µs) provide high-fidelity signal conditioning for applications such as CCDs, transmission lines and low impedance circuits. Even driving loads of 100Ω, the CLC430 provides very low 2nd and 3rd harmonic distortion at 1MHz (-76/-82dBc). 0.1dB gain flatness to 20MHz (Av=+2) 100MHz bandwidth (Av=+1) 2000V/µs slew rate 0.03%/0.05° differential gain/phase ±5V, ±15V or single supplies 100ns disable to high-impedance output Wide gain range Low cost ■ ■ ■ ■ Video distribution CCD clock driver Multimedia systems DAC output buffers Imaging systems Video distribution, multimedia and general purpose applications will benefit from the CLC430’s wide bandwidth and disable feature. Power is reduced and the output becomes a high impedance when disabled. The wide gain range of the CLC430 makes this general purpose op amp an improved solution for circuits such as active filters, differential-to-single-ended drivers, DAC transimpedance amplifiers and MOSFET drivers. CLC430 General Purpose 100MHz Op Amp with Disable June 1999 Typical Application CCD Clock Driver Pinout DIP & SOIC 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC430 Electrical Characteristics (V CC PARAMETERS Ambient Temperature CONDITIONS CLC430 FREQUENCY DOMAIN RESPONSE unity-gain bandwidth Vout < 1.0Vpp small-signal bandwidth Vout < 1.0Vpp Vout < 1.0Vpp 0.1dB bandwidth Vout < 1.0Vpp Vout < 1.0Vpp large-signal bandwidth Vout = 10Vpp gain flatness Vout < 1.0Vpp peaking DC to 10MHz rolloff DC to 20MHz linear phase deviation DC to 20MHz differential gain 4.43MHz, RL=150Ω 4.43MHz, RL=150Ω differential phase 4.43MHz, RL=150Ω 4.43MHz, RL=150Ω TIME DOMAIN RESPONSE rise and fall time 2V step 10V step settling time to 0.05% 2V step overshoot 2V step slew rate 20V step DISTORTION AND NOISE RESPONSE 1Vpp,1MHz, RL=500 2nd harmonic distortion 1Vpp,1MHz, RL=500 3rd harmonic distortion input voltage noise >1MHz non-inverting input current noise >1MHz inverting input current noise >1MHz DC PERFORMANCE input offset voltage average drift input bias current input bias current average drift power-supply rejection ratio common-mode rejection ratio supply current disabled ±15 ±15 ±5 ±15 ±5 ±15 ±5 ±15 ±5 non-inverting average drift inverting DC DC RL= ∞ RL= ∞ VIL MISCELLANEOUS PERFORMANCE Non-inverting input resistance Non-inverting input capacitance input voltage range common mode common mode output voltage range RL= ∞ RL= ∞ output current TYP 25°C 100 75 55 20 16 30 25°C MIN/MAX RATINGS 0 to 70°C -40 to 85°C UNITS 45 42 22 20 19 0.0 0.1 0.5 0.03 0.03 0.05 0.09 0.1 0.7 1.8 0.05 0.05 0.09 0.19 0.2 1.0 2.0 0.06 0.2 1.2 2.1 0.06 0.12 0.13 5 10 35 5 2000 7 14 50 15 1500 7 14 55 15 1450 7 14 55 15 1450 ns ns ns % V/µs dB dB ° % % ° ° 3.5 6.0 18 3.7 6.3 20 3.8 6.8 21 dBc dBc nV/√Hz pA/√Hz pA/√Hz ±15,±5 ±15,±5 1.0 25 3 10 3 10 62 62 11, 8.5 1.5 7.5 --14 --14 --56 54 12 2.0 9.0 50 16 100 15 60 54 53 13 2.2 10.0 50 20 100 17 90 53 52 14.5 2.4 mV µV/ C µA nA/°C µA nA/°C dB dB mA mA 300 200 56 12.5 2.5 10.5 0.6 320 200 56 12.7 2.7 10.0 0.1 340 200 56 ±15 ±5 ±15 ±5 200 100 59 11.8 1.8 10.8 0.8 ns ns dB V V V V 8.0 0.5 ±12.5 ±2.5 ±14 ±4.0 ±85 3.0 1.0 ±12.3 ±2.3 ±13.7 ±3.9 ±60 2.5 1.0 ±12.1 ±2.2 ±13.7 ±3.8 ±50 1.7 1.0 ±11.8 ±1.9 ±13.6 ±3.7 ±45 MΩ pF V V V V mA ±15,±5 ±15,±5 ±15 ±5 ±15 ±5 NOTES MHz MHz MHz MHz MHz MHz 50 35 7 -89 -92 3.0 3.2 15 ±15 SWITCHING PERFORMANCE turn on time turn off time (Note 2) off isolation 10MHz high input voltage VIH low input voltage V cc Ω ; RL = 100Ω = ±15V; AV = +2V/V; Rf =604Ω Ω ; unless noted) A A A A A Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes Absolute Maximum Ratings supply voltage short circuit current common-mode input voltage maximum junction temperature storage temperature lead temperature (soldering 10 sec) ESD rating (human body model) http://www.national.com ±16.5V (note 1) ±Vcc +150°C -65°C to+150°C +300°C 4000V A)J-level: spec is 100% tested at +25°C. 1) Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 125mA. 2) To>50dB attenuation @ 10MHz. 2 3 http://www.national.com Ordering Information Model Temperature Range CLC430AJP CLC430AJE CLC430A8B -40°C to +85°C -40°C to +85°C -55°C to +125°C Package Thermal Resistance Description 8-pin PDIP 8-pin SOIC 8-pin CERDIP, MIL-STD-883 DESC SMD number: 5962-92030. Package θ JC θ JA AJP AJE A8B 60°C/W 55°C/W 30°C/W 115°C/W 135°C/W 120°C/W Reliability Information Transistor count http://www.national.com 4 38 follows: General Design Considerations The CLC430 is a general purpose current-feedback amplifier for use in a variety of small- and large-signal applications. Use the feedback resistor to fine tune the gain flatness and -3dB bandwidth for any gain setting. Comlinear provides information for the performance at a gain of +2 for small and large signal bandwidths. The plots show feedback resistor values for selected gains. Vcc ±15V ±5V Enable >12.7V >2.7V Disable <10.0V <0.8V The amplifier is enabled with pin 8 left open due to the 2kΩ pull-up resistor, shown in Fig. 1. Gain Use the following equations to set the CLC430's noninverting or inverting gain: Non -Inverting Gain = 1+ +Vcc 2kΩ Rf Rg To CLC430 Bias network Rf Rg Choose the resistor values for non-inverting or inverting gain by the following steps. Inverting Gain = - Vin 8kΩ + Fig. 1 Pin 8 Equivalent Disable Circuit Vout Rin CLC430 Open-collector or CMOS interfaces are recommended to drive pin 8. The turn-on and off time depends on the speed of the digital interface. Rs - Rg -Vcc Pin 8 DISABLE Rf The equivalent output impedance when disabled is shown in Fig. 2. With Rg connected to ground, the sum of Rf and Rg dominates and reduces the disabled output impedance. To raise the output impedance in the disabled state, connect the CLC430 as a unity-gain voltage follower by removing Rg. Current-feedback op-amps need the recommended Rf in a unity-gain follower circuit. For high density circuit layouts consider using the dual CLC431 (with disable) or the dual CLC432 (without disable). Fig. 0 Component Identification 1) Select the recommended feedback resistor Rf (refer to plot in the plot section entitled Rf vs Gain). 2) Choose the value of Rg to set gain. 3) Select Rs to set the circuit output impedance. 4) Select Rin for input impedance and input bias. High Gains Equivalent Impedance in Disable Vin + 300kΩ Current feedback closed-loop bandwidth is independent of gain-bandwidth-product for small gain changes. For larger gain changes the optimum feedback register Rf is derived by the following: Vout 8pF - R f = 724Ω − 60Ω ⋅ ( A v ) Rg As gain is increased, the feedback resistor allows bandwidth to be held constant over a wide gain range. For a more complete explanation refer to application note OA-25 Stability Analysis of Current-Feedback Amplifiers. Rf Fig. 2 Equivalent Disabled Output Impedance 2nd and 3rd Harmonic Distortion Resistors have varying parasitics that affect circuit performance in high-speed design. For best results, use leaded metal-film resistors or surface mount resistors. A SPICE model for the CLC430 is available to simulate overall circuit performance. To meet low distortion requirements, recognize the effect of the feedback resistor. Increasing the feedback resistor will decrease the loop gain and increase distortion. Decreasing the load impedance increases 3rd harmonic distortion more than 2nd. Enable / Disable Function The CLC430 amplifier features an enable/disable function that changes the output and inverting input from low to high impedance. The pin 8 enable/disable logic levels are as Differential Gain and Differential Phase The CLC430 has low DG and DP errors for video applications. Add an external pulldown resistor to the CLC430’s output to improve DG and DP as seen in Fig.3. A 604Ω RP will improve DG and DP to 0.01% and 0.02°. 5 http://www.national.com outputs as shown in Fig. 5. To match the mux output impedance to a transmission line, add a resistor (Rs) in series with the output. Add Rp to improve DG and DP Vin + Vout Rin CLC430 Rs - Rf Rg Rp Ro Rf Rg CLC430 Vin1 -Vcc Rin Rs DIS1 DIS2 Vin2 Fig. 3 Improved DG and DP Video Amplifier Ro RL CLC430 Rin Printed Circuit Layout To get the best amplifier performance careful placement of the amplifier, components and printed circuit traces must be observed. Place the 0.1µF ceramic decoupling capacitors less than 0.1" (3mm) from the power supply pins. Place the 6.8µF tantalum capacitors less than 0.75" (20mm) from the power supply pins. Shorten traces between the inverting pin and components to less than 0.25" (6mm). Clear ground plane 0.1" (3mm) away from pads and traces that connect to the inverting, noninverting and output pins. Do not place ground or power plane beneath the op-amp package. Comlinear provides literature and evaluation boards 730013 DIP or 730027 SOIC illustrating the recommended op-amp layout. Vout Rf Rg Fig. 5 Output Connection Automatic Gain Control Current-feedback amplifiers can implement very fast automatic-gain control circuits. The circuit shown in Fig. 6 shows an AGC circuit using the CLC430, a half-wave rectifier, an integrator and a FET. The CLC430 currentfeedback amplifier maintains constant bandwidth and linear phase over AGC's gain range. This circuit effectively controls the output level for continuous signals. Applications Circuits Fig. 6 AGC Circuit Level Shifting The circuit shown in Fig. 4 implements level shifting by AC coupling the input signal and summing a DC voltage. The resistor Rin and the capacitor C set the high-pass break frequency. The amplifier closed-loop bandwidth is fixed by the selection of Rf. The DC and AC gains for circuit of Fig. 4 are different. The AC gain is set by the ratio of Rf and Rg. And the DC gain is set by the parallel combination of Rg and R2. R Rf − Vin f Vout = Vin 1 + ac DC R ||R R2 g 2 + Vin AC C Rin CLC430 The bandwidth of the CLC430 AGC is limited by Rf , the feedback resistor. The FET gate voltage is limited to a range of: Vout Vin DC −2.5 < Vg < −1 Rf R2 Rg R of 750Ω and C1 of 1.0µF gives a useful Rds range of approximately 150 to 2K ohms. Scaling the integrator gain or adding attenuation before the diode D accommodates large signal swings. Determine the overall gain by: Fig. 4 Level Shifting Circuit Multiplexing Multiple signal switching is easily handled with the disable function of the CLC430. Board trace capacitance at the output pin will affect the frequency response and switching transients. To lessen the effects of output capacitance place a resistor (Ro) within the feedback loop to isolate the http://www.national.com 1+ Rf R g + R ds The integrator sets the loop time constant. 6 This page intentionally left blank. 7 http://www.national.com CLC430 General Purpose 100MHz Op Amp with Disable Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. 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