SC660E SMBus System Clock Buffer for Mobile Applications Product Features Product Description § 10 output buffers for high clock fanout applications § Each output can be internally disabled for EMI and The device is a high fanout system clock distributor. Its primary application is to create the large quantity of clocks needed to support a wide range of clock loads that are referenced to a single existing clock. Loads of up to 30 pF are supported. Primary application of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduced by running a single reference clock trace to this device and then using it to regenerate the clock that drives shorter traces by using the SC660 to generate the clocks at the target devices EMI is therefore minimized and board real estate is saved. power consumption reduction. § Separate power supply for each group of 2 clock outputs for mixed voltage application. § < 250ps skew between output clocks. § 28-pin SSOP package for minimum board space § Single output Tristate pin for testability Pin Configuration Block Diagram VDDB SDRAM(0:1) SDRAM(2:3) SDRAM4 FIN SDRAM5 VDD SDATA SCLOCK OE I2C Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com SDRAM(6:7) VDDB SDRAM0 SDRAM1 VSS VDDB SDRAM2 SDRAM3 VSS FIN VDDB SDRAM4 VSS VDD SDATA 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDDB SDRAM9 SDRAM8 VSS VDDB SDRAM7 SDRAM6 VSS OE VDDB SDRAM5 VSS VSS SCLOCK SDRAM(8:9) Document#: 38-07025 Rev. *A 12/17/2002 Page 1 of 8 SC660E SMBus System Clock Buffer for Mobile Applications Pin Description PIN No. 9 Pin Name FIN PWR I/O TYPE Description - I PAD 2,3,6,7,1 1,18,22,2 3,26,27 20 SDRAM(0:9) VDDB O BUF1 This pin is connected to the input reference clock. This clock must be in the range of 10.0 to 100.0 Mhz. Low skew output clocks. OE - I PAD 14 SDATA VDD I/O PAD 15 4, 8, 12, 16, 17, 21, 25 1, 5, 10, 19, 24, 28 13 SCLOCK VSS VDD I PWR PAD - VDDB - PWR - Power for output clock buffers. VDD - PWR - Pin for device core logic. Buffer Output Enable pin. This pin is low it is used to place all output clocks (CLK1:10) in a tri state condition. This feature facilitates in production board level testing to be easily implemented for the clocks that this device produces. Has internal pull-up resistor. Serial Data for SMBus control interface. This pin receives data streams from the SMBus bus and outputs an acknowledge for valid data. Serial Clock for SMBus control interface. Ground pins for clock output buffers. These pins must be returned to the same potential to reduce output clock skew. Maximum Ratings1 This device contains circuitry to protect the inputs against damage due to high static voltages or electric Voltage Relative to VSS: -0.3V field; however, precautions should be taken to avoid Voltage Relative to VDD: 0.3V application of any voltage higher than the maximum Storage Temperature: Operating Temperature: Maximum Power Supply: -65ºC to + 150ºC -40ºC to +85ºC 7V rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com Document#: 38-07025 Rev. *A 12/17/2002 Page 2 of 8 SC660E SMBus System Clock Buffer for Mobile Applications 2-Wire SMBus Control Interface The 2-wire control interface implements a write only slave interface. The device cannot be read back. Subaddressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2wire control interface allows each clock output to be individually enabled or disabled. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions. Previously set control registers are retained. Serial Control Registers NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) “Command Code “ byte, and 2) “Byte Count” byte. Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged. After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1, Byte2, ....) will be valid and acknowledged. Byte 0: Function Select Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 7 6 3 2 Description reserved reserved reserved reserved SDRAM3 (Active = 1, Forced low = 0) SDRAM2 (Active = 1, Forced low = 0) SDRAM1 (Active = 1, Forced low = 0) SDRAM0 (Active = 1, Forced low = 0) Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com Document#: 38-07025 Rev. *A 12/17/2002 Page 3 of 8 SC660E SMBus System Clock Buffer for Mobile Applications Serial Control Registers (Cont.) Byte 1: Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 27 26 23 22 - Description SDRAM9 (Active = 1, Forced low = 0) SDRAM8 (Active = 1, Forced low = 0) SDRAM7 (Active = 1, Forced low = 0) SDRAM6 (Active = 1, Forced low = 0) reserved reserved reserved reserved Byte 2: Clock Register ( 1 = enable, 0 = Stopped ) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 0 1 1 Pin# 18 11 - Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com Description SDRAM5 (Active = 1, Forced low = 0) SDRAM4 (Active = 1, Forced low = 0) Not Used Not Used Not Used Not Used Not Used Not Used Document#: 38-07025 Rev. *A 12/17/2002 Page 4 of 8 SC660E SMBus System Clock Buffer for Mobile Applications Electrical Characteristics Characteristic Symbol Min Typ Max Units Conditions Input Low Voltage VIL - - 0.8 Vdc - Input High Voltage VIH 2.0 - - Vdc - Input Low Current IIL -66 µA Input High Current IIH 66 µA Output Low Voltage IOL = 40mA VOL - - 0.4 Vdc All Outputs (see buffer spec) Output High Voltage IOH = 30mA VOH 2.4 - - Vdc All Outputs Using 3.3V Power (see buffer spec) Tri-State leakage Current Ioz - - 10 µA Idd66 - - 160 mA Input frequency = 66 Mhz - All outputs on and at 30 pF load Idd100 - - 220 mA Input frequency 100 Mhz - All outputs on and at 30 pF load Static Supply Current Isdd - - 4 mA All outputs disabled no input clock Short Circuit Current ISC 25 - - mA 1 output at a time - 30 seconds Input Rise Time TIR 2.4 - - nS .8 to 2.4 volts Dynamic Supply Current VDD = VDD1 thru VDD5 =3.3V ±5%, , TA = -40ºC to +85ºC Switching Characteristics Characteristic Symbol Min Typ Max Units - 45 50 55 % Measured at 1.5V (50/50 in) Buffer out/out Skew All Buffer Outputs tSKEW - - 250 pS 35 pF Load Measured at 1.5V Buffer input to output Skew tSKEW 2.0 4.0 Output Duty Cycle Conditions 5.0 nS Jitter Cycle to Cycle* TJCC 50 pS @ 35 pF loading Jitter Absolute (Peak to Peak)* TJabs 150 pS @ 35 pF loading VDD = VDD1 thru VDD5 = 3.3V ±5%, , TA = -40ºC to +85ºC *This jitter is additive to the input clock’s jitter. Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com Document#: 38-07025 Rev. *A 12/17/2002 Page 5 of 8 SC660E SMBus System Clock Buffer for Mobile Applications TB40_ Type Buffer Characteristics (All Clock Outputs) Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin 30 - 39 mA Vout = VDD - .5V Pull-Up Current Max IOHmax 75 - 109 mA Vout = 1.5V Pull-Down Current Min IOLmin 30 - 40 mA Vout = 0.4 Pull-Down Current Max IOLmax 75 - 103 mA Vout = 1.2V Dynamic Output Impedance Zo 8 - 15 Ohms 66 and 100 MHz Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin - - 1.33 nS 30 pF Load Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 1.33 nS 30 pF Load VDD = VDD1 thru VDD5 =3.3V ±5%, , TA = -40ºC to +85ºC Package Drawing and Dimensions 28 Pin SSOP Outline Dimensions INCHES SYMBOL C MIN NOM MILLIMETERS MAX MIN NOM MAX A - - 0.079 - - 2.0 A1 0.002 - 0.006 0.05 - 0.15 A2 0.065 0.069 0.073 1.65 1.75 1.85 B 0.009 - 0.015 0.22 - 0.38 C 0.004 - 0.010 0.09 - 0.25 D 0.390 0.402 0.413 9.90 10.20 10.50 E 0.197 0.209 0.220 5.00 5.30 5.60 L H E D a A2 A1 B e Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com A e 0.026 BSC 0.65 BSC H 0.291 0.307 0.323 7.40 7.80 8.20 L 0.022 0.030 0.037 0.55 0.75 0.95 a 0º - 0º - Document#: 38-07025 Rev. *A 8º 8º 12/17/2002 Page 6 of 8 SC660E SMBus System Clock Buffer for Mobile Applications Ordering Information Part Number Package Type SC660EYB 28 PIN SSOP Note: Production Flow Commercial, -40ºC to +85ºC The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI SC660EYB Date Code, Lot # SC660EYB Flow B = Commercial, -40ºC to + 85ºC Package Y = SSOP Revision Device Number Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com Document#: 38-07025 Rev. *A 12/17/2002 Page 7 of 8 SC660E SMBus System Clock Buffer for Mobile Applications Document Title: SC660E SMBus System Clock Buffer for Mobile Applications Document Number: 38-07025 Rev. ** *A ECN No. 106953 122723 Issue Date 06/14/01 12/17/02 Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com Orig. of Change IKA RBI Description of Change Convert from IMI to Cypress Added power-up requirements to maximum ratings information. Document#: 38-07025 Rev. *A 12/17/2002 Page 8 of 8