M61047FP Battery Protection Analog Front End (AFE) IC REJ03F0005-0200 Rev.2.00 Mar 04, 2005 Description The M61047FP is intended to be used as SB: Smart Battery. All functions needed for SB are packed to this M61047FP. The combination use with microcomputer such as M37517 will give various functions such as a detection of SB Remaining Capacity. The reset circuit and the linear regulator for Vcc/Vref of microcomputer are dedicated in M61047FP. So this will help easy design of power circuit design of SB. Features • • • • • • • • • • • All FETs are controlled by microcomputer Built-in low dropout series regulator for microcomputer Built-in battery voltage monitor circuit of each battery cell Built-in output selector, which outputs the voltage each selected battery cell Built-in discharge circuit of each battery cell Built-in voltage detection circuit of each battery cell Built-in FET OFF function controlled by microcomputer Various powers saving function to reduce total power dissipation 3-wire serial data transfer system for communication from microcomputer High Input Voltage Device (Absolute Maximum Rating: 33 V) CMOS monolithic IC Application • Smart Battery System Block Diagram VCC VIN12 Series regulator VREG CFET PCFET DFET FET control circuit DFETCNT CFETCNT RESET VIN1 CS CK VIN2 Reset circuit Serial to Parallel conversion circuit Battery cell voltage detection circuit DI ANALOG VIN3 VIN4 GND Multiplexer circuit Rev.2.00 Mar 04, 2005 page 1 of 23 Battery cell 1-4 voltage analog output M61047FP Pin Arrangement 1 2 3 4 5 6 7 8 9 10 M61047FP CK DI ANALOG CFET DFET PCFET GND VREG VCC DFETCNT 20 19 18 17 16 15 14 13 12 11 CS CFETCNT VIN1 VIN2 VIN3 VIN4 RESET VIN12 N.C. N.C. (Top view) Package: PLSP0020JB-A (20P2F-A) Pin Description Pin No. Pin Name Function 9 8 VCC VREG Power source pin. Power from charger or battery Linear-Regulator output for microcomputer 13 18 VIN12 VIN1 Monitoring charger is connected or not Battery 1 + voltage input 17 16 VIN2 VIN3 Battery 1 – voltage and Battery 2 + voltage input Battery 2 – voltage and Battery 3 + voltage input 15 7 VIN4 GND Battery 3 – voltage and Battery 4 + voltage input Ground and Battery 4 - voltage input 5 4 DFET CFET Discharge FET-Drive Output. The Driver is turned off by Microcomputer Charge FET-Drive Output. The Driver is turned off by Microcomputer 6 14 PCFET RESET Pre-charge FET-Drive Output. The Driver is turned off by Microcomputer Reset signal output to RESET of Microcomputer 3 19 ANALOG CFETCNT Various Analog signal outputs to AD-input of Microcomputer Input of CFET and PCFET control signal from Microcomputer 10 20 DFETCNT CS Input of DFET control signal from Microcomputer During low signal input to this CS, data input to DI is enabled 1 2 CK DI Input of shift clock from Microcomputer. DI's input data is latched by low-to-high edge of this CK Input of 6-bit length serial data from Microcomputer Rev.2.00 Mar 04, 2005 page 2 of 23 M61047FP Absolute Maximum Ratings Ratings Unit Absolute maximum rating Supply voltage Item Vabs Vcc Symbol 33 30 V V Power dissipation Operating temperature range PD Topr1 800 –20 to +85 mW °C Storage temperature range Tstg –40 to +125 °C Reference period CK TSDI THDI DI TSCS THCS CS Figure 1 Interface Timing Rev.2.00 Mar 04, 2005 page 3 of 23 Condition M61047FP Electrical Characteristics (Ta = 25°C, Vcc = 14 V, unless otherwise noted) Block Total Regulator Item Interface Conditioning circuit Typ. Max. Unit Circuit Condition Vsup — — 30 V 1 Supply current 1 Isup 35 75 115 µA 1 Supply current 2 Ips 20 45 70 µA 1 Power save mode (Battery voltage detection: OFF) Supply current 3 Ipd Power down mode Output voltage Vreg Load regulation Battery voltage detection Min. Supply voltage Linear regulation Reset Symbol ∆Vline ∆Vload — — 0.5 µA 1 3.276 3.3 3.333 V 2 VCC = 14V, Iout = 10mA 4.75 5.0 5.25 V 2 VCC = 14V, Iout = 10mA — 2 10 mV 2 VREG = 3.3V VCC = 6.0V to 24V, Iout = 10mA — 4 100 mV 2 VREG = 5.0V VCC = 7.5V to 24V, Iout = 10mA — 3 15 mV 2 VREG = 3.3V VCC = 6.0V, Iout = 50µA to 10mA — 5 150 mV 2 VREG = 5.0V VCC = 7.5V, Iout = 50µA to 50mA Detection voltage Vdet– 2.6 2.75 2.9 V 3 VREG = 3.3V Release voltage Vdet+ 2.9 2.975 3.05 V 3 VREG = 3.3V Input offset voltage Voff 31 206 385 mV 4 Voltage gain Gamp 0.594 0.600 0.606 — 4 Output source current Isource 75 — — µA 5 Output sink current Isink 150 — — µA 5 Detection voltage of battery cell Vmo_max 4.7 — — V 2, 4 DI input H voltage VDIH Vreg–0.5 — Vreg V 6 DI input L voltage VDIL 0 — 0.5 V 6 CS input H voltage VCSH Vreg–0.5 — Vreg V 6 CS input L voltage VCSL 0 — 0.5 V 6 CK input H voltage VCKH Vreg–0.5 — Vreg V 6 CK input L voltage VCKL 0 — 0.5 V 6 DI set-up time TSDI 600 — — ns 6 DI hold time THDI 600 — — ns 6 CS set-up time TSCS 600 — — ns 6 CS hold time THCS 600 — — ns 6 DFETCNT input H voltage VDCH Vreg–0.5 — Vreg V 6 DFETCNT input L voltage VDCL 0 — 0.5 V 6 CFETCNT input H voltage VCCH Vreg–0.5 — Vreg V 6 CFETCNT input L voltage VCCL 0 — 0.5 V 6 CFETCNT sink current ICCH 0.3 1 2 µA 6 VIN1 resistor RON1 250 500 1000 Ω 7 VIN2 resistor RON2 250 500 1000 Ω 7 VIN3 resistor RON3 250 500 1000 Ω 7 VIN4 resistor RON4 250 500 1000 Ω 7 Rev.2.00 Mar 04, 2005 page 4 of 23 VREG = 3.3V (Vreg–Voff1)/Gamp CFETCNT = 3.3V M61047FP Measurement Circuit Measuring Ipd: OFF Except above: ON CFET Ipd, Ips, Isup A PCFET Measuring Ipd: ON Except above: OFF DFET VCC VIN12 VIN1 VREG 0.47µF VIN2 VIN3 DI VIN4 CK Data input 0.5V↔VREG–0.5V CS GND ANALOG Measurement circuit 1 CFET PCFET DFET VCC VIN12 VIN1 VREG I (VREG) 0.47µF V VIN2 VIN3 DI VIN4 CK CS GND ANALOG Measurement circuit 2 Rev.2.00 Mar 04, 2005 page 5 of 23 Data input 0.5V↔VREG–0.5V M61047FP CFET PCFET DFET VCC VIN12 VIN1 VREG V VIN2 RESET VIN3 DI VIN4 Data input 0.5V↔VREG–0.5V CK CS GND ANALOG Measurement circuit 3 CFET PCFET DFET VCC VIN12 VIN1 VREG V1 0.47µF VIN2 V2 VIN3 DI V3 VIN4 Data input 0.5V↔VREG–0.5V CK V4 CS GND ANALOG V Measurement circuit 4 Rev.2.00 Mar 04, 2005 page 6 of 23 M61047FP CFET PCFET DFET VCC VIN12 VIN1 VREG V1 0.47µF VIN2 V2 VIN3 DI V3 VIN4 CK V4 Data input 0.5V↔VREG–0.5V CS Isink GND ANALOG A Isource Measurement circuit 5 CFET PCFET DFET VCC VIN12 VIN1 VREG 14V 3.3V VIN2 VIN3 DI VIN4 CK CFETCNT DFETCNT A A GND Measurement circuit 6 Rev.2.00 Mar 04, 2005 page 7 of 23 CS A ANALOG A A M61047FP CFET PCFET DFET VCC VIN12 A VIN1 VREG A VIN2 A VIN3 A VIN4 V1 0.47µF V2 DI V3 CK V4 CS GND ANALOG Measurement circuit 7 Rev.2.00 Mar 04, 2005 page 8 of 23 Data input 0.5V↔VREG–0.5V M61047FP Operation Description M61047FP is developed for intelligent Li-ion battery pack such as SB in SBS. M61047FP is suitable for Smart Battery. Pair using with Microcomputer such as M37517 and small additional parts will give various functions such as battery remaining capacity detection. All functions are described as follows. Note: SBS: Smart Battery System introduced by Intel and Duracell SB: Smart Battery, which contains 3 or 4 series Li-ion battery cells. Voltage Detection Circuit of Each Li-ion Battery Cell M61047FP can output each battery cell's voltage of 3 or 4 series connection. Built-in buffer amplifier is monitoring each battery voltage. Series Regulator M61047FP contains low drop out series regulator. Microcomputer in SB does not need any additional voltage regulator. Usually, although series regulator is 3.3 V output, it is possible to change to 5 V output by register setup at the time of flash memory rewriting of microcomputer. Reset Circuit Vreg output voltage is checked by Reset circuit of M61047FP. Therefore, lower voltage of Vreg issues RESET signal to stop mull-function of microcomputer. Also, lower voltage after long time's left issues RESET signal to stop mullfunction of microcomputer. This function is useful for safety of long time's left battery. When charger is connected to SB, this circuit will check Vreg voltage, so if Vreg voltage is NOT enough high, this circuit remains low as for RESET signal to microcomputer. Conditioning Circuit M61047FP have a discharge circuit of each cells. It is available for drop of cell voltage for safety purpose. And to shorten the difference voltage among the cells. It can extend the battery pack life. Power Save Function M61047FP contains power save function to control several supply current. It can operate in the three state, usual mode, power save mode, and power down mode. These three modes can be changed by the command from a microcomputer, and can control the consumption current in each mode. 1. Usual mode It is in the state where all circuits are operating. 2. Power save mode In power save mode, consumption current is reduced by stopping voltage detection circuit, and outputting ALALOG output with GND level. If ANALOG output is changed to the battery voltage output or offset voltage output of each cell by the command from a microcomputer, it will change to usual mode. In addition, the regulator circuit is operating in a power save mode. 3. Power down mode In power down mode, all circuits will be stopped. The shift to power down mode and operation at the time of resume from power down mode are explained below using Figure 2. Rev.2.00 Mar 04, 2005 page 9 of 23 M61047FP • Enter Power Down Mode Microcomputer issues power down command to M61047FP after microcomputer detects that battery voltage is too low. After this command, the DFET pin is set to 'high' and the VIN12 pin is pulled down by internal resistor to be set 'low' and series regulator are turned off. In the power down mode, the M61047FP operation is impossible. And CFET, DFET and PCFET are set to 'high'. (In this situation, discharging is forbidden.) At this time, supply current becomes max. 0.5 µA, so drops of battery voltage is prevented. • Resume from Power Down Mode After entering Power Down mode, the series regulator will begin operation when charger is connected (VIN12 pin is high). The RESET will output low to high signal when Vreg is over reset level voltage. Microcomputer will begin operation and send command to resume M61047FP from power down mode. VIN12 DFET VCC PCFET CFET GND level in discharging FET control circuit Series regulator VREG DFETCNT CFETCNT RESET RESET circuit CS CK Serial to pallarel conversion circuit DI Figure 2 Function After Detecting Over-Discharge Rev.2.00 Mar 04, 2005 page 10 of 23 VIN1 M61047FP Block Diagram Description Battery Voltage Detection Circuit The M61047FP battery voltage detection circuit is shown in Figure 3. This circuit is composed of switch, buffer amplifier, reference voltage section and logic circuit. Microcomputer selects detecting voltage before logic circuit controls the connection of switches. This connection decides which cell voltage (Vbat1, Vbat2, Vbat3, Vbat4) should be output from Analog out pin. Besides offset voltage can be output. In Power Down mode, supply current in this block is close to zero because all switches are off. Note: Regard 100 µs as the standard of settling time by voltage change in this block. S11 VIN1 VBAT1 Switch control From Serial to Parallel conversion circuit S22 VIN2 S21 Logic circuit VBAT2 S32 VIN3 S31 VBAT3 S42 – VIN4 + To Multiplexer circuit S41 VBAT4 S02 GND VREF S01 Figure 3 Battery Voltage Detection Circuit Table 1 Turned on Switches Function Turn on Switch (refer to Figure 3) VBAT1_OUTPUT VBAT2_OUTPUT S11, S22 S21, S32 VBAT3_OUTPUT VBAT4_OUTPUT S31, S42 S41, S02 VBAT1_OFFSET VBAT2_OFFSET S21, S22 S31, S32 VBAT3_OFFSET VBAT4_OFFSET S41, S42 S01, S02 Rev.2.00 Mar 04, 2005 page 11 of 23 M61047FP Analog Output Selector Analog output selector block is shown in Figure 4. The command from microcomputer determines whether GND is outputted to an analog terminal, or the voltage chosen in the battery voltage detection circuit is outputted. At the time of GND output, since the battery voltage detection circuit stops, M61047FP goes into power save mode. From Serial to Parallel conversion circuit ANALOG Analog output selector Battery voltage detection circuit – + VREF Figure 4 Analog Output Selector Rev.2.00 Mar 04, 2005 page 12 of 23 M61047FP Series Regulator Series regulator is shown in Figure 5. Pch MOS transistor is used for output driver. The output voltage can be adjusted by M61047FP itself. So the external resistor is not required. Usually, although series regulator is 3.3 V output, it is possible to change to 5 V output by register setup at the time of flash memory rewriting of microcomputer. Note: There is a diode put between Vcc and Vreg terminal to prevent the invert current from damaging this IC when Vcc Voltage is higher than Vreg voltage. So please always keep Vreg voltage lower than Vcc+0.3 V. Set a condenser on output to suppress input changes or load changes. In order to suppress input change and load change, please attach a 0.47 µF capacitor to VREG output. Regard 10 ms as the standard of settling time by input change/load change/output change. VCC + – VREG VREF S51 S52 R1 R2 R3 GND Switch control Serial to Parallel conversion circuit Figure 5 Series Regulator Rev.2.00 Mar 04, 2005 page 13 of 23 M61047FP Reset Circuit The M61047FP reset circuit is shown in Figure 6. This circuit is composed of comparator, reference voltage section and breeder resistor. Hysterics is given to detection voltage and release voltage. The reset output is Nch open drain structure so the reset delay time depends on external CR value. The reset circuit monitoring Vreg output to prevent microcomputer abnormal operation when Vcc voltage goes down abnormally. VREG VREG R1 + – RESET R2 VREF Rh GND Figure 6 Reset Circuit Rev.2.00 Mar 04, 2005 page 14 of 23 M61047FP Conditioning Circuit The M61047FP conditioning circuit is shown in Figure 7. This circuit is composed of switch, resistor and logic circuit. According to the serial data from microcomputer, the logic circuit can individually control the switches (S61, S62 … etc.) to do individual cell discharge. Moreover, it is possible to also make from 1 cell to 4 cells discharge similarly by sending serial data two or more times. VIN1 S61 VBAT1 R61 VIN2 S62 VBAT2 Switch control From Serial to Parallel conversion circuit R62 VIN3 Logic circuit S63 VBAT3 R63 VIN4 S64 VBAT4 R64 GND Figure 7 Conditioning Circuit Rev.2.00 Mar 04, 2005 page 15 of 23 M61047FP Resister Map Address Table 2 Address Establishment Data Data Contents D5 D4 D3 D2 D1 D0 Reset Battery voltage output FET control 0 0 0 0 0 1 0 1 0 — — — — — — — — — — Refer to table 3 Refer to table 4 Multiplexer select Regulator 0 1 1 0 1 0 — — — — — — Refer to table 5 Refer to table 6 Conditioning circuit Don’t care 1 1 0 1 1 0 — — — — — — Refer to table 7 — Don’t care 1 1 1 — — — — Data Table 3 Battery Voltage Output D2 D1 D0 Name Function 0 0 0 0 0 1 VBAT1_OUTPUT VBAT2_OUTPUT BAT1 voltage monitor BAT2 voltage monitor 0 0 1 1 0 1 VBAT3_OUTPUT VBAT4_OUTPUT BAT3 voltage monitor BAT4 voltage monitor 1 1 0 0 0 1 VBAT1_OFFSET VBAT2_OFFSET Offset voltage output at BAT1 monitor Offset voltage output at BAT2 monitor 1 1 1 1 0 1 VBAT3_OFFSET VBAT4_OFFSET Offset voltage output at BAT3 monitor Offset voltage output at BAT4 monitor Note: Analog terminal output GND level when system reset. (All switches for battery voltage detect circuit are turned off.) Regard 100µs as the standard of settling time by each change of ANALOG output. Table 4 FET Control Function D2 D1 D0 Name CFET DFET PCFET 0 0 0 0 0 1 0 1 0 FCNT_AH FCNT_PL FCNT_DL High High High High High Low High Low High 0 1 1 0 1 0 FCNT_CH FCNT_CL High Low Low High Low High 1 1 0 1 1 0 FCNT_DH FCNT_PH Low Low High Low Low High 1 1 1 FCNT_AL Low Low Low Note: CFET, DFET and PCFET terminal are high when system reset. Rev.2.00 Mar 04, 2005 page 16 of 23 M61047FP Table 5 Multiplexer Control (Analog Output Control) D2 D1 D0 Name Function 0 0 0 0 0 1 0 1 0 MP_GND1 MP_RUN MP_GND2 GND output Battery voltage output select GND output 0 1 1 0 1 0 MP_GND3 — GND output Don’t care 1 1 0 1 1 0 — — Don’t care Don’t care 1 1 1 — Don’t care Notes BAT1 voltage monitor All switches for battery voltage detect are OFF. BAT4 offset voltage Note: Analog terminal output GND level when system reset. Regard 100µs as the standard of settling time by each change of ANALOG output. Table 6 Regulator D2 D1 D0 Name Function Notes 0 0 0 0 0 1 0 1 0 VREG_33 VREG_OFF VREG_50 VREG = 3.3 V VREG = 0 V (Regulator turned off) VREG = 5.0 V 0 1 1 0 1 0 VREG_33 Don’t care VREG = 3.3 V 1 1 0 1 1 0 Don’t care Don’t care Power Down Command 1 1 1 Don’t care Note: The regulator output 3.3 V when system reset. All functions of M61047FP are stopped. But if the charger is connected then M61047FP will not enter power down mode. Regard 20 ms as the standard of settling time by change of VREG output. Table 7 Conditioning Circuit Function D2 D1 D0 Name BAT1_SW BAT2_SW BAT3_SW BAT4_SW 0 0 0 0 0 1 CD_OFF CD_RON11 OFF ON OFF Don’t care OFF Don’t care OFF Don’t care 0 0 1 1 0 1 CD_RON21 CD_RON31 Don’t care Don’t care ON Don’t care Don’t care ON Don’t care Don’t care 1 1 0 0 0 1 CD_RON41 CD_RON12 Don’t care ON Don’t care Don’t care Don’t care Don’t care ON Don’t care 1 1 1 1 0 1 CD_RON22 CD_RON32 Don’t care Don’t care ON Don’t care Don’t care ON Don’t care Don’t care Note: Conditioning circuit is floating when system reset. By transmitting data two or more times, BAT1 to BAT4 arbitrary cells can be turned on simultaneously. Rev.2.00 Mar 04, 2005 page 17 of 23 M61047FP Digital Data Format The block diagram of the serial to parallel conversion circuit of serial data transmission is shown in Figure 8, and a timing chart is shown in Figure 9, respectively. After setting CS terminal to Low, serial data is read into the inside of IC in an order from LSB (D0) synchronizing with the stand-up of CK terminal. If CS terminal is set to High when it inputs by 6 bits, the contents of a 6-bit shift register are latched to an internal latch circuit after serial to parallel conversion. MSB First Last DI LSB 6-bit shift register CK D5 CS D4 Address D3 D2 D1 D0 Decoder Latch Latch Latch Latch MPX MPX MPX MPX MPX Vreg control Battery voltage output Multiplexer Conditioning control control FET control Latch Figure 8 Serial to Parallel Conversion Circuit LSB DI MSB D0 D1 D2 D3 D4 D5 CK CS Figure 9 Timing Chart Direct FET Control It is possible to control direct FET by sending a signal to DFETCNT terminal or CFETCNT terminal other than serial data transmission from a microcomputer. If DFETCNT terminal is set to high, DFET terminal will be set to high, and if CFETCNT terminal is set to high, CFET terminal and PCFET terminal will be set to high. Priority is given to this function regardless of serial data communications. Rev.2.00 Mar 04, 2005 page 18 of 23 M61047FP Timing Chart Battery voltage (V) Charging Sequence 5 Vbat4 reaches overcharge detect voltage 4 3 From bottom: Vbat1, Vbat2, Vbat3, Vbat4 2 Charging time 1 0 CFET (V) 20 15 10 5 Instruction from microprocessor Off during initialization Start of charging Instruction from microprocessor End of charging 0 PCFET (V) 20 15 10 5 Instruction from microprocessor Off during initialization Instruction from microprocessor Start of precharging End of charging 0 DFET (V) 20 15 10 Instruction from microprocessor Off during initialization 5 Start of charging VREG, RESET (V) Battery voltage (V) 0 20 VCC pin 15 10 VIN_1 pin 5 0 4 3 2 1 0 VREG Charger connected RESET Microprocessor operation start ANALOG (V) 3 2 1 Instruction from microprocessor 0 Note: A constant voltage battery charger is used. Rev.2.00 Mar 04, 2005 page 19 of 23 VBAT1 monitor VBAT3 VBAT2 monitor monitor VBAT4 monitor M61047FP Battery voltage (V) Discharge Sequence 5 From top: Vbat1, Vbat2, Vbat3, Vbat4 4 Self-discharge time 3 2 Vbat4 reaches excess discharge detect voltage Discharge time 1 0 CFET (V) 20 15 Instruction from microprocessor 10 5 0 PCFET (V) 20 15 10 Instruction from microprocessor 5 0 DFET (V) 20 Instruction from microprocessor 15 10 5 End of discharge Off in power-down mode Battery voltage (V) 20 VREG, RESET (V) 0 4 15 VIN_1 pin 10 VIN_12 pin Pulled down to ground potential when discharge prohibited 5 0 3 VREG ANALOG (V) Instruction from microprocessor RESET 2 System stop 1 0 3 2 1 0 Rev.2.00 Mar 04, 2005 page 20 of 23 VBAT1 monitor VCC pin VBAT2 VBAT3 VBAT4 monitor monitor monitor M61047FP Application Circuit 1kΩ + terminal 10kΩ VIN12 0.22µF DFET 6.8Ω VCC PCFET CFET 1kΩ VIN1 VREG 0.22µF VBAT1 0.47µF 1kΩ VIN2 CS 0.22µF VBAT2 CK MCU M37517F8HP DI 1kΩ M61047FP VIN3 0.22µF VBAT3 RESET CFETCNT 1kΩ VIN4 DFETCNT 0.22µF VBAT4 GND ANALOG – terminal Figure 10 Application Circuit for 4 Cell Battery Rev.2.00 Mar 04, 2005 page 21 of 23 M61047FP 1kΩ + terminal 10kΩ VIN12 0.22µF DFET 6.8Ω VCC PCFET CFET VIN1 VREG 0.47µF 1kΩ VIN2 CS 0.22µF VBAT2 CK MCU M37517F8HP DI 1kΩ M61047FP VIN3 0.22µF VBAT3 RESET CFETCNT 1kΩ VIN4 DFETCNT 0.22µF VBAT4 GND ANALOG – terminal Figure 11 Application Circuit for 3 Cell Battery Rev.2.00 Mar 04, 2005 page 22 of 23 M61047FP Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A 20P2F-A 0.1g 11 E *1 HE 20 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. F 1 Index mark 10 c A2 A1 Reference Symbol *2 Dimension in Millimeters Min Nom Max D 6.4 6.5 6.6 E 4.3 4.4 4.5 L D A A2 1.15 A *3 e y bp Detail F 1.45 A1 0 0.1 0.2 bp 0.17 0.22 0.32 c 0.13 0.15 0° HE 6.2 6.4 6.6 e 0.53 0.65 0.77 0.3 0.5 y L Rev.2.00 Mar 04, 2005 page 23 of 23 0.2 10° 0.10 0.7 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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