N CLC426 Wideband, Low-Noise, Voltage Feedback Op Amp General Description Features The CLC426 combines an enhanced voltage-feedback architecture with an advanced complementary bipolar process to provide a high-speed op amp with very low noise (1.6nV/√Hz & 2.0pA/√Hz) and distortion (-62/-68dBc 2nd/3rd harmonics at 1Vpp and 10MHz). ■ Providing a wide 230MHz gain-bandwidth product, a fast 400V/µs slew rate and very quick 16ns settling time to 0.05% , the CLC426 is the ideal choice for high speed applications requiring a very widedynamic range such as an input buffer for high-resolution analog-todigital converters. The CLC426 is internally compensated for gains ≥ 2V/V and can easily be externally compensated for unity-gain stability in applications such as wideband low-noise integrators. The CLC426 is also equipped with external supply current adjustment which allows the user to optimize power, bandwidth, noise and distortion performance for each application. ■ ■ ■ ■ ■ ■ Wide gain-bandwidth product: 230MHz Ultra-low input voltage noise: 1.6nV/√Hz Very low harmonic distortion: -62/-68dBc Fast slew rate: 400V/µs Adjustable supply current Dual ±2.5 to ±5V or single 5 to 12V supplies Externally compensatable Applications Active filters & integrators Ultrasound ■ Low-power portable video ■ ADC/DAC buffer ■ Wide dynamic range amp ■ Differential amps ■ Pulse/RF amp ■ ■ The CLC426's combination of speed, low noise and distortion and low dc errors will allow high-speed signal conditioning applications to achieve the highest signal-to-noise performance. To reduce design times and assist board layout, the CLC426 is supported by an evaluation board and SPICE simulation model available from National. CLC426 Wideband, Low-Noise, Voltage Feedback Op Amp June 1999 For even higher gain-bandwidth voltage-feedback op amps see the 1.9GHz CLC425 (Av ≥ 10V/V) or the 5.0GHz CLC422 (Av ≥ 30V/V). Typical Application Wide Dynamic Range Sallen-Key Band Pass Filter 2nd-Order (20MHz, Q=10, G=2) 1999 National Semiconductor Corporation Printed in the U.S.A. Pinout DIP & SOIC NC 1 Vinv 2 - 7 +Vcc Vnon-inv 3 + 6 Vout -Vcc 4 8 Rp (optional) 5 Ext. Comp. (optional) http://www.national.com CLC426 Electrical Characteristics (V CC PARAMETERS Ambient Temperature CONDITIONS CLC426 FREQUENCY DOMAIN RESPONSE gain bandwidth product Vout < 0.5Vpp Vout < 0.5Vpp -3dB bandwidth, Av=+2 Vout < 5.0Vpp gain flatness Vout < 0.5Vpp peaking DC to 200MHz rolloff DC to 30MHz linear phase deviation DC to 30MHz TIME DOMAIN RESPONSE rise and fall time 1V step settling time 2V step to 0.05% overshoot 1V step slew rate 5V step DISTORTION AND NOISE RESPONSE 1Vpp,10MHz 2nd harmonic distortion 3rd harmonic distortion 1Vpp,10MHz equivalent input noise op amp only voltage 1MHz to 100MHz current 1MHz to 100MHz STATIC DC PERFORMANCE open-loop gain input offset voltage average drift input bias current average drift input offset current average drift power-supply rejection ratio common-mode rejection ratio supply current DC DC DC pin #8 open, RL= ∞ MISCELLANEOUS PERFORMANCE input resistance common-mode differential-mode input capacitance common-mode differential-mode output resistance closed loop output voltage range RL= ∞ RL=100Ω input voltage range common mode output current = ± 5V; AV = +2V/V; Rf =100 Ω; RL = 100 Ω ; unless noted) =100Ω 100Ω TYP +25°C +25°C MIN/MAX RATINGS 0 to +70°C -40 to +85°C UNITS 230 130 50 170 90 25 120 70 22 100 55 20 MHz MHz MHz 0.6 0.0 0.2 1.5 0.6 1.0 2.2 1.0 1.5 2.5 1.0 1.5 dB dB ° 2.3 16 5 400 3.5 20 15 300 5.0 24 15 275 6.5 24 18 250 ns ns % V/µs 1 - 62 - 68 - 52 - 58 - 47 - 54 - 45 - 54 1.6 2.0 2.0 3.0 2.3 3.6 2.6 4.6 nV/√Hz pA/√Hz 64 1.0 3 5 90 0.3 5 73 70 11 60 2.0 --25 --3 --65 62 12 54 2.8 10 40 600 5 25 60 57 13 54 2.8 10 65 700 5 50 60 57 15 dB mV µV/°C µA nA/°C µA nA/°C dB dB mA 500 750 2.0 2.0 0.07 ± 3.8 ± 3.5 ± 3.7 ± 70 250 200 3.0 3.0 0.1 ± 3.5 ± 3.2 ± 3.5 ± 50 125 50 3.0 3.0 0.2 ± 3.3 ± 2.6 ± 3.3 ± 40 NOTES dBc dBc 125 25 3.0 3.0 0.2 ± 3.3 ± 1.3 ± 3.3 + 35, -20 A A A A kΩ kΩ pF pF Ω V V V mA Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Ordering Information Absolute Maximum Ratings supply voltage short circuit current common-mode input voltage differential input voltage maximum junction temperature storage temperature lead temperature (soldering 10 sec) ESD rating ±7V (note 2) ±V cc ±10V +150°C -65°C to+150°C +300°C 2000V Notes A)J-level: spec is 100% tested at +25°C. 1) Minimum stable gain with out external compensation is +2 or -1V/V, the CLC426 is unity-gain stable with external compensation. 2) Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA. 3) See text for compensation techniques. http://www.national.com Model Temperature Range CLC426AJP CLC426AJE CLC426A8B -40°C to +85°C -40°C to +85°C -55°C to +125°C Description 8-pin PDIP 8-pin SOIC 8-pin CerDIP, MIL-STD-883 Package Thermal Resistance Package θ JC θ JA Plastic (AJP) Surface Mount (AJE) CerDIP 70°C/W 60°C/W 40°C/W 125°C/W 140°C/W 130°C/W Reliability Information Transistor Count 2 52 3 http://www.national.com Application Discussion produces the optimal response of the CLC426 at unity gain. The plot labeled "Open-Loop Gain vs. Compensation Cap." illustrates the CLC426's open-loop behavior for various values of compensation capacitor. This plot also illustrates one technique of bandlimiting the device by reducing the open-loop gain resulting in lower closed-loop bandwidth. Fig. 1 shows the effect of external compensation on the CLC426's pulse response. Introduction The CLC426 is a wide bandwidth voltage-feedback operational amplifier that is optimized for applications requiring wide dynamic range. The CLC426 features adjustable supply current and external compensation for the added flexibility of tuning its performance for demanding applications. The Typical Performance section illustrates many of the performance trade-offs. Although designed to operate from ±5Volt power supplies, the CLC426 is equally impressive operating from a single +5V supply. The following discussion will enable the proper selection of external components for optimum device performance in a variety of applications. External Compensation The CLC426 is stable for noise gains ≥2V/V. For unity-gain operation, the CLC426 requires an external compensation capacitor (from pin 5 to ground). The plot located in the Typical Performance section labeled "Frequency Response vs Compensation Cap." illustrates the CLC426's typical AC response for different values of compensation capacitor. From the plot it is seen that a value of 15pF http://www.national.com Fig. 1 4 Supply Current Adjustment The CLC426's supply current can be externally adjusted downward from its nominal value to less than 2mA by adding an optional resistor (Rp) between pin 8 and the negative supply as shown in fig 2. The plot labeled "OpenLoop Gain vs. Supply Current" illustrates the influence that supply current has over the CLC426's open-loop Fig. 4 tive Load". Faster Settling The circuit of fig. 5 shows an alternative method for driving capacitive loads that results in quicker settling times. The small series-resistor, Rs, is used to decouple the CLC426's open-loop output resistance, Rout, from the load capacitance. The small feedback-capacitance, Cf, is used to Fig. 2 response. From the plot it is seen that the CLC426 can be compensated for unity-gain stability by simply lowering its supply current. Therefore lowering the CLC426's supply current effectively reduces its open-loop gain to the point that there is adequate phase margin at unity gain crossover. The plot labeled "Supply Current vs. Rp" provides the means for selecting the value of Rp that produces the desired supply current. The curve in the plot represents nominal processing but a ±12% deviation over process can be expected. The two plots labeled "Voltage Noise vs. Supply Current" and "Current Noise vs. Supply Current" illustrate the CLC426 supply current's effect over its input-referred noise characteristics. Fig. 5 Driving Capacitive Loads The CLC426 is designed to drive capacitive loads with the addition of a small series resistor placed between the output and the load as seen in fig. 3. Two plots located in provide a high-frequency bypass between the output and inverting input. The phase lead introduced by Cf compensates for the phase lag due to CL and therefore restores stability. The following equations provide values of Rs and Cf for a given load capacitance and closed-loop amplifier gain. R s = R out Fig. 3 2 R R C1 = 1 + f CL out R R g g the Typical Performance section illustrate this technique for both frequency domain and time domain applications. The plot labeled "Frequency Response vs. Capacitive Load" shows the CLC426's resulting AC response to various capacitive loads. The values of Rs in this plot were chosen to maximize the CLC426's AC response (limited to ≤1dB peaking). The second plot labeled "Settling Time vs. Capacitive Load" provides the means for the selection of the value of Rs which minimizes the CLC426's settling time. As seen from the plot, for a given capacitive load Rs is chosen from the curve labeled "Rs". The resulting settling time to 0.05% can then be estimated from the curve labeled "Ts to 0.05%". The plot of fig. 4 shows the CLC426's pulse response for various capacitive loads where Rs has been chosen from the plot labeled "Settling Time vs. Capaci- R f ; where R out ≈ 6Ω R g Eq. 1 Eq. 2 The plot in fig. 6 shows the result of the two methods of capacitive load driving mentioned above while driving a 100pF||1kΩ load. 5 Fig. 6 http://www.national.com signal bandwidth = Single-Supply Operation The CLC426 can be operated with single power supply as shown in fig. 7. Both the input and output are capacitively 1 GBW 2 2πR f C t Eq. 5 Sallen-Key Active Filters Fig. 7 C2 = coupled to set the dc operating point. DAC Output Buffer The CLC426's quick settling, wide bandwidth and low differential input capacitance combine to form an excellent I-to-V converter for current-output DACs in such applications as reconstruction video. The circuit of fig. 8 implements a low-noise transimpedance amplifier commonly used to buffer high-speed current output devices. The transimpedance gain is set by Rf. A feedback capacitor, Cf, is needed in order to compensate for the 1 5 G = 1+ R1 = 2 R2 = R3 = C1 Rf Rg , desired mid − band gain Q GC1(2 πf ) , where f = desired center frequency 2 2 GR1 1 + 4.8Q − 2G + G + 1 2 4.8Q − 2G + G 2 2 2 5GR1 1 + 4.8Q − 2G + G + G − 1 2 4Q The CLC426 is well suited for Sallen-Key type of active filters. Fig. 9 shows the 2nd order Sallen-Key band-pass filter topology and design equations. Fig. 9 To design the band-pass, begin by choosing values for Rf and Rg, for example R f = R g = 200Ω . Then choose reasonable values for C1 and C2 (where C1=5C2) and then compute R1. R2 and R3 can then be computed. For optimum high-frequency performance it is recommended that the resistor values fall in the range of 10Ω to 1kΩ and the capacitors be kept above 10pF. The design can be further improved by compensating for the delay through the op amp. For further details on this technique, please request Application Note OA-21 from National Semiconductor Corporation. Fig. 8 inductive behavior of the closed-loop frequency response of this type of circuit. Equation 3 shows a means of calculating the value of Cf which will provide conditions for a maximally-flat signal frequency response with approximately 65° phase margin and 5% step-response overshoot. Notice that Ct is the sum of the DAC output capacitance and the differential input capacitance of the CLC426 which is located in its Electrical Characteristics Table. Notice also that CLC426's gain-bandwidth product (GBW) is also located in the same table. Equation 5 provides the resulting signal bandwidth. Cf = 2 Ct 2πR f GBW C t = C out + C in dif http://www.national.com Printed Circuit Board Layout Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency-response peaking and possible circuit oscillation, see OA-15 for more information. National suggests the CLC730013 (through-hole) or the CLC730027 (SOIC) evaluation board as a guide for highfrequency layout and as an aid in device testing and characterization. Eq. 3 Eq. 4 6 This page intentionally left blank. 7 http://www.national.com CLC426 Wideband, Low-Noise, Voltage Feedback Op Amp Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. 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