AD SSM2404P

a
FEATURES
“CIickless” Bilateral Audio Switching
Four SPST Switches in a 20-Pin Package
Ultralow THD+N: 0.0008% @ 1 kHz (2 V rms,
R L = 100 kV)
Low Charge Injection: 35 pC typ
High OFF Isolation: –100 dB typ (RL = 10 kV @ 1 kHz)
Low Crosstalk: –94 dB typ (R L = 10 kV @ 1 kHz)
Low ON Resistance: 28 V typ
Low Supply Current: 900 mA typ
Single or Dual Supply Operation: +11 V to +24 V or
65.5 V to 612 V
Guaranteed Break-Before-Make
TTL and CMOS Compatible Logic Inputs
Low Cost-Per-Switch
GENERAL DESCRIPTION
The SSM2404 integrates four SPST analog switches in a single
20-pin package. Developed specifically for high performance
audio applications, distortion and noise are negligible over the
full operating range of 20 Hz to 20 kHz. With very low charge
injection of 35 pC, “clickless” audio switching is possible, even
under the most demanding conditions.
Switch control is realized by conventional TTL or CMOS
logic. Guaranteed “break-before-make” operation assures that
all switches in a large system will open before any switch
reaches the ON state.
Single or dual supply operation is possible. Additional features
include –100 dB OFF isolation, –94 dB crosstalk and 28 Ω ON
resistance. Optional current-mode switching permits an
extended signal-handling range. Although optimized for large
load impedances, the SSM2404 maintains good audio
performance even under low load impedance conditions.
Quad Audio Switch
SSM2404
BLOCK DIAGRAM OF ONE SWITCH CHANNEL
V–
CONTROL
LOGIC INTERFACE
AND
BREAK-BEFORE-MAKE
CONTROL
SW1 A
RAMP
GENERATOR
DIGITAL
CONTROL
SW1 B
V+
PIN CONNECTIONS
Epoxy Mini-DIP (P Suffix)
and SOIC (S Suffix)
SW1 A
1
AGND
2
SW1 B
3
SW1
SW1
SW4
20
SW4 A
19
AGND
18
SW4 B
17
V+
DGND
4
SW1 CONTROL
5
16
SW4 CONTROL
SW2 CONTROL
6
15
SW3 CONTROL
NC*
7
14
V–
SW2 B
8
13
SW3 B
AGND
9
12
AGND
SW2 A
10
11
SW3 A
O
TOP VIEW
(Not
to Scale)
SSM2404
SW2
SW3
NC = NO CONNECT
*CONNECT TO ANALOG GROUND
FOR BEST NOISE ISOLATION
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
SSM2404–SPECIFICATIONS
(VS = 612 V, TA = +258C, unless otherwise noted.
Typical specifications apply at TA = +258C.)
Parameter
Symbol
Conditions
AUDIO PERFORMANCE
Total Harmonic Distortion Plus Noise
THD+N
@ 1 kHz, with 80 kHz Filter,
RL = 100 kΩ, VIN = 2 V rms
20 Hz to 20 kHz
20 Hz to 20 kHz
Spectral Noise Density
Wideband Noise Density
ANALOG SIGNAL SECTION
Analog Voltage Range
Analog Current Range
ON Resistance
RON Matching
ON Leakage Current
OFF Leakage Current
Charge Injection
ON-State Input Capacitance
OFF-State Input Capacitance
OFF Isolation
Channel-to-Channel Crosstalk
CONTROL SECTION
Digital Input High
Digital Input Low
Turn-On Time1
Turn-Off Time2
Break-Before-Make Time Delay
Logic Input Current
Logic HI
Logic LO
POWER SUPPLY
Supply Voltage Range
Positive Supply Current
Negative Supply Current
Ground Current
en
en p-p
Min
Typ
Max
Units
0.0008
0.8
0.6
%
nV/√Hz
µV p-p
± 12
± 10
28
45
1
0.1
+20
0.1
+20
35
31
17
–100
–94
V
mA
Ω
%
nA
nA
pC
pF
pF
dB
dB
VA
IA
RON
RON Match
IS(ON)
IS(OFF)
Q
CON
COFF
ISO(OFF)
CT
VINH = 2.4 V, IA = ± 2 mA
VINH = 2.4 V, VA = 0 V
IA = ± 10 mA, VA = ± 10 V dc
IA = ± 10 mA, VA = 0 V
VA = ± 10 V
VA = ± 10 V
VINH
VINL
tON
tOFF
tON-tOFF
DGND = 0 V
DGND = 0 V
See Test Circuit
See Test Circuit
2.4
0
VINH = 2.4 V
VINL = 0.8 V
–1000 1.3
–1000 1.0
+1000 nA
+1000 nA
Single Supply
Dual Supply
All Channels On
All Channels On
All Channels On
+11
± 5.5
+24
± 12
5
VS
ISY+
ISY–
–20
–20
VA = 5 V rms
VA = 5 V rms
VA = 50 mV rms, f = 1 kHz, RL = 10 kΩ
VA = 50 mV rms, f = 1 kHz, RL = 10 kΩ
8
5
3
–1.5
–2.0
0.9
–0.6
–0.3
VS
0.8
50
30
20
V
V
ms
ms
ms
V
V
mA
mA
mA
NOTES
1
Turn-on time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the final value.
2
Turn-off time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the initial value.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27 V
Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 13.5 V
Analog Input Voltage (VA) . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Logic Input Voltage (VINL/INH) . . . . . . . . . . . . . . . . . . . . . . VS
Maximum Current Through Any Switch . . . . . . . . . . . 20 mA
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Thermal Resistance1
20-Pin Plastic DIP (P): θJA = 74, θJC = 32 . . . . . . . . . °C/W
20-Pin SOIC (S): θJA = 90, θJC = 27 . . . . . . . . . . . . . . °C/W
ORDERING GUIDE
Model
Operating
Temperature
Range
Package
Package
Option*
SSM2404P
SSM2404S
–40°C to +85°C
–40°C to +85°C
20-Pin Plastic DIP
20-Pin SOIC
N-20
R-20
*N = Plastic DIP, R = SOIC.
NOTE
1
θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for P-DIP package.
–2–
REV. B
SSM2404
VA (IN) = 50mVRMS
f = 20Hz TO 100kHz
VA (IN)
VA (OUT)
R L = 10kΩ AND 100kΩ
50Ω
OFF ISOLATION = 20 LOG
VA (OUT)
VA (IN)
OFF Isolation Test Circuit
HIGH
LOGIC
INPUT LOW
1.4V
t r 100ns
t f 100ns
1.4V
Figure 2. Headroom (VS = ± 12 V, f = 1 kHz, with
80 kHz Filter)
LOW
DC VOLTAGE
VA (IN)
CLOSED
OPEN
VA (OUT)
50%
50%
OPEN
1.0
t ON
t OFF
tON/tOFF Timing Diagram
THD + N – %
0.1
+12V
V+
VA (IN)
0.01
VA (OUT)
SWITCH
CONROL
0.001
GND
V–
0.0001
100
–12V
1k
10k
LOAD RESISTANCE – Ω
100k
Figure 3. THD+N vs. Load (VS = ± 12 V, VA = 2 V rms,
f = 1 kHz, with 80 kHz Filter)
Test Circuit for tON/tOFF Timing Specification, tON/tOFF
Switching Response, and ON/OFF Transition Photos
THD + N – %
0.01
0.001
0.0001
0
Figure 1. THD+N vs. Frequency (VS = ± 12 V,
VA = 2 V rms, with 80 kHz Filter)
REV. B
±4
±8
±12
SUPPLY VOLTAGE – V
Figure 4. THD+N vs. Supply Voltage (VA = 2 V rms,
f = 1 kHz, RL = 100 kΩ, with 80 kHz Filter)
–3–
SSM2404
9.5
OUTPUT VOLTAGE SWING – VRMS
9.0
TA = 25°C
VS = ±12V
f = 20kHz
8.5
8.0
7.5
7.0
6.5
6.0
100
1k
10k
100k
LOAD RESISTANCE – Ω
Figure 8. Output Voltage Swing vs. Load Resistance
Figure 5. Frequency Response (VS = ± 12 V,
VA = 1 V rms, RL = 100 kΩ)
10
CH A: 8.00µV FS
MKR: 0.11µV/ Hz
0Hz
MKR: 20 000Hz
OUTPUT VOLTAGE SWING – VRMS
9
1.00µV/DIV
8
7
TA = 25°C
R L = 100kΩ
f = 20kHz
0.1% THD + N
6
5
4
3
2
1
25kHz
BW: 150Hz
0
±4
±6
±10
±8
±12
SUPPLY VOLTAGE – Volts
Figure 9. Output Voltage Swing vs. Supply Voltage
Figure 6. SSM2404 Spectral Noise Density en
[5 Devices (20 Switches) Chained Together]
–20
TA = 25°C
VS = ±12V
VA = 50mVRMS
–30
–40
OFF ISOLATION – dB
10V
100
0V
0V
INPUT
90
OUTPUT
10
–50
R L = 100k
–60
–70
–80
R L = 10k
–90
–100
0%
10V
–110
5µs
–120
10
Figure 7. Square Wave Response (TA = +25°C,
VS = ± 12 V, RL = 100 kΩ, f = 20 kHz)
100
1k
FREQUENCY – Hz
10k
100k
Figure 10. OFF-Isolation vs. Frequency
–4–
REV. B
SSM2404
50
0
CROSSTALK – dB
–30
SWITCH LEAKAGE CURRENT – nA
TA = 25°C
VS = ±12V
VA = 50mVRMS
–15
–45
–60
R L = 100k
–75
R L = 10k
–90
–105
–120
40
VS = ±12V
VINL = 0.8V
RL = ∞
–40°C TO +85 °C
30
20
10
0
–10
–135
–150
10
100
1k
FREQUENCY – Hz
10k
–20
–10
100k
0
5
10
ANALOG INPUT VOLTAGE – Volts
Figure 11. Channel-to-Channel Crosstalk vs. Frequency
(Worst Case Conditions, as Measured Between
Switches 1 and 4, or 2 and 3)
Figure 14. Leakage Current vs. Analog Voltage
50
20
VS = ±12V
RL = ∞
IA = 10mA
40
VS = ±12V
VA = ±5V
RL = ∞
18
16
+85°C
30
+25°C
20
–40°C
SWITCHING TIME – ms
ON RESISTANCE – Ω
–5
10
14
12
10
TON
8
6
TOFF
4
2
0
–10
0
–5
5
ANALOG INPUT VOLTAGE – Volts
0
–40
10
Figure 12. ON Resistance vs. Analog Voltage
20
40
TEMPERATURE – °C
60
80
100
1.0
TA = 25°C
VS = ±12V
RL = ∞
80
70
0.8
60
50
40
VIL = 0.8V
30
20
10
VIH = 2.4V
0.2
0
–0.2
I SY–
–0.4
IGND
–0.6
–10
–0.8
–1.0
–40
–20
–10
–5
0
5
ANALOG INPUT VOLTAGE – Volts
10
15
VS = ±12V
VA = GND
VINH = 2.4V
0.4
0
–15
I SY+
0.6
SUPPLY CURRENT – mA
SWITCH LEAKAGE CURRENT – mA
0
Figure 15. Switching Time vs. Temperature
90
–20
0
20
40
60
80
TEMPERATURE – °C
Figure 16. Supply Current vs. Temperature
Figure 13. Overvoltage Characteristics
REV. B
–20
–5–
100
SSM2404
10V
100
5V
90
0
5V
10
0%
0
ANALOG
OUTPUT
VA (OUT)
SSM2404 can also be configured as a 4:1 multiplexer, or by
using additional packages, as 8:1 or 16:1 and up. The breakbefore-make feature is guaranteed from part to part allowing
such multiple-package applications.
LOGIC
INPUT
VINL/INH
As Figure 20 shows, the SSM2404 is easy to use, and no additional devices are needed. The load resistors are recommended
for improved OFF-isolation and charge injection. The ON
resistance of the switch is only 28 Ω typically, which causes very
little signal attenuation even with a load resistor.
5ms/div
IN1
Figure 17. tON/tOFF Switching Response
1
2
RL
IN4
SW4 19
RL
18
3
OUT1
DGND
SW1 CONTROL
OUT4
17
+12V
16
SW4 CONTROL
6
15
SW3 CONTROL
7
14
–12V
8
13
4
5
TOP VIEW
(Not to Scale)
SSM2404
100
90
SW2 CONTROL
CLOSED
(SWITCH ON)
OUT2
RL
OUT3
RL
9
OPEN
(SWITCH OFF)
20
SW1
SW2
SW3
12
10
IN2
0%
50mV
50µs
10
11
R L IS OPTIONAL
Figure 18. Switch OFF-to-ON Transition (RL = 5 kΩ)
IN3
SW
SWITCH
CONTROL STATE
0
1
OFF
ON
Figure 20. Basic Circuit Configuration
OPTIMIZING PERFORMANCE
100
90
CLOSED
(SWITCH ON)
OPEN
(SWITCH OFF)
10
0%
50mV
As the performance curves show, the switch is optimized for
high impedance loads. The distortion performance is at its best
when the switch has a load impedance of 100 kΩ or greater as
shown in Figure 1. However, even at lower values of load resistances, the 1 kHz distortion performance is still excellent,
0.006% for a 10 kΩ load. The main trade-off with THD is
OFF-isolation and crosstalk. This is shown in Figures 10 and
11, again with two different load conditions. As these graphs
show, the 10 kΩ load yields approximately a 16 dB improvement in both characteristics.
50µs
Figure 19. Switch ON-to-OFF Transition (RL = 5 kΩ)
APPLICATIONS INFORMATION
The SSM2404 integrates four analog CMOS switches with
guaranteed “break-before-make” operation to provide high
quality audio switching. Each switch has complementary
N-channel and P-channel MOSFETs to allow the analog input
voltage range to include the positive and negative rails and
improve linearity. In addition, the topology permits fully
bilateral switching. When using the SSM2404 there is full
flexibility in configuring the switches. For example, they can be
used individually as shown in Figure 20, or as a double-pole,
double-throw (DPDT) switch, which is explained later. The
Thus, the optimum operating point depends on the most critical parameters. When THD is critical then high load impedances should be used; however, when crosstalk and OFFisolation are critical, lower impedances on the order of 10 kΩ
should be used. An additional benefit of using the smaller
load resistor is that any charge injected onto the output will be
shunted to ground through the resistor. If improved OFFisolation is needed, the SSM2404 dual audio switch should be
considered with its excellent 120 dB OFF-isolation at 20 kHz.
It is important that all of the AGND pins be connected to the
system analog ground. These pins isolate the input and output
of each switch. Without connecting these pins, the OFFisolation will degrade significantly.
–6–
REV. B
SSM2404
voltages of N4 and P4 are changing, the ON resistance of each
switch is ramping from its OFF state to 28 Ω and vice versa.
The actual rise and fall times are shown in Figures 18 and 19
for a 5 kΩ load. These times are significantly slower than
typical switches, minimizing the SSM2404’s charge injection
and giving it “clickless” performance.
DETAILED SWITCH OPERATION
A simplified circuit schematic with the functional sections is
shown in Figure 21. The TTL interface has an internally
regulated 5 V to ensure TTL logic levels regardless of the supply
voltage. The logic threshold is with respect to the DGND pin,
which can be offset. For example, if DGND is connected to the
negative supply, then the SSM2404 will operate with negative
rail logic. The interface shifts the control logic down to the
negative supply and inverts it to drive N1.
DOUBLE-POLE DOUBLE-THROW SWITCH
The SSM2404 is ideal as a one-chip solution for a stereo
switch. The schematic in Figure 22 shows the typical configuration. This circuit will select one of two stereo sources, channel
A or B. The switch controls for the left and right input of each
channel are tied together so that both will be turned on or off
simultaneously. An inverter is inserted between the channel A
and B controls so that only one logic signal is needed. The outputs can be configured many different ways, such as an inverting or noninverting amplifier stage, and the 10 kΩ load resistors
are added to improve the OFF-isolation. The performance of
this stereo switch is equivalent to each individual switch, yielding a high quality audio switch that is virtually transparent to
the signal.
V+
100nA
100nA
P1
SW1 A
BIAS
P2
P3
C1
15pF
SW
CONTROL
DGND
–1
C2
15pF
TTL
INTERFACE
N1
N2
N4
P4
–1
V+
SW1 B
N3
17
V–
BREAK-BEFORE-MAKE
SSM2404
RAMP GENERATOR
10
8
SW2
L INA
Figure 21. Simplified Schematic
1
N1 in combination with C1 and the 100 nA current source
provides the break-before-make operation of the switch. When
the switch is on, N1 is off and C1 is charged up to the positive
rail. However, when the SW CONTROL is turned off, then the
gate of N1 is pulled high. This turns N1 on, providing a low
impedance path to quickly discharge C1 to the negative rail,
which quickly “breaks” the switch. On the other hand, when the
SW CONTROL goes high again, the gate of N1 is pulled low,
turning it off. This leaves C1 to be slowly charged up to the
positive rail by the 100 nA current source. The difference in the
discharge and charging times ensures break-before-make
operation, even from device to device.
3
SW1
L INB
6
SWA/SWB
15
4
5
16
SW2 CONTROL
AGND
SW3 CONTROL
12
DGND
19
SW1 CONTROL
SW4 CONTROL
13
SW3
20
R INB
2
9
11
R INA
L OUT
10kΩ
SWA/SWB
CHANNEL
SELECTED
0
1
B
A
18
SW4
R OUT
10kΩ
14
The voltage on C1 is inverted by P1 to drive the ramp generator
differential pair, consisting of P2, P3 and N2, N3. This differential pair steers the 100 nA of tail current to either charge or
discharge C2. As discussed above, when the switch is on, C1 is
charged up to the positive rail. P1 inverts this, putting a low
voltage equivalent to the negative supply on the gate of P2. The
BIAS voltage is approximately equal to the midpoint of the two
supply voltages. Thus, when P2 is pulled down, it is turned on
and P3 is off. All of the 100 nA flows through N2 and is mirrored by N3. Thus, the 100 nA discharges C2 through N3.
When C2 is pulled low, the inverter turns N4 on by pulling its
gate high, and the second inverter turns P4 on. To turn the
switch off the gate of P2 is pulled above the BIAS so that all
100 nA charges C2 through P3. This is then inverted to turn off
N4 and P4.
V–
Figure 22. Double-Pole, Double-Throw Stereo Switch
VIRTUAL GROUND SWITCHING
The SSM2404 was built on a CMOS process with a 24 V
operating limit for the total supply voltage across the part. This
leads to a corresponding limit on the analog voltage range. However, to achieve larger signal swings, the SSM2404 should be
configured in the virtual ground mode. As shown in Figure 23,
the output of the SSM2404 is connected to the inverting input
of an amplifier. Since the noninverting input is grounded, the
SSM2404 will also be biased at ground, and large voltage
swings on the circuit’s input will not significantly change the
voltage on the switch. The only limitation is that the current
through the switch needs to be less than ±10 mA, and the voltage
range is limited only by the op amp and its supply voltages.
The internal ramp has rise and fall times on the order of a few
milliseconds which is sped up by the inverters. As the gate
REV. B
–7–
SSM2404
The circuit was tested with an SSM2131 high slew rate audio
amplifier and the results are shown in Figures 24 and 25. This
configuration yields excellent THD performance that is
primarily determined by the amplifier. Also, the headroom is
now +24 dBu (0 dBu = 0.775 V rms), which is due to the
amplifier’s output voltage swing. Thus, even though the
SSM2404 has a ± 12 V limitation on its supplies, it can be used
in systems with much higher voltage ranges. For example, the
double-pole double-throw switch from Figure 22 can be
reconfigured in the virtual ground mode to allow higher voltage
swings, as shown in Figure 26. This application realizes the
excellent performance of Figures 24 and 25 while providing a
low cost switching solution.
V+
17
SSM2404
5k Ω
LINB
1
AUDIO
IN
1
SW1 A
SW1 B
3
LOUT
SW1
6
SWA/SWB
15
4
5
5k Ω
R2
5kΩ
SSM2404
R1
5kΩ
5k Ω
SW2
16
+12V
8
10
RINA
SSM2131
SW2 CONTROL
2
AGND
SW3 CONTROL
9
DGND
12
SW1 CONTROL
19
SW4 CONTROL
13
11
SW3
5k Ω
+18V
5k Ω
3
RINB
SSM2131
1N914
C1626–20–1/92
5k Ω
LINA
18
20
ROUT
SW4
AUDIO
OUT
14
SSM2131
V–
–12V
–18V
Figure 26. Double-Pole, Double-Throw Stereo Switch
Using Virtual Ground Operation
Figure 23. Virtual Ground Switching
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP (P Suffix)
11
20
0.280 (7.11)
0.240 (6.10)
PIN 1
1
10
1.060 (26.90)
0.925 (23.50)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
Figure 24. Virtual Ground Switch THD+N vs. Frequency
(VS = ± 12 V, VA = 2 V rms, with 80 kHz Filter)
0.150
(3.81)
MIN
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
SOIC (S Suffix)
20
PRINTED IN U.S.A.
0.5118 (13.00)
0.4961 (12.60)
11
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4193 (10.65)
0.3937 (10.00)
1
10
0.0500 (1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
Figure 25. Virtual Ground Switch Headroom (VS = ± 12 V
for SSM2404; VS = ± 18 V for Op Amp, f = 1 kHz, with
80 kHz Filter)
–8–
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0125 (0.32)
0.0091 (0.23)
0.0291 (0.74)
X 45°
0.0098 (0.25)
0°- 8°
0.0500 (1.27)
0.0157 (0.40)
REV. B