a FEATURES Wide Bandwidth: 15 MHz Low Offset Voltage: 325 V max Low Noise: 9.5 nV/÷Hz @ 1 kHz Single-Supply Operation: +2.7 V to +12 V Rail-to-Rail Output Swing Low TCVOS: 1 V/ⴗC typ High Slew Rate: 13 V/s No Phase Inversion Unity Gain Stable APPLICATIONS Portable Instrumentation Sampling ADC Amplifier Wireless LANs Direct Access Arrangement Office Automation 15 MHz Rail-to-Rail Operational Amplifiers OP162/OP262/OP462 PIN CONFIGURATIONS 8-Lead Narrow-Body SO (S Suffix) NULL –IN A +IN A V– 1 8 OP162 4 5 NULL V+ OUT A NC NC = NO CONNECT 8-Lead TSSOP (RU Suffix) NULL –IN A +IN A V– 8 1 NULL V+ OUT A NC OP162 4 5 NC = NO CONNECT 8-Lead Narrow-Body SO (S Suffix) GENERAL DESCRIPTION The OP162 (single), OP262 (dual), OP462 (quad) rail-to-rail 15 MHz amplifiers feature the extra speed new designs require, with the benefits of precision and low power operation. With their incredibly low offset voltage of 45 mV (typ) and low noise, they are perfectly suited for precision filter applications and instrumentation. The low supply current of 500 mA (typ) is critical for portable or densely packed designs. In addition, the rail-to-rail output swing provides greater dynamic range and control than standard video amplifiers provide. These products operate from single supplies as low as +2.7 V to dual supplies of ± 6 V. The fast settling times and wide output swings recommend them for buffers to sampling A/D converters. The output drive of 30 mA (sink and source) is needed for many audio and display applications; more output current can be supplied for limited durations. The OP162 family is specified over the extended industrial temperature range (–40∞C to +125∞C). The single OP162 and dual OP262 are available in 8-lead SOIC and TSSOP packages. The quad OP462 is available in 14-lead narrow-body SOIC and TSSOP packages. OUT A –IN A +IN A V– 1 8 OP262 4 5 V+ OUT B –IN B +IN B 8-Lead TSSOP (RU Suffix) OUT A –IN A +IN A V– 8 1 OP262 4 5 V+ OUT B –IN B +IN B 14-Lead Narrow-Body SO (S Suffix) OUT A –IN A +IN A V+ +IN B –IN B 1 OUT B 7 14 OUT D –IN D +IN D V– +IN C OP462 8 –IN C OUT C 14-Lead TSSOP (RU Suffix) OUT A –IN A +IN A V+ +IN B –IN B OUT B 1 14 OP462 7 8 OUT D –IN D +IN D V– +IN C –IN C OUT C REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 OP162/OP262/OP462–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = +5.0 V, V S CM = 0 V, TA = +25ⴗC, unless otherwise noted) Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS OP162G, OP262G, OP462G, –40∞C £ TA £ +125∞C H Grade, –40∞C £ TA £ +125∞C D Grade, –40∞C £ TA £ +125∞C Input Bias Current IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection VCM CMRR Large Signal Voltage Gain AVO Long-Term Offset Voltage Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing High VOS DVOS/DT DIB/DT VOH Output Voltage Swing Low VOL Short Circuit Current Maximum Output Current ISC IOUT POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier PSRR ISY Min 0 V £ VCM £ +4.0 V, –40∞C £ TA £ +125∞C RL = 2 kW, 0.5 £ VOUT £ 4.5 V RL = 10 kW, 0.5 £ VOUT £ 4.5 V RL = 10 kW, –40∞C £ TA £ +125∞C G Grade1 Note 2 IL = 250 mA, –40∞C £ TA £ +125∞C IL = 5 mA IL = 250 mA, –40∞C £ TA £ +125∞C IL = 5 mA Short to Ground VS = +2.7 V to +7 V –40∞C £ TA £ +125∞C OP162, VOUT = 2.5 V –40∞C £ TA £ +125∞C OP262, OP462, VOUT = 2.5 V –40∞C £ TA £ +125∞C Max Units 45 325 800 1 3 5 600 650 ± 25 ± 40 +4 mV mV mV mV mV nA nA nA nA V 0.8 360 –40∞C £ TA £ +125∞C –40∞C £ TA £ +125∞C Typ ± 2.5 0 70 65 40 110 30 88 1 250 dB V/mV V/mV V/mV mV mV/∞C pA/∞C 4.99 4.94 14 65 ± 80 ± 30 V V mV mV mA mA 600 4.95 4.85 50 150 120 90 600 500 750 1 700 850 dB dB mA mA mA mA DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin SR tS GBP fm 1 V < VOUT < 4 V, RL = 10 kW To 0.1%, AV = –1, VO = 2 V Step 10 540 15 61 V/ms ns MHz Degrees NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 0.5 9.5 0.4 mV p-p nV/÷Hz pA/÷Hz NOTES 1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 ∞C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the –40∞C to +25∞C delta and the +25∞C to +125∞C delta. Specifications subj]ect to change without notice. –2– REV. D OP162/OP262/OP462–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = +3.0 V, V S CM = 0 V, TA = +25ⴗC, unless otherwise noted) Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS OP162G, OP262G, OP462G H Grade, –40∞C £ TA £ +125∞C D Grade, –40∞C £ TA £ +125∞C Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection IB IOS VCM CMRR Large Signal Voltage Gain AVO Long-Term Offset Voltage VOS OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier VOH VOL PSRR ISY OP162/OP262/OP462 0 V £ VCM £ +2.0 V, –40∞C £ TA £ +125∞C RL = 2 kW, 0.5 V £ VOUT £ 2.5 V RL = 10 kW, 0.5 V £ VOUT £ 2.5 V G Grade1 IL = 250 mA IL = 5 mA IL = 250 mA IL = 5 mA VS = +2.7 V to +7 V, –40∞C £ TA £ +125∞C OP162, VOUT = 1.5 V –40∞C £ TA £ +125∞C OP262, OP462, VOUT = 1.5 V –40∞C £ TA £ +125∞C Min Typ Max Units 50 325 1 3 5 600 ± 25 +2 mV mV mV mV nA nA V 600 dB V/mV V/mV mV 50 150 V V mV mV 700 1 650 850 dB mA mA mA mA 0.8 0 70 20 2.95 2.85 60 360 ± 2.5 110 20 30 2.99 2.93 14 66 110 600 500 DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin SR tS GBP fm RL = 10 kW To 0.1%, AV = –1, VO = 2 V Step 10 575 15 59 V/ms ns MHz Degrees NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 0.5 9.5 0.4 mV p-p nV/÷Hz pA/÷Hz NOTES 1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 ∞C, with an LTPD of 1.3. Specifications subject to change without notice. REV. D –3– OP162/OP262/OP462–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = ⴞ5.0 V, V S CM = 0 V, TA = +25ⴗC, unless otherwise noted) Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage VOS OP162G, OP262G, OP462G –40∞C £ TA £ +125∞C H Grade, –40∞C £ TA £ +125∞C D Grade, –40∞C £ TA £ +125∞C Input Bias Current IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection VCM CMRR Large Signal Voltage Gain AVO Long-Term Offset Voltage Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing High VOS DVOS/DT DIB/DT VOH Output Voltage Swing Low VOL Short Circuit Current Maximum Output Current ISC IOUT POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier Supply Voltage Range PSRR ISY VS Min –4.9 V £ VCM £ +4.0 V, –40∞C £ TA £ +125∞C RL = 2 kW, –4.5 V £ VOUT £ 4.5 V RL = 10 kW, –4.5 V £ VOUT £ 4.5 V –40∞C £ TA £ +125∞C G Grade1 Note 2 IL = 250 mA, –40∞C £ TA £ +125∞C IL = 5 mA IL = 250 mA, –40∞C £ TA £ +125∞C IL = 5 mA Short to Ground VS = ± 1.35 V to ± 6 V, –40∞C £ TA £ +125∞C OP162, VOUT = 0 V –40∞C £ TA £ +125∞C OP262, OP462, VOUT = 0 V –40∞C £ TA £ +125∞C Max Units 25 325 800 1 3 5 500 650 ± 25 ± 40 +4 mV mV mV mV mV nA nA nA nA V 0.8 260 –40∞C £ TA £ +125∞C –40∞C £ TA £ +125∞C Typ ± 2.5 –5 70 75 25 110 35 120 1 250 dB V/mV V/mV V/mV mV mV/∞C pA/∞C 4.99 4.94 –4.99 –4.94 ± 80 ± 30 V V V V mA mA 600 4.95 4.85 60 110 650 550 +3.0 (± 1.5) –4.95 –4.85 800 1.15 775 1 +12 (± 6) dB mA mA mA mA V DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin SR tS GBP fm –4 V < VOUT < 4 V, RL = 10 kW To 0.1%, AV = –1, VO = 2 V Step 13 475 15 64 V/ms ns MHz Degrees NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 0.5 9.5 0.4 mV p-p nV/÷Hz pA/÷Hz NOTES 1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 ∞C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the –40∞C to +25∞C delta and the +25∞C to +125∞C delta. Specifications subject to change without notice. –4– REV. D OP162/OP262/OP462 ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . ± 0.6 V Internal Power Dissipation SOIC (S) . . . . . . . . . . . . . . . . . . . Observe Derating Curves TSSOP (RU) . . . . . . . . . . . . . . . . Observe Derating Curves Output Short-Circuit Duration . . . . Observe Derating Curves Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C Junction Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300∞C Package Type JA3 JC Units 8-Lead SOIC (S) 8-Lead TSSOP (RU) 14-Lead SOIC (S) 14-Lead TSSOP (RU) 158 240 120 180 43 43 36 35 ∞C/W ∞C/W ∞C/W ∞C/W Model Temperature Range Package Description Package Option OP162GS OP162DRU OP162HRU OP262DRU OP262GS OP262HRU OP462DRU OP462DS OP462GS OP462HRU –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C 8-Lead SOIC 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead SOIC 8-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC 14-Lead SOIC 14-Lead TSSOP RN-8 RU-8 RU-8 RU-8 RN-8 RU-8 RU-14 RN-14 RN-14 RU-14 NOTES 1 For supply voltages greater than 6 volts, the input voltage is limited to less than or equal to the supply voltage. 2 For differential input voltages greater than 0.6 volts the input current should be limited to less than 5 mA to prevent degradation or destruction of the input devices. 3 qJA is specified for the worst case conditions, i.e., qJA is specified for device soldered in circuit board for SOIC and TSSOP packages. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP162/OP262/OP462 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, p roper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. D –5– WARNING! ESD SENSITIVE DEVICE OP162/OP262/OP462–Typical Performance Characteristics VS = 5V TA = 25ⴗC TA = 25ⴗC 80 COUNT = 720 OP AMPS 150 100 50 20 0.2 180 50 25 Figure 4. OP462 Input Offset Voltage vs. Temperature –100 –200 –300 –400 –500 –50 0 25 50 75 100 125 150 TEMPERATURE – ⴗC –25 0 4.94 IOUT = 5mA 4.88 5 0.080 IOUT = 5mA 0.060 0.040 0.020 RL = 10k⍀ 80 VS = 5V 60 40 RL = 2k⍀ 20 RL = 600⍀ IOUT = 250A 4.82 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 7. OP462 Output High Voltage vs. Temperature 0.000 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 6. OP462 Input Offset Current vs. Temperature VS = 5V OUTPUT LOW VOLTAGE – mV IOUT = 250A 10 100 0.100 VS = 5V 5.06 VS = 5V 0 –75 –50 –25 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 5. OP462 Input Bias Current vs. Temperature 5.12 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMMON-MODE VOLTAGE – Volts 15 VS = 5V INPUT OFFSET CURRENT – nA 75 0 Figure 3. OP462 Input Bias Current vs. Common-Mode Voltage OPEN-LOOP GAIN – V/mV 100 5.00 260 100 0.3 0.5 0.7 0.9 1.1 1.3 1.5 INPUT OFFSET DRIFT, TCVOS – V/ⴗC VS = 5V 0 –75 –50 –25 340 0 INPUT BIAS CURRENT – nA INPUT OFFSET VOLTAGE – V 40 Figure 2. OP462 Input Offset Voltage Drift (TCVOS) 125 OUTPUT HIGH VOLTAGE – Volts 60 0 0 –200 –140 –80 –20 40 100 160 INPUT OFFSET VOLTAGE – V Figure 1. OP462 Input Offset Voltage Distribution COUNT = 360 OP AMPS VS = 5V INPUT BIAS CURRENT – nA VS = 5V QUANTITY – Amplifiers QUANTITY – Amplifiers 200 420 100 250 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 8. OP462 Output Low Voltage vs. Temperature –6– 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 9. OP462 Open-Loop Gain vs. Temperature REV. D OP162/OP262/OP462 1.0 100 60 VS = 10V VS = 3V 40 20 0.7 0.8 SUPPLY CURRENT – mA 80 SUPPLY CURRENT – mA OUTPUT VOLTAGE – mV 0.9 VS = 10V 0.7 VS = 5V 0.6 VS = 3V 0.5 0.4 0.3 0.2 0 1 2 3 4 5 6 LOAD CURRENT – mA 0 –75 –50 –25 7 Figure 10. Output Low Voltage to Supply Rail vs. Load Current VS = 5V 20 PHASE 90 10 135 0 180 –10 225 –20 270 –30 100k 10M 1M FREQUENCY – Hz PHASE SHIFT – dB 45 100M Figure 13. Open-Loop Gain and Phase vs. Frequency (No Load) CLOSED-LOOP GAIN – dB TA = 25ⴗC TA = +25ⴗC 40 RL = 830⍀ CL ≤ 5pF 20 0 –20 –40 10k 100k 1M 10M FREQUENCY – Hz 1 0 –1 –2 0.1% 0.01% 0 200 400 600 800 SETTLING TIME – ns 1000 Figure 16. Settling Time vs. Step Size REV. D 30 TA = 25ⴗC VIN = ⴞ50mV RL = 10k⍀ +OS –OS 20 10 –3 –4 40 NOISE DENSITY – nV/ Hz VS = 5V TA = 25ⴗC OVERSHOOT – % STEP SIZE – Volts 2 0 10 AVCL = 1 RL = 10k⍀ CL = 15pF 1 TA = 25°C DISTORTION < 1% 1M 100k FREQUENCY – Hz 10M VS = 5V 60 50 0.01% VS = 5V 2 70 60 0.1% 3 Figure 15. Maximum Output Swing vs. Frequency 3 VS = 5V 12 4 0 10k 100M Figure 14. Closed-Loop Gain vs. Frequency 4 4 6 8 10 SUPPLY VOLTAGE – Volts Figure 12. OP462 Supply Current/ Amplifier vs. Supply Voltage MAXIMUM OUTPUT SWING – V p-p GAIN 2 5 VS = 5V 30 GAIN – dB 0 60 40 0.5 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 11. Supply Current/Amplifier vs. Temperature 50 0.6 0.4 0.1 0 TA = 25ⴗC TA = 25ⴗC 50 40 30 20 10 0 100 CAPACITANCE – pF 1000 Figure 17. Small-Signal Overshoot vs. Capacitance –7– 1 10 100 FREQUENCY – Hz 1k Figure 18. Voltage Noise Density vs. Frequency OP162/OP262/OP462 300 VS = 5V TA = 25ⴗC OUTPUT IMPEDANCE – ⍀ NOISE DENSITY – pA/ Hz 6 5 4 3 2 90 VS = 5V 250 200 150 AVCL = 10 10 100 FREQUENCY – Hz 50 40 AVCL = 1 30 0 100k 1k Figure 19. Current Noise Density vs. Frequency 60 100 0 1 TA = 25ⴗC 70 50 1 VS = 5V 80 TA = 25ⴗC CMRR – dB 7 1M FREQUENCY – Hz 10M Figure 20. Output Impedance vs. Frequency 20 1k 10k 100k 1M FREQUENCY – Hz 10M Figure 21. CMRR vs. Frequency 90 VS = 5V 80 20mV TA = 25ⴗC PSRR – dB 70 2V 2s 90 VIN = 12V p-p VS = ⴞ5V 100 90 100 AV = 1 60 +PSRR –PSRR 50 10 40 VS = 5V AV = 100k⍀ en = 0.5V p-p 0% 30 20 1k 10k 100k 1M FREQUENCY – Hz 10 0% 2V 20s 10M Figure 22. PSRR vs. Frequency Figure 23. 0.1 Hz to 10 Hz Noise Figure 24. No Phase Reversal; [VIN = 12 V p-p, VS = ± 5 V, AV = 1] VS = 5V VS = 5V 100 AV = 1 90 100 90 TA = 25ⴗC AV = 1 TA = 25ⴗC CL = 100pF CL = 100pF 10 10 0% 0% 20mV 200ns Figure 25. Small Signal Transient Response 100s 500mV Figure 26. Large Signal Transient Response –8– REV. D OP162/OP262/OP462 VCC. It is important to avoid accidentally connecting the wiper to VEE, as this will damage the device. The recommended value for the potentiometer is 20 kW. APPLICATIONS SECTION Functional Description The OPx62 family is fabricated using Analog Devices’ high speed complementary bipolar process, also called XFCB. The process includes trench isolating each transistor to lower parasitic capacitances thereby allowing high speed performance. This high speed process has been implemented without trading off the excellent transistor matching and overall dc performance characteristic of Analog Devices’ complementary bipolar process. This makes the OPx62 family an excellent choice as an extremely fast and accurate low voltage op amp. +5V 20k⍀ 1 8 3 7 OP162 2 Figure 27 shows a simplified equivalent schematic for the OP162. A PNP differential pair is used at the input of the device. The cross connecting of the emitters is used to lower the transconductance of the input stage, which improves the slew rate of the device. Lowering the transconductance through cross connecting the emitters has another advantage in that it provides a lower noise factor than if emitter degeneration resistors were used. The input stage can function with the base voltages taken all the way to the negative power supply, or up to within 1 V of the positive power supply. 6 –5V Figure 28. Schematic Showing Offset Adjustment Rail-to-Rail Output The OP162/OP262/OP462 has a wide output voltage range that extends to within 60 mV of each supply rail with a load current of 5 mA. Decreasing the load current will extend the output voltage range even closer to the supply rails. The commonmode input range extends from ground to within 1 V of the positive supply. It is recommended that there be some minimal amount of gain when a rail-to-rail output swing is desired. The minimum gain required is based on the supply voltage and can be found as: VCC AV, min = VS VS – 1 where VS is the positive supply voltage. With a single supply voltage of +5 V, the minimum gain to achieve rail-to-rail output should be 1.25. +IN VOUT –IN VOS 4 Output Short-Circuit Protection To achieve a wide bandwidth and high slew rate, the output of the OP162/OP262/OP462 is not short-circuit protected. Shorting the output directly to ground or to a supply rail may destroy the device. The typical maximum safe output current is ±30 mA. Steps should be taken to ensure the output of the device will not be forced to source or sink more than 30 mA. VEE Figure 27. Simplified Schematic Two complementary transistors in a common-emitter configuration are used for the output stage. This allows the output of the device to swing to within 50 mV of either supply rail at load currents less than 1 mA. As load current increases, the maximum voltage swing of the output will decrease. This is due to the collector-to-emitter saturation voltages of the output transistors increasing. The gain of the output stage, and consequently the open-loop gain of the amplifier, is dependent on the load resistance connected at the output. And because the dominant pole frequency is inversely proportional to the open-loop gain, the unity-gain bandwidth of the device is not affected by the load resistance. This is typically the case in rail-to-rail output devices. For single +5 V supply applications, resistors less than 169 W are not recommended. +5V VIN 169⍀ OPx62 Offset Adjustment Because the OP162/OP262/OP462 has such an exceptionally low typical offset voltage, adjustment to correct offset voltage may not be needed. However, the OP162 does have pinouts where a nulling resistor can be attached. Figure 28 shows how the OP162 offset voltage can be adjusted by connecting a potentiometer between Pins 1 and 8, and connecting the wiper to REV. D In applications where some output current protection is needed, but not at the expense of reduced output voltage headroom, a low value resistor in series with the output can be used. This is shown in Figure 29. The resistor is connected within the feedback loop of the amplifier so that if VOUT is shorted to ground and VIN swings up to +5 V, the output current will not exceed 30 mA. –9– VOUT Figure 29. Output Short-Circuit Protection OP162/OP262/OP462 The input voltage should be limited to ± 6 V or damage to the device can occur. Electrostatic protection diodes placed in the input stage of the device help protect the amplifier from static discharge. Diodes are connected between each input as well as from each input to both supply pins as shown in the simplified equivalent circuit in Figure 27. If an input voltage exceeds either supply voltage by more than 0.6 V, or if the differential input voltage is greater than 0.6 V, these diodes begin to energize and overvoltage damage could occur. The input current should be limited to less than 5 mA to prevent degradation or destruction of the device. Figures 30 and 31 provide a convenient way to see if the device is being overheated. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature around the package. By using the previous equation, it is a simple matter to see if PDISS exceeds the device’s power derating curve. To ensure proper operation, it is important to observe the recommended derating curves shown in Figures 30 and 31. 2.0 MAXIMUM POWER DISSIPATION – Watts Input Overvoltage Protection This can be done by placing an external resistor in series with the input that could be overdriven. The size of the resistor can be calculated by dividing the maximum input voltage by 5 mA. For example, if the differential input voltage could reach 5 V, the external resistor should be 5 V/5 mA = 1 kW. In practice, this resistance should be placed in series with both inputs to balance any offset voltages created by the input bias current. Output Phase Reversal qJA = OPx62 package thermal resistance, junction-toambient; and TA = Ambient temperature of the circuit. The power dissipated by the device can be calculated as: PDISS = ILOAD ¥ (VS – VOUT) where: ILOAD is the OPx62 output load current; VS is the OPx62 supply voltage; and VOUT is the OPx62 output voltage. –20 0 20 40 60 80 100 AMBIENT TEMPERATURE – ⴗC 120 1.5 14-PIN SOIC PACKAGE 1.0 0.5 0 –40 To calculate the internal junction temperature of the OPx62, the following formula can be used: PDISS = OPx62 power dissipation; 8-PIN TSSOP PACKAGE 2.0 The maximum power that can be safely dissipated by the OP162/OP262/OP462 is limited by the associated rise in junction temperature. The maximum safe junction temperature is 150∞C, and should not be exceeded or device performance could suffer. If this maximum is momentarily exceeded, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the device in an “overheated” condition for an extended period can result in permanent damage to the device. where: TJ = OPx62 junction temperature; 0.5 8-PIN SOIC PACKAGE Figure 30. Maximum Power Dissipation vs. Temperature for 8-Pin Package Types Power Dissipation TJ = PDISS ¥ qJA + TA 1.0 0 –40 MAXIMUM POWER DISSIPATION – Watts The OP162/OP262/OP462 is immune to phase reversal as long as the input voltage is limited to ± 6 V. Figure 24 shows a photo of the output of the device with the input voltage driven beyond the supply voltages. Although the device’s output will not change phase, large currents due to input overvoltage could result, damaging the device. In applications where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used, as described in the previous section. 1.5 14-PIN TSSOP PACKAGE –20 0 20 40 60 80 100 AMBIENT TEMPERATURE – ⴗC 120 Figure 31. Maximum Power Dissipation vs. Temperature for 14-Pin Package Types Unused Amplifiers It is recommended that any unused amplifiers in a dual or a quad package be configured as a unity gain follower with a 1 kW feedback resistor connected from the inverting input to the output and the noninverting input tied to the ground plane. Power On Settling Time The time it takes for the output of an op amp to settle after a supply voltage is delivered can be an important consideration in some power-up sensitive applications. An example of this would be in an A/D converter where the time until valid data can be produced after power-up is important. The OPx62 family has a rapid settling time after power-up. Figure 32 shows the OP462 output settling times for a single supply voltage of VS = +5 V. The test circuit in Figure 33 was used to find the power on settling times for the device. –10– REV. D OP162/OP262/OP462 2V 500ns 100 100 90 90 VS = 5V AV = 1 CL = 300pF RL = 10k⍀ WITH SNUBBER: RX = 140⍀ CX = 10nF VS = 5V AV = 1 10 0% 10 RL = 10k⍀ 0% 50mV Figure 32. Oscilloscope Photo of VS and VOUT Figure 36. A Photo of a Nice Square Wave at the Output The network operates in parallel with the load capacitor, CL, and provides compensation for the added phase lag. The actual values of the network resistor and capacitor are determined empirically to minimize overshoot while maximizing unity-gain bandwidth. Table I shows a few sample snubber networks for large load capacitors: +1 + 0 TO +5V SQUARE 1s 50mV – VOUT OP462 10k⍀ Table I. Snubber Networks for Large Capacitive Loads Figure 33. Test Circuit for Power On Settling Time Capacitive Load Drive The OP162/OP262/OP462 is a high speed, extremely accurate device and can tolerate some capacitive loading at its output. As load capacitance increases, however, the unity-gain bandwidth of the device will decrease. There will also be an increase in overshoot and settling time for the output. Figure 35 shows an example of this with the device configured for unity gain and driving a 10 kW resistor and 300 pF capacitor placed in parallel. CLOAD RX CX <300 pF 500 pF 1 nF 10 nF 140 W 100 W 80 W 10 W 10 nF 10 nF 10 nF 47 nF Obviously, higher load capacitance will also reduce the unitygain bandwidth of the device. Figure 37 shows a plot of unitygain bandwidth versus capacitive load. The snubber network will not provide any increase in bandwidth, but it will substantially reduce ringing and overshoot, as shown in the difference between Figures 35 and 36. By connecting a series R-C network, commonly called a “snubber” network, from the output of the device to ground, this ringing can be eliminated and overshoot can be significantly reduced. Figure 34 shows how to set up the snubber network, and Figure 36 shows the improvement in output response with the network added. 10 9 8 VOUT OPx62 VIN BANDWIDTH – MHz +5V RX CL CX 7 6 5 4 3 2 Figure 34. Snubber Network Compensation for Capacitive Loads 1 0 10pF 90 The OPx62 device family offers low total harmonic distortion. This makes it an excellent device choice for audio applications. Figure 38 shows a graph of THD plus noise figures at 0.001% for the OP462. Figure 39 shows a graph of the worst case crosstalk between two amplifiers in the OP462 device. A 1 V rms signal is applied to one amplifier while measuring the output of an adjacent amplifier. Both amplifiers are configured for unity gain and supplied with ± 2.5 V. 10 1s Figure 35. A Photo of a Ringing Square Wave REV. D 10nF Total Harmonic Distortion and Crosstalk 0% 50mV 1nF CLOAD Figure 37. Unity Gain Bandwidth vs. CLOAD VS = 5V AV = 1 CL = 300pF RL = 10k⍀ 100 100pF –11– OP162/OP262/OP462 0.010 The audio signal is ac coupled to each noninverting input through a 10 mF capacitor. The gain of the amplifier is controlled by the feedback resistors and is: (R2/R1) + 1. For this example, the gain is 6. By removing R1 altogether, the amplifier would have unity gain. A 169 W resistor is placed at the output in the feedback network to short-circuit protect the output of the device. This would prevent any damage to the device from occurring if the headphone output became shorted. A 270 mF capacitor is used at the output to couple the amplifier to the headphone. This value is much larger than that used for the input because of the low impedance of headphones, which can range from 32 W to 600 W or more. VS = ⴞ2.5V AV = 1 VIN = 1.0V rms RL = 10k⍀ THD+N – % BANDWIDTH: <10Hz TO 22kHz 0.001 0.0001 20 100 1k FREQUENCY – Hz R1 = 10k⍀ 10k 20k 10F Figure 38. THD+N vs. Frequency Graph 10F –60 XTALK – dBV –70 5V LEFT IN –40 –50 R2 = 50k⍀ AV = 1 VIN = 1.0V rms (0dBV) 5V L VOLUME CONTROL OP262-A 270F HEADPHONE LEFT 47k⍀ 10k⍀ 100k⍀ RL = 10k⍀ VS = ⴞ2.5V 169⍀ 100k⍀ 10F –80 5V –90 10k⍀ –100 R VOLUME CONTROL –110 RIGHT IN –120 169⍀ 10F 100 1k FREQUENCY – Hz 10k HEADPHONE RIGHT 47k⍀ R2 = 50k⍀ –130 –140 20 270F OP262-B R1 = 10k⍀ 20k 10F Figure 39. Crosstalk vs. Frequency Graph Figure 40. Headphone Output Amplifier PCB Layout Considerations Because the OP162/OP262/OP462 can provide gain at high frequency, careful attention to board layout and component selection is recommended. As with any high speed application, a good ground plane is essential to achieve the optimum performance. This can significantly reduce the undesirable effects of ground loops and I¥R losses by providing a low impedance reference point. Best results are obtained with a multilayer board design with one layer assigned to ground plane. Chip capacitors should be used for supply bypassing, with one end of the capacitor connected to the ground plane and the other end connected within 1/8 inch of each power pin. An additional large tantalum electrolytic capacitor (4.7 mF–10 mF) should be connected in parallel. This capacitor does not need to be placed as close to the supply pins, as it is to provide current for fast large-signal changes at the device’s output. APPLICATION CIRCUITS Single Supply Stereo Headphone Driver Figure 40 shows a stereo headphone output amplifier that can be run from a single +5 V supply. The reference voltage is derived by dividing the supply voltage down with two 100 kW resistors. A 10 mF capacitor prevents power supply noise from contaminating the audio signal and establishes an ac ground for the volume control potentiometers. Instrumentation Amplifier Because of its high speed, low offset voltages and low noise characteristics, the OP162/OP262/OP462 can be used in a wide variety of high speed applications, including a precision instrumentation amplifier. Figure 41 shows an example of such an application. –VIN OP462-A 1k⍀ OP462-D RG 1k⍀ 2k⍀ 2k⍀ 10k⍀ OP462-C OUTPUT 2k⍀ 1.9k⍀ 10k⍀ OP462-B +VIN 200⍀ 10 TURN (OPTIONAL) Figure 41. A High Speed Instrumentation Amplifier –12– REV. D OP162/OP262/OP462 The differential gain of the circuit is determined by RG, where: ADIFF = 1 + Direct Access Arrangement 2 RG with the RG resistor value in kW. Removing RG will set the circuit gain to unity. The fourth op amp, OP462-D, is optional and is used to improve CMRR by reducing any input capacitance to the amplifier. By shielding the input signal leads and driving the shield with the common-mode voltage, input capacitance is eliminated at common-mode voltages. This voltage is derived from the midpoint of the outputs of OP462-A and OP462-B by using two 10 kW resistors followed by OP462-D as a unity gain buffer. It is important to use 1% or better tolerance components for the 2 kW resistors, as the common-mode rejection is dependent on their ratios being exact. A potentiometer should also be connected in series with the OP462-C noninverting input resistor to ground to optimize common-mode rejection. P1 TX GAIN ADJUST The circuit in Figure 41 was implemented to test its settling time. The instrumentation amp was powered with ± 5 V, so the input step voltage went from –5 V to +4 V to keep the OP462 within its input range. Therefore, the 0.05% settling range is when the output is within 4.5 mV. Figure 42 shows the positive slope settling time to be 1.8 ms, and Figure 43 shows a settling time of 3.9 ms for the negative slope. 5mV Figure 44 shows a schematic for a +5 V single supply transmit/ receive telephone line interface for 600 W transmission systems. It allows full duplex transmission of signals on a transformer coupled 600 W line. Amplifier A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured so as to apply the largest possible differential signal to the transformer. The largest signal available on a single +5 V supply is approximately 4.0 V p-p into a 600 W transmission system. Amplifier A3 is configured as a difference amplifier to extract the receive information from the transmission line for amplification by A4. A3 also prevents the transmit signal from interfering with the receive signal. The gain of A4 can be adjusted in the same manner as A1’s to meet the modem’s input signal requirements. Standard resistor values permit the use of SIP (Single In-line Package) format resistor arrays. Couple this with the OP462 14-lead SOIC or TSSOP package and this circuit can offer a compact solution. TO TELEPHONE LINE 2k⍀ R3 360⍀ 1:1 1 A1 5V DC R6 10k⍀ 6 7 A2 R7 10k⍀ 5 100 90 R9 10k⍀ R10 10k⍀ 2 R11 10k⍀ 0% 1s A1, A2 = 1/2 AD8532 A3, A4 = 1/2 AD8532 Figure 42. Positive Slope Settling Time 5mV 3 R12 10k⍀ A3 1 R13 10k⍀ R14 14.3k⍀ 2k⍀ 6 5 P2 RX GAIN ADJUST A4 7 RECEIVE RXA C2 0.1F Figure 44. A Single-Supply Direct Access Arrangement for Modems 2V 100 90 10 0% 1µs 1 s Figure 43. Negative Slope Settling Time REV. D R8 10k⍀ 10F 10 TRANSMIT TXA 3 6.2V T1 MIDCOM 671-8005 2V C1 R1 10k⍀ 0.1F 2 R5 10k⍀ 6.2V ZO 600⍀ R2 9.09k⍀ –13– OP162/OP262/OP462 Spice Macro-Model * OP162/OP262/OP462 SPICE Macro-model * 7/96, Ver. 1 * Troy Murphy / ADSC * * Copyright 1996 by Analog Devices * * Refer to “README.DOC” file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP162 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14, 20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 (20, 0) 1 G1 98 10 (5, 6) 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz * ECM 13 98 POLY (2) (1, 98) (2, 98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 (10, 98) .588E-6 R4 21 98 1.7E6 R5 21 22 1.7E6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 (21, 98) 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 (24, 98) 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY (1) (99, 50) 277.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY (1) (98, 25) 0.70366 EB2 42 50 POLY (1) (25, 98) 0.73419 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 . MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, .MODEL NOUT NPN (BF=110, IS=1.786E-17, .MODEL DX D() .ENDS –14– 7.5E-6 1 1 VAF=28, KF=3E-7) VAF=90, KF=3E-7) REV. D OP162/OP262/OP462 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) 14-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-14) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.50 (0.0196) ⴛ 45ⴗ 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.33 (0.0130) COPLANARITY SEATING 0.10 PLANE 4.00 (0.1575) 3.80 (0.1496) 6.20 (0.2440) 5.80 (0.2284) 14 8 1 7 1.75 (0.0689) 1.35 (0.0531) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) 8ⴗ 0.25 (0.0098) 0ⴗ 1.27 (0.0500) 0.41 (0.0160) 0.19 (0.0075) 6.20 (0.2441) 5.80 (0.2283) 0.51 (0.0201) 0.33 (0.0130) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0197) ⴛ 45ⴗ 0.25 (0.0098) 8ⴗ 0.25 (0.0098) 0ⴗ 1.27 (0.0500) 0.40 (0.0157) 0.19 (0.0075) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Dimensions shown in millimeters 5.10 5.00 4.90 3.10 3.00 2.90 8 5 14 4.50 4.40 6.40 BSC 4.30 1 4 7 PIN 1 0.65 BSC 1.20 MAX 0.30 COPLANARITY 0.19 0.10 SEATING 0.20 PLANE 0.09 1.05 1.00 0.80 8ⴗ 0ⴗ 0.65 BSC 1.20 MAX 0.15 0.05 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AA REV. D 6.40 BSC 1 PIN 1 0.15 0.05 8 4.50 4.40 4.30 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 8ⴗ 0ⴗ COMPLIANT TO JEDEC STANDARDS MO-153AB-1 –15– 0.75 0.60 0.45 OP162/OP262/OP462 Revision History Location Page PRINTED IN U.S.A. Deleted 8-Lead Plastic DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Deleted 14-Lead Plastic DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to Figure 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to Figure 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C00288–0–10/02(D) 10/02—Data Sheet changed from REV. C to REV. D. –16– REV. D