AD AD8026AR

a
FEATURES
Voltage Feedback, Rail-to-Rail Output
Rated Settling Time to Within 0.5 V of Supply Rail
Quad High Speed Amplifier
Settling Time to 0.1% of 55 ns (4 V Swing, C L = 100 pF)
Slew Rate 135 V/ms (4 V Swing)
–3 dB Bandwidth 60 MHz
Fixed Gain Resistors for High DC Accuracy
Low Voltage Offset 0.5 mV RTO Typical
Gain Error Less than 0.05%
Low Supply Current 3.4 mA
Nominal +12 V Supply
14-Lead SOIC Package
Quad High Speed
Amplifier
AD8026
FUNCTIONAL BLOCK DIAGRAM
OUT A
OUT D
RF
RF
RG
RG
–IN A
RP
+IN A
VCC
+IN B
RP
AD8026
RP
RP
RG
–IN D
+IN D
VEE
+IN C
RG
–IN B
RF
RF
OUT B
–IN C
OUT C
APPLICATIONS
LCD Source Drivers
CD DVD
CDR
PRODUCT DESCRIPTION
The AD8026 is a complete low cost, closed loop, voltage feedback, quad amplifier. Precision trimmed resistors set a fixed RF/
RG ratio of 5/3 to a typical gain accuracy of 0.02%. Manufactured on ADI’s proprietary XFCB high speed bipolar process,
which enables the output drivers to settle to within 0.1% within
55 ns into a 100 pF load (4 V swing) and drive output voltages
to rated settling time to within 0.5 V from the rail. The typical
3 dB bandwidth is 60 MHz, at G = +2.67. The AD8026 is
laser trimmed to produce both exceptional offset and gain
performance.
The low settling time, high slew rate, low offset and rail-to-rail
output voltage drive capability makes the AD8026 ideal for
driving LCD displays.
RL = 10kV
INPUT
1V/DIV
VIN = 1.5V
OUTPUT
1V/DIV
VOUT = 4V
50ns/DIV
Figure 1. 4 V Step Response
The AD8026 is available in a 14-lead SOIC package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
(@ +258C, VS = 66 V, RI = 500 V, RL = 10 kV, RF = 5K, R G = 3K Noninverting
MIN = 08C, TMAX = +708C, unless otherwise noted.)
AD8026–SPECIFICATIONS Configuration, T
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Voltage Noise (RTO)1
Crosstalk, Output to Output
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
RTO Offset Voltage2
RTO Offset Drift
+Input Bias Current
Closed-Loop Gain Error3
Gain Matching
Conditions
VIN = 50 mV rms
RL = 1 kΩ
VIN = 50 mV rms
RL = 1 kΩ
VO = 4 V Step
VO = 2 V p-p
VO = 4 V Step, CL = 100 pF,
RS = 50 Ω
Min
Typ
20
60
MHz
12
135
10
MHz
V/µs
MHz
55
ns
–60
67
dBc
nV/√Hz
–80
0.02
0.02
dB
%
Degrees
fC = 5 MHz, VO = 2 V p-p,
RL = 1 kΩ
f = 10 kHz
f = 5 MHz, VO = 2 V p-p,
RL = 1 kΩ
NTSC RL = 1 kΩ
NTSC RL = 1 kΩ
VIN = 0 V
TMIN to TMAX
0.5
10
0.6
–0.02
RL = 10 kΩ, –2.67 < VO < +2.67
TMIN to TMAX
Channel-to-Channel, RL = 10 kΩ
INPUT CHARACTERISTICS
+Input Resistance
+Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Output Current
POWER SUPPLY
Operating Range4
Quiescent Current/Amp
Power Supply Rejection Ratio (RTO)
Max
5.5
6
1.6
0.05
0.05
0.03
170
2.5
RL = 10 kΩ, VCC – VOH, VEE + VOL
+VS = 5.5 V to 6.5 V, –VS = –6 V
–VS = –5.5 V to –6.5 V, +VS = 6 V
OPERATING TEMPERATURE RANGE
0.2
175
48
48
0
3.2
60
65
Units
mV
mV
µV/°C
µA
%
%
%
kΩ
pF
0.25
V
mA
13
3.4
V
mA/Amp
dB
dB
+70
°C
NOTES
1
Includes gain resistor thermal noise.
2
RTO offset includes effects of input voltage offset, input current, and input offset current.
3
Measured in the inverting mode.
4
Observe Absolute Maximum Ratings.
Specifications subject to change without notice.
–2–
REV. 0
AD8026
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply␣ Voltage VCC–VEE . . . . . . . . . . . . . . . . . . . . . . . 14.0␣ V
Internal␣ Power␣ Dissipation2
␣␣
Small␣ Outline␣ Package (R) . . . . . . . . . . . . . . . . . . . . 0.9␣ W
+Input Voltage VCC–VIN+ . . . . . . . . . . . . . . . . . . . . . . < 12 V
–Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . < VEE + 12 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > VEE – 12 V
Output Short Circuit Duration
␣ ␣ . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . . 0°C to +70°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C
The maximum power that can be safely dissipated by the
AD8026 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
While the AD8026 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
14-Lead SOIC Package: θJA = 120°C/W, where P D = (TJ – TA)/θ JA.
MAXIMUM POWER DISSIPATION – Watts
1.5
ORDERING GUIDE
Model
Temperature
Range
AD8026AR
0°C to +70°C
AD8026AR-REEL 0°C to +70°C
AD8026AR-REEL7 0°C to +70°C
Package
Description
Package
Option
14-Lead Plastic SOIC SO-14
REEL SOIC
SO-14
REEL 7 SOIC
SO-14
PIN CONFIGURATION
OUT A 1
14
OUT D
–IN A 2
13
–IN D
+IN A 3
12
+IN D
11
VEE
–IN B 6
9
–IN C
OUT B 7
8
OUT C
VCC 4
AD8026
TJ = +1508C
1.0
0.5
–10
0
10
20
30
40
50
60
AMBIENT TEMPERATURE – 8C
70
80
Figure 2. Maximum Power Dissipation vs. Temperature
TOP VIEW
(Not to Scale) 10
+IN B 5
+IN C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8026 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
0.5
2
21.5
0.4
1
18.5
0.3
0
15.5
0.2
–1
0.1
–2
0
–3
–0.2
–0.3
–4
VIN = 50mV rms
RL = 1kV
RS = 0V
CL = 0pF
–5
–0.4
–0.5
100k
1M
10M
FREQUENCY – Hz
100M
VIN = 2.0V p-p
RL = 1kV
VIN = 1.0V p-p
12.5
OUTPUT – dBm
–0.1
NORMALIZED OUTPUT – dB
NORMALIZED FLATNESS – dB
AD8026–Typical Performance Characteristics
9.5
VIN = 0.5V p-p
6.5
3.5
VIN = 0.25V p-p
0.5
–6
–2.5
–7
–5.5
–8.5
100k
–8
500M
1M
10M
FREQUENCY – Hz
100M
500M
Figure 6. Large Signal Bandwidth
Figure 3. Small Signal Bandwidth and 0.1 dB Flatness
3
RL = 10kV
2
20mV/DIV
25mV/DIV
NORMALIZED OUTPUT – dB
VIN = 37.5mV
VOUT = 100mV
1
VIN = 50mV rms
RL = 1kV
CL = 100pF
RS = 25V
0
–1
CL = 200pF
–2
CL = 300pF
–3
–4
–5
–6
50ns/DIV
–7
100k
Figure 4. 100 mV Step Response
1M
10M
FREQUENCY – Hz
100M
500M
Figure 7. Cap Load vs. Frequency
0
VIN = 4V STEP
RL = 10kV
RS = 50V
CL = 100pF
0.1%/DIV
CROSSTALK – dB
–20
VOUT = 2V p-p
RL = 1kV
–40
–60
–80
–100
0
20
40
60
80 100 120 140 160 180
TIME – ns
–120
100k
Figure 5. Short-Term Settling Time
1M
10M
FREQUENCY – Hz
100M
Figure 8. Crosstalk (Output-to-Output) vs. Frequency
–4–
REV. 0
AD8026
10000
0.01
0.00
–0.01
–0.02
–0.03
1
2
3
4
5
6
IRE
7
8
9
10
11
0.03
0.02
NTSC
0.01
0.00
–0.01
–0.02
–0.03
1
2
3
4
5
6
IRE
7
8
9
10
in
10
1000
en
100
1
10
10
11
Figure 9. Differential Gain and Differential Phase
100
1k
FREQUENCY – Hz
10k
0.1
100k
Figure 12. Noise (RTO) vs. Frequency
0
–30
–0.2
–40
–0.4
–50
–0.6
–60
DISTORTION – dBc
VOS RTO – mV
100
NTSC
–0.8
–1.0
–1.2
RL = 1kV
VOUT = 2V p-p
–70
–80
–90
–100
–1.4
–110
–1.6
–120
–1.8
–15
0
15
25
40
TEMPERATURE – 8C
55
–130
100k
70
Figure 10. V OS RTO vs. Temperature
POWER SUPPLY REJECTION RATIO – dB
20
GAIN ACCURACY – %
–0.0005
–0.001
–0.0015
–0.002
–0.0025
15
25
40
TEMPERATURE – 8C
55
10
0
–10
–PSRR
–20
–30
–40
+PSRR
–50
–60
–70
–80
30k
70
Figure 11. Gain Accuracy vs. Temperature
REV. 0
10M
Figure 13. Total Harmonic Distortion
0
0
1M
FREQUENCY – Hz
100k
1M
FREQUENCY – Hz
10M
Figure 14. PSRR vs. Frequency
–5–
100M
NOISE CURRENT – pA/ Hz
0.02
NOISE VOLTAGE, RTO – nV/ Hz
DIFF PHASE – Degrees
DIFF GAIN – %
0.03
AD8026
THEORY OF OPERATION
The AD8026, a quad voltage feedback amplifier with rail-to-rail
output swing, is internally configured for a gain of either –5/3 or
+8/3. The gain-setting resistors are laser trimmed for precise
control of their ratio. In addition, the amplifier’s frequency
response has been adjusted to compensate for the parasitic
capacitances associated with the gain resistors and with the
amplifier’s inverting input. The result is an amplifier with very
tight control of closed-loop gain and settling time.
OUTPUT IMPEDANCE – V
100
10
1
0.1
The amplifier’s input stage will operate with voltages from about
–0.2 V below the negative supply voltage to within about 1 V of
the positive supply. Exceeding these values will not cause phase
reversal at the output; however, the input ESD protection devices will begin to conduct if the input voltages exceed the supply rails by greater than 0.5 V. The gain resistors that connect to
Pins 2, 6, 9, and 13 are protected from ESD in such a way that
the voltages applied to these pins may exceed the negative supply by as much as –7 V.
0.01
10k
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 15. Output Impedance vs. Frequency
The rail-to-rail output range of the AD8026 is provided by a
complementary common-emitter output stage. The chosen
circuit topology allows the outputs to source and sink 50 mA of
output current and, with the use of an external series resistor, to
achieve rapid settling time while driving capacitive loads within
0.5 V of the supply rails.
1M
INPUT IMPEDANCE – V
100k
Output Referred Offset Voltage
10k
The output referred offset voltage for a voltage feedback amplifier can be estimated with the following equation:
1k
(
100
10
10k
(
)
(
(
100k
1M
10M
FREQUENCY – Hz
100M
VOOS = output referred offset voltage,
VIOS = input referred offset voltage,
IOS = difference of the two input currents,
IB = average of the two input currents,
RP = total resistance in series with positive input,
RF = 5 kΩ, RG = 3 kΩ for this part.
1G
This equation leads to the well known conclusion that, for a
voltage feedback amplifier to maintain minimum output offset
voltage, the value of RP should be selected to match the parallel
combination of RF and R G. It should be noted that the AD8026
was designed for an assumed source impedance, of 500 Ω driving the +Input. Therefore, the value of RP included on the chip
is 500 Ω less than the ideal value for minimum output offset.
Additional resistance may be added externally, in series with the
+Input, if the part is to be driven by a lower impedance source.
20
VIN = 50mV rms
CL = 100pF
10
0V
0
24.9V
49.9V
–10
1875V
RS
+
–
–20
5kV
100V
APPLICATIONS
CL
The AD8026 is designed with on-chip resistors for each op amp
to provide accurate fixed gain and low output-referenced offset
voltages. This can result in significant cost and board-space savings
for systems that can take advantage of the AD8026 specifications.
3kV
1
100k
))
where:
Figure 16. Input Impedance vs. Frequency
NORMALIZED OUTPUT – dB
)
VOOS = V IOS × 1+ R F /RG + IOS × RF iRG + I B × RP − RF iRG
1M
10M
FREQUENCY – Hz
100M
500M
The part is actually trimmed in three steps. First, the supply
current of the part is trimmed. Then the gain is accurately
trimmed to specification. This trim adjusts the values of either
the gain or feedback resistor for a ratio of 5 to 3. The final trim
is for the offset voltage. For this trim, the –Input is connected to
ground and the +Input is connected to ground via 500 Ω, while
internal offset resistors are trimmed.
Figure 17. Bandwidth and Flatness vs. Series Resistance
into 100 pF
–6–
REV. 0
AD8026
In a system application, the part is designed assuming that each
–Input will be driven from a low impedance source, while each
+Input will be driven by a current-output DAC with a 500 Ω
termination resistor. Thus, to first order, each on-chip series
input resistor to each +Input is 500 Ω less than the parallel
combination of the gain-setting resistors. The offset-inducing
effect of the bias currents is minimized by this scheme.
QUAD AMPLIFIER CHARACTERIZATION BOARD
Figure 18 shows how to drive the AD8026 with a fixed positive
gain of 8/3 from a current output DAC. The gain and offset
errors are minimized by using a 500 Ω resistor (RI) to convert
the DAC output current into a voltage. The gain resistor (RG)
should be directly connected to ground, or driven from a low
output impedance source to ensure minimum offset and maximum gain accuracy.
If the +Input of any of the op amps is driven from a voltage
source, the low offset voltage of the AD8026 can be maintained
by adding a series resistance of 500 Ω between the source and
the +Input to the AD8026. This is illustrated in Figure 19. If
the –Input is to be driven, such as when creating an offset voltage, then a low source impedance should be provided in order
to maintain both gain and offset accuracy.
+VS
Figure 20. Component Side
10mF
0.1mF
CURRENTOUTPUT
DAC
VIN
RP
RI
500V
+IB
1/4 AD8026
VOUT
RS
CL
RF
–IB
RG
0.1mF
10mF
–VS
Figure 21. Solder Side
Figure 18. Low Offset and High Gain Accuracy Circuit for
Driving the AD8026 from a Current Output DAC
+VS
10mF
0.1mF
VOLTAGEOUTPUT
DRIVER
VIN
RI
500V
RP
1/4 AD8026
VOUT
+IB
–IB
RF
RS
CL
RG
0.1mF
10mF
–VS
Figure 19. Low Offset and High Gain Accuracy Circuit for
Driving the AD8026 from a Voltage Source
REV. 0
Figure 22. Silkscreen
–7–
AD8026
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3327–8–4/98
14-Lead SOIC
(SO-14)
0.3444 (8.75)
0.3367 (8.55)
14
8
1
7
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.0500
SEATING (1.27)
PLANE BSC
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
3 458
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
PRINTED IN U.S.A.
0.1574 (4.00)
0.1497 (3.80)
–8–
REV. 0