a Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10465 FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-to-Channel Matching, ⴞ0.5% Gain Error Channel-to-Channel Isolation, >90 dB DC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range (ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V) Gain Flatness up to 25 MHz: < 0.2 dB 80 dB Spurious-Free Dynamic Range Two’s Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 1.75 W per Channel Industrial and Military Grade utilize an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD10465 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings. The AD10465 operates with ±5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs. The AD10465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Antijamming Receivers Multichannel, Multimode Receivers The AD10465 is packaged in a 68-lead Ceramic Gull Wing package, footprint-compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufacturing is done on Analog Devices, Inc. Mil-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–40°C to +85°C). The AD6644 internal components are manufactured on Analog Devices, Inc. high-speed complementary bipolar process (XFCB). PRODUCT DESCRIPTION The AD10465 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6644 ADCs. Each AD6644 has a dccoupled amplifier front end including an AD8037 low distortion, high bandwidth amplifier, providing a high input impedance and gain, and driving the AD8138 single-to-differential amplifier. The AD6644s have on-chip track-and-hold circuitry and PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance. 5. Footprint compatible family; 68-lead LCC. FUNCTIONAL BLOCK DIAGRAM AINA3 AINA2 AINA1 AINB3 AINB2 AINB1 REF A DRAOUT D0A (LSB) REF B D1A D2A DRBOUT D3A ENC AD10465 D4A TIMING ENC D5A D6A D7A 11 D8A D9A D10A TIMING ENC ENC VREF DROUT VREF DROUT 14 14 D13B D12B 5 OUTPUT BUFFERING 9 OUTPUT BUFFERING 3 D11B D10B D9B D11A D12A D13A (MSB) D0B (LSB) D1B D2B D3B D4B D5B D6B D7B D8B REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD10465–SPECIFICATIONS (AV Parameter CC = +5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC unless otherwise noted.) Temp Test Level Mil Subgroup AD10465AZ/BZ/QML-H Min Typ Max RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error1 Gain Error Channel Match 14 Full 25°C Full Full 25°C Full 25°C Max Min VI I VI V I VI I I I ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth3 Full Full Full V V V Full Full Full 25°C Full IV IV IV IV V ENCODE INPUT (ENC, ENC)4 Differential Input Voltage 17 Differential Input Resistance Differential Input Capacitance Full 25°C 25°C IV V V SWITCHING PERFORMANCE Maximum Conversion Rate 5 Minimum Conversion Rate 5 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay (T E_DR) Full Full 25°C 25°C 25°C 25°C 25°C Full Full VI V V IV V IV IV V 25°C 25°C Full 25°C Full 25°C Full 25°C 25°C Full 25°C Full 25°C Full SNR6 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz SINAD7 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz 1, 2, 3 1 2, 3 1 2, 3 1 2 3 –2.2 –2.2 –1 –3 –5 –1.5 –3 –5 Guaranteed ± 0.02 ± 1.0 ± 1.0 –1.0 ± 2.0 ± 0.5 ± 1.0 Bits +2.2 +2.2 +1 +1 +5 +1.5 +3 +5 ± 0.5 ± 1.0 ±2 12 12 12 12 99 198 396 0 100 200 400 4.0 100 101 202 404 7.0 65 20 1.5 250 0.3 7.7 7.7 6.8 11.5 Ω Ω Ω pF MHz V p-p kΩ pF 10 2.5 12 % FS % FS % % FS % FS % % % V V V 0.4 4, 5, 6 12 Unit 500 12 12 6.2 6.2 V I II I II I II 4 5, 6 4 5, 6 4 5, 6 69 68 68 67 67 67 70 70 70 70 70 69 69 dBFS dBFS dBFS dBFS dBFS dBFS dBFS V I II I II I II 4 5, 6 4 5, 6 4 5, 6 67.5 67.5 65 65 60 58 70 69 69 68 68 63 61 dB dB dB dB dB dB dB –2– 9.2 9.2 MSPS MSPS ns ps ps rms ns ns ns ns REV. 0 AD10465 Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Temp Test Level Mil Subgroup AD10465AZ/BZ/QML-H Min Typ Max 25°C 25°C Full 25°C Full 25°C Full V I II I II I II 4 5, 6 4 5, 6 4 5, 6 73 70 72 70 62 60 25°C 4 5, 6 4 5, 6 78 78 68 60 12 Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz TWO-TONE IMD REJECTION 9 fIN = 10 MHz and 11 MHz f1 and f2 are –7 dB fIN = 31 MHz and 32 MHz f1 and f2 Are –7 dB 25°C Full I II I II CHANNEL-TO-CHANNEL ISOLATION 10 25°C IV TRANSIENT RESPONSE 25°C V Full Full IV IV OVERVOLTAGE RECOVERY TIME VIN = 2.0 × fS VIN = 4.0 × fS Unit 8 85 82 82 78 78 68 66 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 87 dBFS 70 dBFS 90 dB 15.3 ns 11 DIGITAL OUTPUTS 12 Logic Compatibility DVCC = 3.3 V Logic “1” Voltage Logic “0” Voltage DVCC = 5 V Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY AVCC Supply Voltage13 I (AVCC) Current AVEE Supply Voltage13 I (AVEE) Current DVCC Supply Voltage13 I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) Passband Ripple to 10 MHz Passband Ripple to 25 MHz 12 12 40 150 100 200 ns ns 0.5 V V CMOS Full Full I I Full Full V V Full Full Full Full Full Full Full Full Full VI I VI V VI V I I V V V 1, 2, 3 1, 2, 3 2.5 DVCC – 0.2 0.2 DVCC – 0.3 0.35 Two’s Complement 4.85 –5.25 3.135 1, 2, 3 1, 2, 3 5.0 270 –5.0 38 3.3 30 338 3.5 0.02 0.1 0.2 V V 5.25 308 –4.75 49 3.465 46 403 3.9 V mA V mA V mA mA W % FSR/% VS dB dB NOTES 1 Gain tests are performed on A IN1 input voltage range. 2 Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 All ac specifications tested by driving ENCODE and ENCODE differentially. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full power. 7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 8 Analog input signal power swept from –1 dBFS to –60 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 11 Input driven to 2× and 4× AIN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS. 12 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. All specifications guaranteed within 100 ms of initial power-up regardless of sequencing. Specifications subject to change without notice. REV. 0 –3– AD10465 ABSOLUTE MAXIMUM RATINGS 1 Parameter TEST LEVEL I. 100% Production Tested. Min Max Units ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL2 Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) 0 –7 VEE –10 0 –10 –40 –65 7 0 VCC +10 VCC 4 +10 V V V mA V V mA +85 174 300 +150 °C °C °C °C II. 100% Production Tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample Tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at temperature at 25°C, sample tested at temperature extremes. NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for “ES” package: θJC = 2.2°C/W; θJA = 24.3°C/W. ORDERING GUIDE Model Temperature Range Package Description AD10465AZ AD10465BZ 5962-9961601HXA AD10465/PCB –25°C to +85°C (Case) –40°C to +85°C (Case) –40°C to +85°C (Case) 25°C 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10465AZ CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD10465 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1 2, 4, 5, 9–11 SHIELD AGNDA 3 6 7 8 12 13 14 26, 27 15–25, 31–33 28 29 30 43, 44 34–42, 45–49 53–54, 57–61, 65, 68 REF_A AINA1 AINA2 AINA3 DRAOUT AVEE AVCC DGNDA D0A–D13A ENCODEA ENCODEA DVCC DGNDB D0B-D13B AGNDB 50 51 52 55 56 62 63 64 66 67 DVCC ENCODEB ENCODEB DRBOUT REF_B AINB1 AINB2 AINB3 AVCC AVEE Internal Ground Shield between channels. A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. A Channel Internal Voltage Reference. Analog Input for A side ADC (nominally ± 0.5 V). Analog Input for A side ADC (nominally ± 1.0 V). Analog Input for A side ADC (nominally ± 2.0 V). Data Ready A Output. Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). Analog Positive Supply Voltage (nominally 5.0 V). A Channel Digital Ground. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital Positive Supply Voltage (nominally 5.0 V/3.3 V). B Channel Digital Ground. Digital Outputs for ADC B. D0 (LSB). B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally 5.0 V/3.3 V). Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Data Ready B Output. B Channel Internal Voltage Reference. Analog Input for B side ADC (nominally ± 0.5 V). Analog Input for B side ADC (nominally ± 1.0 V). Analog Input for B side ADC (nominally ± 2.0 V). Analog Positive Supply Voltage (nominally –5.0 V). Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). . PIN CONFIGURATION 1 68 67 66 65 64 63 62 61 6 4 3 2 AGNDB SHIELD AGNDB 5 7 A IN B2 A IN B1 AGNDA AGNDA REF A AGNDA 8 AVCC AGNDB A IN B3 AINA1 AINA2 AINA3 9 AGNDA 10 AVEE AGNDA 68-Lead Ceramic Leaded Chip Carrier 60 AGNDB PIN 1 IDENTIFIER AGNDA 11 59 AGNDB DRAOUT 12 AVEE 13 58 AGNDB 57 AGNDB AVCC 14 56 REF B D0A(LSBA) 15 55 DRBOUT D1A 16 D2A 17 54 AGNDB AD10465 D3A 18 53 AGNDB 52 ENCODEB TOP VIEW (Not to Scale) D4A 19 51 ENCODEB D5A 20 50 DVCC 49 D13B(MSBB) D6A 21 D7A 22 D8A 23 48 D12B 47 D11B D9A 24 46 D10B D10A 25 45 D9B DGNDA 26 44 DGNDB –5– DGNDB D8B D6B D7B D5B D4B D3B D2B D1B D0B(LSBB) D12A D13A(MSBA) DVCC D11A DGNDA REV. 0 ENCODEA ENCODEA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AD10465–Typical Performance Characteristics 0 0 –20 –20 –30 –40 –40 –50 –50 –60 –60 dB dB –30 –70 –70 –80 –80 3 2 –90 4 2 –90 5 6 –100 –100 –110 –110 –120 –120 –130 ENCODE = 65MSPS AIN = 10MHz (–1dBFS) SNR = 70.79 SFDR = 86.06dBc –10 ENCODE = 65MSPS AIN = 5MHz (–1dBFS) SNR = 71.02 SFDR = 92.11dBc –10 5 –130 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY – MHz FREQUENCY – MHz TPC 1. Single Tone @ 5 MHz TPC 4. Single Tone @ 10 MHz 0 0 ENCODE = 65MSPS AIN = 20MHz (–1dBFS) SNR = 70.71 SFDR = 79.73dBc –10 –20 –20 –30 –40 –40 –50 –50 –60 –60 –70 –70 3 –80 2 –90 6 3 2 –80 5 –90 4 –100 –100 –110 –110 –120 –120 –130 –130 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 0 ENCODE = 65MSPS AIN = 25MHz (–1dBFS) SNR = 70.36 SFDR = 74.58dBc –10 dB dB –30 5 0 6 4 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY – MHz FREQUENCY – MHz TPC 2. Single Tone @ 20 MHz TPC 5. Single Tone @ 25 MHz 0 100 ENCODE = 65MSPS AIN = 32MHz (–1dBFS) SNR = 70.22 SFDR = 66.40dBc –10 –20 –30 90 SFDR 80 –40 70 –50 60 –60 2 –dBc dB 3 4 6 3 –70 SINAD 50 40 –80 –90 5 6 –100 30 4 20 –110 10 –120 –130 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 4.989 FREQUENCY – MHz 9.989 19.000 32.000 INPUT FREQUENCY – MHz TPC 3. Single Tone @ 32 MHz TPC 6. SFDR and SINAD vs. Frequency –6– REV. 0 AD10465 0 0 ENCODE = 65MSPS AIN = 9MHz AND 10MHz (–7dBFS) SFDR = 82.83dBc –10 –20 –20 –30 –40 –40 –50 –50 –60 –60 dB dB –30 –70 –80 F2– –90 F1 2F1– F2 2F1+ F2 F1+ F2 2F2– F1 2F2+ F1 2F2+ F1 –70 2F1+ F2 –80 F2– F1 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 ENCODE = 65MSPS AIN = 17MHz AND 18MHz (–7dBFS) SFDR = 77.68dBc –10 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 0 2F1– F2 2F2– F1 F1+ F2 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY – MHz FREQUENCY – MHz TPC 7. Two Tone @ 9/10 MHz TPC 10. Two Tone @ 17/18 MHz 3.0 3.0 ENCODE = 65MSPS DNL MAX = +0.549 CODES DNL MIN = –0.549 CODES 2.5 ENCODE = 65MSPS INL MAX = +1.173 CODES INL MIN = –1.332 CODES 2.0 2.0 1.0 LSB LSB 1.5 1.0 0 0.5 –1.0 0 –2.0 –0.5 –1.0 –3.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 TPC 8. Differential Nonlinearity 2048 4096 6144 8192 10240 12288 14336 16384 TPC 11. Integral Nonlinearity 0 72.0 –1 71.5 –2 –40ⴗC 71.0 –3 70.5 +25ⴗC SNRFS dBFS –4 –5 70.0 +85ⴗC 69.5 –6 69.0 –7 –8 68.5 –9 68.0 –10 1.0 4.2 7.4 10.6 13.8 17.0 20.2 23.4 26.6 29.8 67.5 33.0 5 FREQUENCY – MHz 19 AIN – MHz TPC 9. Gain Flatness REV. 0 10 TPC 12. SNR vs. AIN Frequency –7– 32 AD10465 DEFINITION OF SPECIFICATIONS Analog Bandwidth Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Power Supply Rejection Ratio Aperture Delay The ratio of a change in input offset voltage to a change in power supply voltage. The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled. Signal-to-Noise-and-Distortion (SINAD) Aperture Uncertainty (Jitter) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. May be reported in dB (i.e., relative to signal level) or in dBFS (always related back to converter full scale). The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Signal-to-Noise Ratio (without Harmonics) Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dB (i.e., relative to signal level) or in dBFS (always related back to converter full scale). Harmonic Distortion Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the worst harmonic component. The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Transient Response The time required for the converter to achieve 0.03% accuracy when a one-half full-scale step function is applied to the analog input. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBFS. Maximum Conversion Rate The encode rate at which parametric testing is performed, above which converter performance may degrade. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. tA N+3 N AIN N+1 N+2 t ENC ENC, ENC t ENCH N N+4 t ENCL N+2 N+1 N+3 N+4 t E, DR D[13:0] N–3 N–2 t OD N–1 N DRY Figure 1. Timing Diagram –8– REV. 0 AD10465 DVCC AVIN3 200⍀ CURRENT MIRROR AVIN2 100⍀ AVIN1 TO AD8037 100⍀ DVCC VREF Figure 2. Analog Input Stage DR OUT LOADS AVCC AVCC AVCC AVCC 10k⍀ 10k⍀ CURRENT MIRROR ENCODE ENCODE 10k⍀ 10k⍀ Figure 4. Digital Output Stage DVCC CURRENT MIRROR LOADS Figure 3. ENCODE Inputs THEORY OF OPERATION DVCC The AD10465 is a high dynamic range 14-bit, 65 MHz pipeline delay (three pipelines) analog-to-digital converter. The custom analog input section maintains the same input ranges (1 V p-p, 2 V p-p, and 4 V p-p) and input impedance (100 Ω, 200 Ω, and 400 Ω) as the AD10242. The AD10465 employs four monolithic ADI components per channel (AD8037, AD8138, AD8031, and AD6644), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter. The input signal is passed through a precision laser-trimmed resistor divider allowing the user to externally select operation with a full-scale signal of ± 0.5 V, ± 1.0 V or ± 2.0 V by choosing the proper input terminal for the application. The AD10465 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs. The AD8037 amplifier provides a high input impedance and gain for driving the AD8138 in a single-ended to differential amplifier configuration. The AD8138 has a –3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the AD6644, maximizing the performance of the ADC. The AD8031 provides the buffer for the internal reference of the AD6644. The internal reference voltage of the AD6644 is designed to track the offsets and drifts of the ADC and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common mode input on the AD8138. The AD6644 reference voltage sets the output common-mode on the AD8138 at 2.4 V, which is the midsupply level for the AD6644. The AD6644 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold, REV. 0 VREF 100⍀ D0–D13 CURRENT MIRROR Figure 5. Digital Output Stage TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives 14 bits of precision which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two’s complement. USING THE FLEXIBLE INPUT The AD10465 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. While the standard inputs are ± 0.5 V, ± 1.0 V and ± 2.0 V, the user can select the input impedance of the –9– AD10465 AD10465 on any input by using the other inputs as alternate locations for GND or an external resistor. The following chart summarizes the impedance options available at each input location: AIN1 = AIN1 = AIN1 = AIN2 = AIN2 = AIN2 = AIN2 = AIN3 = AIN3 = AIN3 = AIN3 = VT 0.1F ENCODE ECL/ PECL 100 Ω when AIN2 and AIN3 are open. 75 Ω when AIN3 is shorted to GND. 50 Ω when AIN2 is shorted to GND. 200 Ω when AIN3 is open. 100 Ω when AIN3 is shorted to GND. 75 Ω when AIN2 to AIN3 has an external resistor of 300 Ω, with AIN3 shorted to GND. 50 Ω when AIN2 to AIN3 has an external resistor of 100 Ω, with AIN3 shorted to GND. 400 Ω. 100 Ω when AIN3 has an external resistor of 133 Ω to GND. 75 Ω when AIN3 has an external resistor of 92 Ω to GND. 50 Ω when AIN3 has an external resistor of 57 Ω to GND. ENCODE VT Figure 7. Differential ECL for Encode Jitter Considerations The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. 1 + ε N + 2 2 SNR = −20 × log (2 × π × f ANALOG × t J rms) 2 VNOISE RMS 2N APPLYING THE AD10465 Encoding the AD10465 The AD10465 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 32 MHz input signals when using a high-jitter clock source. See Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance” for complete details. For optimum performance, the AD10465 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. T1-4T (1) fANALOG = analog input frequency. tJ RMS = rms jitter of the encode (rms sum of encode source and internal encode circuitry). ε = average DNL of the ADC (typically 0.50 LSB). N = Number of bits in the ADC. For a 14-bit analog-to-digital converter like the AD10465, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD10465 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance.” 71 ENCODE AD10465 ENCODE AIN = 5MHz 70 69 68 SNR – dBFS CLOCK SOURCE 1/2 + VNOISE RMS = V rms noise referred to the analog input of the ADC (typically 5 LSB). Shown below is one preferred method for clocking the AD10465. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD10465 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD10465, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary. 0.1nF 100⍀ AD10465 0.1F AIN = 10MHz 67 66 65 AIN = 20MHz 64 HSMS2812 DIODES 63 Figure 6. Crystal Clock Oscillator, Differential Encode 62 If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola. 61 AIN = 32MHz 60 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 0.1 0.3 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 3.9 RMS CLOCK JITTER – ps Figure 8. SNR vs. Jitter –10– REV. 0 AD10465 Power Supplies LAYOUT INFORMATION Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be “received” by the AD10465. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 µF chip capacitors. The schematic of the evaluation board (Figure 10) represents a typical implementation of the AD10465. The pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. The AD10465 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD10465 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs. Output Loading Care must be taken when designing the data receivers for the AD10465. The digital outputs drive an internal series resistor (e.g., 100 Ω) followed by a gate like 75LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 10. The digital outputs of the AD10465 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V, ÷ 1 ns) of dynamic current per bit will flow in or out of the device. A full-scale transition can cause up to 140 mA (14 bits × 10 mA/bit) of current flow through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD10465. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. EVALUATION BOARD The AD10465 evaluation board (Figure 9) is designed to provide optimal performance for evaluation of the AD10465 analogto-digital converter. The board encompasses everything needed to insure the highest level of performance for evaluating the AD10465. The board requires an analog input signal, encode clock and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD10465. The digital outputs of the AD10465 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required. Figure 9a. Evaluation Board Mechanical Layout REV. 0 –11– AD10465 JP5 J1 LATCHB CLKLATCHB2 AINB3 1 CLKLATCHB1 AGNDB JP3 J2 U2:A 3 74LCX00M AINB2 U2:D 13 11 4 U2:B 74LCX00M BUFLATB JP2 BUFLATA 6 5 12 2 JP1 74LCX00M DRBOUT DRAOUT AGNDB J22 1 JP4 AINB1 U4:A 3 2 U4:D 13 11 12 4 U4:B 6 5 CLKLATCHA1 74LCX00M AGNDB 74LCX00M 74LCX00M JP6 CLKLATCHA2 J7 LATCHA AINA3 AGNDA –5.2VAB J8 AINA2 47⍀ AT 100MHz L9 47⍀ AT 100MHz L8 47 47 C59 10F +5VAB C52 10F AGNDA AINB3 AINB2 AINB1 C57 0.1F AGNDB +5VAB AINA3 AINA2 AINA1 AINA1 AGNDA AGNDB J20 DRAOUT AGNDA DGNDA 61 AINB1 AGNDB 64 63 62 67 66 65 +5VAB AGNDB AINB3 AINB2 SHIELD AGNDB –5.2VAB AD10465 DGNDA L11 +3.3VDA D12B D11B D10B D9B DGNDB 60 59 58 57 56 55 54 53 C61 0.1F DRBOUT AGNDB 52 51 50 ENCBB ENCB DUT 3.3VDB 49 48 47 L6 47 D13B(MSB) C64 0.1F D12B D11B D10B D9B 46 45 44 +3.3VDB C58 10F DGNDB AGNDB D8B D4B D5B D6B D7B AGNDA AGNDB AGNDB AGNDB AGNDB REFB DRBOUT AGNDB AGNDB ENCBB ENCB +3.3VDB D13B(MSB) U1 D1B D2B D3B C53 10F 47 47⍀ AT 100MHz DUT 3.3VDA D11A D12A D13A DB0B L7 +5VAA D0A D1A D2A D3A D4A D5A D6A D7A D8B D9A D10A AGNDA AGNDA DRAOUT –5.2VAA +5VAA D0A(LSB) D1A D2A D3A D4A D5A D6A D7A D8B D9A D10A 27 28 29 30 31 32 33 34 35 36 +5VAA 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 D0B(LSB) D1B D2B 37 D3B 38 D4B 39 D5B 40 D6B 41 D7B 42 D8B 43 DGNDB 47 ENCAB ENCA C22 10F AINA2 AINA1 AGNDA AGNDA REFA AGNDA L10 DGNDA ENCAB ENCA +3.3VDA D11A D12A D13A(MSB) AGNDA –5.2VAA AGNDA AINA3 9 8 7 6 5 4 3 2 1 68 AGNDA DGNDB DUT 3.3VDB C62 10F DGNDA 47 10 C26 0.1F DGNDA DUT 3.3VDA SPARE GATE C63 0.1F 9 U2:C 8 10 C27 0.1F 9 74LCX00M DGNDB DGNDB SPARE GATE U4:C 8 74LCX00M DGNDA DGNDA Figure 9b. Evaluation Board –12– REV. 0 AD10465 +5VAA U6 2 6 +5VAA ADP3330 IN OUT NR SD ERR 1 C45 100pF 8 3 AGNDA GND C42 0.1F J6 4 JP11 OPEN ENCODEA AGNDA R140 33k⍀ R82 51⍀ AGNDA C44 0.1F U7 1 AGNDA 2 C40 0.1F J18 3 ENCODEA AGNDA 4 R83 51⍀ JP8 JP7 NC D D C49 0.1F 7 Q 6 Q VBB ENCAB 8 VCC ENCA 5 VEE MC10EP16D NC = NO CONNECT AGNDA AGNDA C41 0.47F R94 100⍀ AGNDA AGNDA +5VAA R89 100⍀ U8 2 6 +5VAA ADP3330 IN OUT NR SD ERR 1 C43 100pF 8 3 AGNDB GND C37 0.1F J16 ENCODEB AGNDB 4 JP12 OPEN R141 33k⍀ R76 51⍀ AGNDB C48 0.1F U9 1 AGNDB 2 C39 0.1F J17 3 ENCODEB AGNDB R79 51⍀ AGNDB 4 JP10 JP9 NC D D VBB VCC Q Q VEE ENCB 8 C46 0.1F 7 6 ENCBB 5 MC10EP16D NC = NO CONNECT AGNDB C38 0.47F AGNDB Figure 9c. Evaluation Board REV. 0 –13– R95 100⍀ AGNDAB R97 100⍀ AD10465 OUT 3.3VDA R117 100⍀ OUT 3.3VDA U21 C13 0.1F C14 0.1F C15 0.1F C20 0.1F VCC R98 51⍀ LATCHA 24 DGNDA BANANA JACKS FOR GNDS AND PWRS (LSB) D0A +5VAB +5VAA +3.3VDB R100 0⍀ R99 0⍀ +3.3VDA E1 D1A D2A D3A D4A D5A DGNDA E2 D6A E3 D7A D8A D9A E4 E5 D10A E6 D11A D12A (MSB) D13A E7 25 E8 E10 E9 VCC CP2 OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND VCC 42 VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8 O6 O5 O4 O3 O2 O1 O0 GND GND R116 100⍀ 7 16 O7 R115 100⍀ 31 12 11 9 8 6 R114 100⍀ AGNDA –5.2VAA DGNDB BUFLATA R103 100⍀ C24 0.1F VCC R119 51⍀ LATCHB DGNDA E72 E140 E141 E142 E144 E145 E147 E150 E151 E154 E185 E194 E196 E198 E200 E202 E204 E206 E223 E225 AGNDA E162 E163 E164 E165 E166 E171 E172 E177 E179 E181 E186 E187 E207 E209 E211 E213 E215 E217 E219 E221 E227 E229 E231 E233 E159 E160 E161 E167 E168 E169 E170 E178 E180 E182 E183 E191 E192 E193 E208 E210 E212 E214 E216 E218 E220 E222 E228 E230 E232 E234 (LSB) D0B R123 0⍀ 25 24 DGNDB E87 E88 E89 E139 E143 E146 E148 E149 E152 E153 E184 E188 E189 E190 E195 E197 E199 E201 E203 E205 E224 E226 DGNDB 8 21 19 22 18 23 17 24 16 25 15 26 14 27 13 28 12 29 11 30 10 31 9 32 8 33 R108 100⍀ R107 100⍀ 21 22 23 24 25 26 27 28 29 30 31 32 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 7 7 6 6 5 5 4 4 3 3 2 2 1 1 R109 100⍀ J3 R110 100⍀ DGNDA MSB R112 100⍀ R124 D1B 0⍀ D2B D3B D4B D5B DGNDB D6B D7B D8B D9B D10B D11B D12B (MSB) D13B VCC CP2 OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND VCC 42 O6 O5 O4 O3 O2 O1 O0 GND GND R126 100⍀ 7 16 VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8 O7 R127 100⍀ 31 12 11 9 8 6 R125 100⍀ R128 100⍀ R134 100⍀ R137 51⍀ BUFLATB R135 100⍀ R136 100⍀ R131 100⍀ 3 2 21 R132 100⍀ R133 100⍀ 15 18 GND 4 GND 20 19 19 18 18 R129 100⍀ 5 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 1 R120 100⍀ 25 25 26 26 27 27 28 28 29 29 30 31 32 30 31 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 2 1 J4 R121 100⍀ 74LCX163743MTD 21 21 22 22 23 23 24 24 20 R130 100⍀ R122 100⍀ AGNDB 11 9 R101 100⍀ OUT 3.3VDB C23 0.1F 12 10 R102 100⍀ U22 C21 0.1F 13 20 DGNDA OUT 3.3VDA C25 0.1F 15 14 R111 100⍀ DGNDA AGNDB 16 R118 51⍀ 74LCX163743MTD –5.2VAB 17 R106 100⍀ 15 18 GND 4 GND 18 R104 100⍀ 3 2 19 R105 100⍀ 5 21 20 R113 100⍀ DGNDB MSB DGNDB Figure 9d. Evaluation Board –14– REV. 0 AD10465 Bill of Materials List for AD10465 Evaluation Board Reference Qty Designator Value Description Manufacturer and Part Number Component Name 2 U2, U4 IC, Low-Voltage Quad 2-Input Nand, SOIC-14 Toshiba/TC74LCX00FN 74LCX00M 2 U21, U22 IC, 16-Bit Transparent Latch with Three-State Outputs, TSSOP-48 Fairchild/74LCX163743MTD 74LCX163743MTD 1 U1 DUT, IC 14-Bit Analog-to-Digital Converter ADI/AD10465AZ ADI/AD10465AZ 2 U6, U8 IC, Voltage Regulator 3.3 V, RT-6 Analog Devices/ADP3330ART-3, 3-RLT ADP3330 10 E1–E10 Banana Jack, Socket Johnson Components/08-0740-001 Banana Hole 22 C13–C15, C20, C21, C23–C27, C37, C39, C40, C42, C44, C46, C48, C49, C57, C61, C63, C64 0.1 µF Capacitor, 0.1 µF, 20%, 12 V dc, 0805 Mena/GRM40X7R104K025BL CAP 0805 2 C38, C41 0.47 µF Capacitor, 0.47 µF, 5%, 12 V dc, 1206 Vitramon/VJ1206U474MFXMB CAP 1206 2 C43, C45 100 pF Capacitor, 100 pF, 10%, 12 V dc, 0805 Johansen/500R15N101JV4 CAP 0805 2 J3, J4 Connector, 40-pin Header Male St. Samtec/TSW-120-08-G-D HD40M 6 L6–L11 Inductor, 47 µH @ 100 MHz, 20%, IND2 Fair-Rite/2743019447 IND2 2 U7, U9 IC, Differential Receiver, SOIC-8 Motorola/MC10EP16D MC10EP16D 6 C22, C50, C52, C53, C59, C62 10 µF Capacitor, 10 µF, 20%, 16 V dc, 1812POL Kemet/T491C106M016A57280 POLCAP 1812 R99, R100, R123, R124 0.0 Ω Resistor, 0.0 Ω, 0805 Panasonic/ERJ-6GEY0R00V RES2 0805 2 R140, R141 33,000 Ω Resistor, 33,000 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ333V RES2 0805 8 R76, R79, R82, R83, R98, R118, R119, R137 51 Ω Resistor, 51 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ510V RES2 0805, RES 0805 36 R89, R94, R95, R97, R101–R117, R120–R122, R125–R136 100 Ω Resistor, 100 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ101V RES2 0805, RES 0805 8 J1, J2, J6–J8, J16–J18, J20, J22 Connector, SMA Female St. Johnson Components/142-0701-201 SMA 4 REV. 0 47 µH –15– AD10465 Figure 10a. Top Layer Copper Figure 10b. Second Layer Copper –16– REV. 0 AD10465 Figure 10c. Third Layer Copper Figure 10d. Fourth Layer Copper REV. 0 –17– AD10465 Figure 10e. Fifth Layer Copper Figure 10f. Bottom Layer Copper –18– REV. 0 AD10465 Figure 10g. Bottom Silkscreen Figure 10h. Bottom Assembly REV. 0 –19– AD10465 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C02356–4.5–1/01 (rev. 0) 68-Lead Ceramic Leaded Chip Carrier (ES-68A) 1.180 (29.97) SQ 0.950 (24.13) SQ 0.240 (6.096) 0.060 (1.52) 61 9 10 60 PIN 1 0.800 (20.32) TOP VIEW (PINS DOWN) 26 44 43 27 0.018 (0.457) PRINTED IN U.S.A. 0.050 (1.27) –20– REV. 0