a Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD13465 FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-to-Channel Matching, ⴞ1% Gain Error 90 dB Channel-to-Channel Isolation DC-Coupled Signal Conditioning 85 dB Spurious-Free Dynamic Range Selectable Bipolar Inputs (ⴞ1 V and ⴞ0.5 V Ranges) Integral Two-Pole Low-Pass Nyquist Filter Two’s Complement Output Format 3.3 V Compatible Outputs 1.8 W per Channel Industrial and Military Grade state-of-the-art high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching and impedance control, and provide for significant board area savings. Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while remaining general-purpose. The AD13465 operates with ± 5.0 V for the analog signal conditioning, 5.0 V supply for the analog-to-digital conversion, and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent Encode and Analog Inputs, while maintaining minimal crosstalk and interference. APPLICATIONS Radar Processing Optimized for I/Q Baseband Operation Phased Array Receivers Multichannel, Multimode Receivers GPS Antijamming Receivers Communications Receivers The AD13465 is packaged in a 68-lead ceramic gull wing package. Manufacturing is done on Analog Devices’ MIL38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–40°C to +85°C). The components are manufactured using Analog Devices’ high-speed complementary bipolar process (XFCB). PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD13465 is a complete dual channel signal processing solution including on-board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13465 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. The AD13465 uses 1. Guaranteed sample rate of 65 MSPS. 2. Input signal conditioning included; gain and impedance matching. 3. Single-ended, differential, or off-module filter options. 4. Fully tested/characterized full channel performance 5. Pin compatible with 12-bit AD13280 product family. FUNCTIONAL BLOCK DIAGRAM AMP-IN-A-2 AMP-IN-A-1 AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B AMP-OUT-A A–IN B+IN A+IN B–IN DROUTA (LSB) D0A DROUTB AD13465 D1A ENC D2A TIMING D3A D4A VREF D5A DROUT D6A D7A D8A D9A VREF DROUT D13B (MSB) 14 D12B 14 11 100⍀ OUTPUT TERMINATORS TIMING 3 100⍀ OUTPUT TERMINATORS 5 ENC ENC D11A D12A D13A (MSB) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. D11B D10B 9 D9B D10A REV. 0 ENC D0B D1B D2B D3B D4B D5B (LSB) D6B D7B D8B One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 (AVCC = 5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC with Front AD13465–TARGET SPECIFICATIONS End Amplifier unless otherwise noted.) Parameter Temp Test Level Mil SubGroup Min RESOLUTION DC ACCURACY No Missing Codes Offset Error AD13465AZ/BZ Typ Max 14 IV I VI VI I VI I VI VI Full Full V V Full Full IV IV Full V 100 200 4.0 100 DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to A–IN and B+IN to B–IN 4 Input Impedance Analog Input Bandwidth 3 Full Full Full V V V ± 1.0 618 50 V Ω MHz ENCODE INPUT (ENC, ENC) 5 Differential Input Voltage Differential Input Resistance Differential Input Capacitance Full 25°C 25°C IV V V 12 10 2.5 V p-p kΩ pF Full Full 25°C 25°C 25°C 25°C 25°C Full Full VI IV V IV V IV IV IV V 4, 5, 6 12 25°C 25°C Full 25°C Full 25°C Full V I II I II V V 25°C 25°C Full 25°C Full 25°C Full V I II I II V V Gain Error Channel Match SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 AMP-IN-X-2 Input Resistance AMP-IN-X-1 AMP-IN-X-2 Input Capacitance2 Analog Input Bandwidth 3 SWITCHING PERFORMANCE Maximum Conversion Rate 6 Minimum Conversion Rate 6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulse with High ENCODE Pulse with Low Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay SNR7 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 21 MHz Analog Input @ 32 MHz SINAD8 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 21 MHz Analog Input @ 32 MHz –2.2 –2.2 –1.0 –3.0 –5.0 +1.5 –3.0 –5.0 Guaranteed ± 0.2 ± 1.0 ± 0.1 –1.0 ± 2.0 ± 0.5 ± 1.0 ± 1.0 Bits Full 25°C Full Full 25°C Full 25°C Max Min Offset Error Channel Match Gain Error1 12 1 2, 3 1, 2, 3 1 2, 3 1 2 3 Unit +2.2 +2.2 +1.0 +1.0 +5.0 +1.5 +3.0 +5.0 ± 0.5 ± 1.0 12 12 99 198 –2– V V 101 202 7.0 0.4 65 20 12 12 12 12 5.0 5.0 4 5, 6 4 5, 6 70 69 69 68 4 5, 6 4 5, 6 69 68.5 66.5 66 1.5 250 0.3 7.7 7.7 7.5 11.5 % FS % FS % FS % FS % FS % FS % FS % FS 500 9.5 9.5 Ω Ω pF MHz MSPS MSPS ns ps ps rms ns ns ns ns 72 72 71 71 70 70 69 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 72 72 70.5 70 69 63 61 dBFS dBFS dBFS dBFS dBFS dBFS dBFS REV. 0 AD13465 Temp Test Level 25°C 25°C Full 25°C Full 25°C Full V I II I II V V SINGLE-ENDED ANALOG INPUT Pass Band Ripple to 10 MHz Pass Band Ripple to 25 MHz 25°C 25°C DIFFERENTIAL ANALOG INPUT Pass Band Ripple to 10 MHz Pass Band Ripple to 25 MHz Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Mil SubGroup Min 4 5, 6 4 5, 6 80 78 70 69 AD13465AZ/BZ Typ Max Unit 9 85 86 84 76 74 63 62 dBFS dBFS dBFS dBFS dBFS dBFS dBFS V V 0.05 0.1 dB dB 25°C 25°C V V 0.3 0.82 dB dB TWO-TONE IMD REJECTION 10 fIN = 9.1 MHz and 10.1 MHz f1 and f2 are –7 dB fIN = 19.1 MHz and 20.7 MHz f1 and f2 are –7 dB 25°C Full 25°C I II V 4 5, 6 82 80 72 dBc CHANNEL-TO-CHANNEL ISOLATION 11 25°C IV 12 TRANSIENT RESPONSE 25°C V Analog Input @ 21 MHz Analog Input @ 32 MHz DIGITAL OUTPUTS Logic Compatibility DVCC = 3.3 V Logic 1 Voltage Logic 0 Voltage DVCC = 5 V Logic 1 Voltage Logic 0 Voltage Output Coding 77.5 76.5 dBc 90 dB 15.3 ns 12 POWER SUPPLY AVCC Supply Voltage13 I (AVCC) Current AVEE Supply Voltage13 I (AVEE) Current DVCC Supply Voltage13 I (DVCC) Current (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) CMOS Full Full I I Full Full V V Full Full Full Full Full Full Full Full Full VI V VI V VI V I I V 1, 2, 3 1, 2, 3 2.5 DVCC – 0.2 0.2 0.5 DVCC – 0.3 0.35 Two’s Complement 4.85 –5.25 3.135 1, 2, 3 1, 2, 3 5.0 270 –5.0 38 3.3 34 369 3.57 0.02 V V V V 5.25 308 –4.75 49 3.465 46 403 3.9 V mA V mA V mA mA W % FSR/ % VS NOTES 1 Gain tests are performed on AMP-IN-X-1 input voltage range. 2 Input capacitance spec. combines AD8037 capacitance and ceramic package capacitance. 3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180 ° out of phase). For single ended input: +IN = 2 V p-p and –IN = GND. 5 All AC specifications tested by driving ENCODE and ENCODE differentially. AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND. 6 Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale. 8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale. 9 Analog Input signal power at –1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 11 Channel-to-channel isolation tested with A Channel grounded and a full-scale signal applied to B Channel. 12 Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 13 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice. REV. 0 –3– AD13465 ABSOLUTE MAXIMUM RATINGS 1 TEST LEVEL ELECTRICAL AVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V AVEE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0 V DVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . VEE to VCC Analog Input Current . . . . . . . . . . . . . . –10 mA to +10 mA Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to VCC ENCODE, ENCODE Differential Voltage . . . . . . . . . . 4 V Digital Output Current . . . . . . . . . . . . –10 mA to +10 mA ENVIRONMENTAL2 Operating Temperature (Case) . . . . . . . . . –40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . 175°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . 300°C Storage Temperature Range (Ambient) . . –65°C to +150°C I 100% Production Tested. II 100% Production Tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III Sample Tested Only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at temperature at 25°C: sample tested at temperature extremes. NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for “ES” package: θJC, 2.2°C/W; θJA, 24.3°C/W. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range (Case) Package Description Package Option AD13465AZ AD13465AF –25°C to +85°C –25°C to +85°C ES-68C ES-68C 5962-0150601HXA AD13465/PCB –40°C to +85°C 25°C 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD13465AZ –4– ES-68C REV. 0 AD13465 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1, 35 2, 3, 9, 10, 13, 16 SHIELD AGNDA 4 5 6 7 8 11 12 14 15 17 18–25, 28–33 26, 27 34 36 37–42, 45–52 43, 44 53 54, 57, 60, 61, 67, 68 55 56 58 59 62 63 64 65 66 A–IN A+IN AMP-OUT-A AMP-IN-A-1 AMP-IN-A-2 AVEEA AVCCA ENCA ENCA DVCCA D0A–D13A DGNDA DROUTA DROUTB D0B–D13B DGNDB DVCCB AGNDB ENCB ENCB AVCCB AVEEB AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B B+IN B–IN Internal Ground Shield Between Channels. A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Inverting Differential Input (Gain = 1). Noninverting Differential Input (Gain = 1). Single-Ended Amplifier Output (Gain = 2). Analog Input for A Side ADC (Nominally ± 0.5 V). Analog Input for A Side ADC (Nominally ± 1.0 V). A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). A Channel Analog Positive Supply Voltage (Nominally 5.0 V). Complement of Encode; Differential Input. Encode Input; Conversion Initiated on Rising Edge. A Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V). Digital Outputs for ADC A. D0 (LSB). A Channel Digital Ground. Data Ready A Output. Data Ready B Output. Digital Outputs for ADC B. D0 (LSB). B Channel Digital Ground. B Channel Digital Positive Supply Voltage (Nominally 5.0 V/3.3 V). B Channel Analog Ground. Encode Input; Conversion Initiated on Rising Edge. Complement of Encode; Differential Input. B Channel Analog Positive Supply Voltage (Nominally 5.0 V). B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). Analog Input for B Side ADC (Nominally ± 1.0 V). Analog Input for B Side ADC (Nominally ± 0.5 V). Single-Ended Amplifier Output (Gain = 2). Noninverting Differential Input (Gain = 1). Inverting Differential Input (Gain = 1). AGNDA SHIELD AGNDB 4 2 1 68 67 66 65 64 63 62 61 5 3 AGNDB A–IN AGNDA 6 AMP-IN-B-1 AMP-IN-B-2 AMP-OUT-A A+IN 7 B+IN AMP-OUT-B AMP-IN-A-1 8 B–IN AMP-IN-A-2 9 AGNDA 10 AVEEA 11 AGNDB AGNDA PIN CONFIGURATION 59 AGNDB AVEEB AVCCA 12 AGNDA 13 ENCA 14 58 AVCCB 57 56 AGNDB ENCB ENCA 15 AGNDA 16 DVCCA 17 55 ENCB 54 60 PIN 1 IDENTIFIER D0A(LSB) 18 D1A 19 AD13465 53 AGNDB DVCCB TOP VIEW (Not to Scale) 52 D13B(MSB) 51 D2A 20 50 D12B D11B D3A 21 49 D10B D4A 22 48 D9B D5A 23 47 D8B D6A 24 46 D7B D7A 25 DGNDA 26 45 D6B DGNDB 44 REV. 0 –5– DGNDB D5B D3B D4B D2B D1B DROUTB D0B(LSB) SHIELD DROUTA D12A D13A(MSB) D9A D10A D11A D8A DGNDA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AD13465 –Typical Performance Characteristics 0 0 ENCODE = 65MSPS AIN = 5MHz(–1dBFS) SNR = 72.12dBFS SFDR = 86.05dBc –10 –20 –20 –30 –40 –40 –50 –50 –60 –60 dB dB –30 ENCODE = 65MSPS AIN = 9.9MHz(–1dBFS) SNR = 72.09dBFS SFDR = 84.04dBc –10 –70 –80 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 0 FREQUENCY – MHz FREQUENCY – MHz TPC 1. Single Tone @ 5 MHz TPC 4. Single Tone @ 9.9 MHz 0 0 ENCODE = 65MSPS AIN = 21MHz(–1dBFS) SNR = 71.74dBFS SFDR = 73.07dBc –10 –20 ENCODE = 65MSPS AIN = 32MHz(–1dBFS) SNR = 70.8dBFS SFDR = 62.57dBc –10 –20 –30 –40 –40 –50 –50 –60 –60 dB dB –30 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY – MHz FREQUENCY – MHz TPC 2. Single Tone @ 21 MHz TPC 5. Single Tone @ 32 MHz 0 0 ENCODE = 65MSPS AIN = 9.1MHz AND 10.1MHz(–1dBFS) SFDR = 85.01dBc –10 –20 ENCODE = 65MSPS AIN = 19MHz AND 20.7MHz(–1dBFS) SNR = 70.8dBFS SFDR = 75.40dBc –10 –20 –30 –30 –40 –40 –50 –50 –60 –60 dB dB 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY – MHz FREQUENCY – MHz TPC 3. Two-Tone @ 9.1 MHz/10.1 MHz TPC 6. Two-Tone @ 19 MHz/20.7 MHz –6– REV. 0 AD13465 3.0 3.0 ENCODE = 65MSPS DNL MAX = 0.632 CODES DNL MIN = –0.52 CODES 2.5 ENCODE = 65MSPS INL MAX = 1.18 CODES INL MIN = –1.06 CODES 2.0 2.0 1.0 LSB LSB 1.5 1.0 0 0.5 –1.0 0 –2.0 –0.5 –1.0 –3.0 0 2048 4096 6144 8192 0 10240 12288 14336 16384 TPC 7. Differential Nonlinearity 2048 4096 6144 8192 TPC 10. Integral Nonlinearity 0 0 ENCODE = 40MSPS AIN = 5MHz(–1dBFS) SNR = 72dBFS SFDR = 87.57dBc –10 –1 –20 ENCODE = 65MSPS ROLLOFF = –0.18dB –30 –3 –40 –4 –50 dB dBFS –2 10240 12288 14336 16384 –5 –6 –60 –70 –80 –90 –7 –100 –8 –110 –9 –120 –10 1.0 3.5 6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 –130 0 26.0 2.5 5.0 TPC 8. Passband Ripple to 25 MHz –30 –10 –20 –30 –40 –40 –50 –50 –60 –60 dB dB 12.5 15.0 17.5 20.0 17.5 20.0 0 ENCODE = 40MSPS AIN = 9.1MHz AND 10.1MHz(–1dBFS) SFDR = 84.16dBc –20 –70 ENCODE = 40MSPS AIN = 18MHz(–1dBFS) SNR = 71.5dBFS SFDR = 78.7dBc –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 –130 0 20.0 FREQUENCY – MHz 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY – MHz TPC 9. Two-Tone @ 9.1 MHz/10.1 MHz REV. 0 10.0 TPC 11. Single Tone @ 5 MHz 0 –10 –130 0 7.5 FREQUENCY – MHz FREQUENCY – MHz TPC 12. Single Tone @ 18 MHz –7– AD13465 DEFINITION OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Maximum Conversion Rate The encode rate at which parametric testing is performed. Aperture Delay Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE command and the instant at which the analog input is sampled. The delay between a differential crossing of ENCODE and ENCODE command and the time when all output data bits are within valid logic levels. Aperture Uncertainty (Jitter) Overvoltage Recovery Time The sample-to-sample variation in aperture delay. The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) Differential Analog Input Voltage Range The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. May be reported in dB (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dB (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable encode duty cycle. Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Transient Response Harmonic Distortion The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity Two-Tone Intermodulation Distortion Rejection The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. tA N+3 N AIN N+1 N+2 t ENC ENC, ENC t ENCH N N+4 t ENCL N+2 N+1 N+3 N+4 t E_DR D[13:0] N–3 N–2 t OD N–1 N DRY Figure 1. Timing Diagram –8– REV. 0 AD13465 THEORY OF OPERATION AMP-IN-X-1 100⍀ AMP-IN-X-2 The AD13465 is a high-dynamic range, 14-bit, 65 MHz pipeline delay (three pipelines) analog-to-digital converter. The custom analog input section provides input ranges of 1 V p-p and 2 V p-p, and input impedance configurations of 50 Ω, 100 Ω, and 200 Ω. TO AD8037 100⍀ Figure 2. Single-Ended Input Stage The AD13465 employs four monolithic ADI components per channel (AD8037, AD8138, AD8031, and AD6644), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter. LOADS AVCC AVCC AVCC AVCC 10k⍀ 10k⍀ ENCODE ENCODE 10k⍀ 10k⍀ LOADS Figure 3. ENCODE Inputs In the single-ended input configuration, the input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full-scale signal of ± 0.5 V or ± 1.0 V by choosing the proper input terminal for the application. The result of the resistor divider is to apply a full-scale input approximately 0.4 V to the noninverting input of the internal AD8037 amplifier. The AD13465 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifier’s inputs and outputs. The AD8037 amplifier provides a high-input impedance and gain for driving the AD8138 in a single-ended-to-differential amplifier configuration. The AD8138 has a –3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the AD6644 maximizing the performance of the device. DVCC CURRENT MIRROR DVCC VREF DR OUT CURRENT MIRROR The AD8031 provides the buffer for the internal reference analog-to-digital converter. The internal reference voltage of the AD6644 is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common mode input on the AD8138. This reference voltage sets the output common mode on the AD8138 at 2.4 V, which is the midsupply level for the ADC. The AD6644 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold. Figure 4. Digital Output Stage DVCC The AD6644 digital outputs drive 100 Ω series resistors (Figure 5.) The result is a 14-bit parallel digital CMOS-compatible word, coded as two’s complement. CURRENT MIRROR USING THE SINGLE-ENDED INPUT DVCC VREF 100⍀ D0–D13 CURRENT MIRROR Figure 5. Digital Output Stage REV. 0 The AD13465 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. The standard inputs are ± 0.5 V and ± 1.0 V. The user can select the input impedance of the AD13465 on any input by using the other inputs as alternate locations for the GND. The following chart summarizes the impedance options available at each input location. AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open. AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND. AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open. Each channel has two analog inputs AMP-IN-A-1 and AMPIN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1 –9– AD13465 or AMP-IN-B-1 when an input of ±5 V full scale is desired. Use AMP-IN-A-2 or AMP-IN-B-2 when ± 1 V full scale is desired. Each channel has an AMP-OUT that must be tied to either a noninverting or inverting input of a differential amplifier with the remaining input grounded. For example, Side A, AMPOUT-A (Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 4) tied to ground for noninverting operation or AMP-OUT-A (Pin 6) tied to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting operation. If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola. VT 0.1F ENCODE ECL/ PECL AD13465 0.1F ENCODE USING THE DIFFERENTIAL INPUT APPLYING THE AD13465 Encoding the AD13465 The AD13465 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. Maintaining 14-bit accuracy at 65 MSPS places a premium on encode clock phase noise. SNR performance can easily degrade 3 dB to 4 dB with 32 MHz input signals when using a high-jitter clock source. See Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance,” for complete details. For optimum performance, the AD13465 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. VT Figure 7. Differential ECL for Encode Jitter Consideration The signal-to-noise ratio (SNR) for any ADC can be predicted. When normalized to ADC codes, the equation below, accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. 1/ 2 2 V (1 + ε SNR = –20 × log N + (2 × π × f ANALOG × t J RMS )2 + NOISEN RMS 2 2 fANALOG = analog input frequency tJ RMS = rms jitter of the encode (rms sum of encode source and internal encode circuitry) ε = average DNL of the ADC (typically 0.50 LSB) N = Number of bits in the ADC VNOISE RMS = V rms noise referred to the analog input of the ADC (typically 5 LSB) For a 14-bit analog-to-digital converter like the AD13465, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD13465 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance.” Shown below is one preferred method for clocking the AD13465. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD13465 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13465, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limited resistor (typically 100 Ω) is placed in the series with the primary. 71 70 68 67 0.1mF 100 ⍀ AIN = 9.9MHz 66 AIN = 21MHz 65 64 63 62 61 60 CLOCK SOURCE AIN = 5MHz 69 SNR – –dBFS Each channel of the AD13465 was designed with two optional differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs provide system designers with the ability to bypass the AD8037 amplifier and drive the AD8138 directly. The AD8138 differential ADC driver can be deployed in either a single-ended or differential input configuration. The differential analog inputs have a nominal input impedance of 620 Ω and nominal fullscale input range of 1.2 V p-p. The AD8138 amplifier drives a differential filter and the custom analog-to-digital converter. The differential input configuration provides the lowest even-order harmonics and signal-to-noise (SNR) performance improvement of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in the layout of the differential input signal paths. The differential input transmission line characteristics are matched and balanced. Equal attention to system level signal paths must be provided in order to realize significant performance improvements. AIN = 32MHz 59 T1-4T ENCODE 58 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.0 AD13465 CLOCK JITTER – ps ENCODE HSMS2812 DIODES Figure 8. SNR vs. Jitter Figure 6. Crystal Clock Oscillator—Differential Encode –10– REV. 0 AD13465 Power Supplies LAYOUT INFORMATION Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be received by the AD13465. Each of the power supply pins should be decoupled as closely to the package as possible, using 0.1 µF chip capacitors. The schematic of the evaluation board (Figure 10) represents a typical implementation of the AD13465. The pinout of the AD13465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. The AD13465 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within +5% and –3% of 5 V. The AD13465 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs. Output Loading Care must be taken when designing the data receivers for the AD13465. The digital outputs drive an internal series resistor (e.g., 100 Ω) followed by a gate like 75LCX574. To minimize capacitive loading, there should be only one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 10. The digital outputs of the AD13465 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current per bit will flow in or out of the device. A fullscale transition can cause up to 140 mA (14 bits × 10 mA/bit) of transient current through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD13465. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. EVALUATION BOARD The AD13465 evaluation board (Figure 9) is designed to provide optimal performance for evaluation of the AD13465 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD13465. The board requires an analog input signal, encode clock, and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and out clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD13465. The digital outputs of the AD13465 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required. Figure 9. Evaluation Board Mechanical Layout REV. 0 –11– AD13465 Bill of Materials List for Evaluation Board Qty Component Name Ref/Des 2 1 2 10 2 4 6 74CLX16373MTD AD13465AZ ADP3330 BJACK BRES0805 BRES0805 RES2 36 RES2 28 CAP2 2 2 6 4 2 8 CAP2 H40DM IND2 MC10EL16 MC100ELT23 POLCAP2 4 12 4 4 1 RES2 SMA Stand-Off Screws PCB U7, U8 U1 U5, U6 BJ1-BJ10 R41, R53 R38, R39, R55, R56 R1, R2, R5, R7, R8 R54 R3, R4, R6, R9 R12–R15, R19–R28, R31–R36, R37, R42–R46, R51, R52 C1, C2, C5–C10, C12, C16–C18 C20–C26, C28 C30–C38 C13, C27 J1, J2 L1–L6 U2, U3, U9, U11 U4, U10 C3, C4, C11, C14, C15, C19, C29, C30 R47–R50 J3–J14 Value Description Manufacturing Part No. 25 Ω 33 kΩ 50 Ω Latch AD13465AZ Regulator Banana Jacks 0805 SM Resistor 0805 SM Resistor 0805 SM Resistor 74LCX1673MTD (Fairchild) AD13465AZ ADP3330ART-3.3RL7 108-0740-001 (Johnson Components) EFJ-6GEYJ240V EFJ-6GEYJ333V EFJ-6GEYJ333V 100 Ω 0805 SM Resistor EFJ-6GEYJ333V 0.1 µF 0805 SM Resistor GRM 40X7R104K025BL 0.47 µF 0805 SM Resistor 2 × 20 40-Pin Male Connector SM Inductor Clock Drivers ECL/TTL Clock Drivers Tantalum Polar Caps VJ1206U474MFXMB TSW-120-08-G-D 2743019447 MC1016EP16D SY100ELT23L T491C106M016A57280 0805 SM Resistor SMA Connectors Stand-Off Screws (Stand-Off) AD13465 Eval Board (Rev B) ERJ-6GEY OR 00V 142-0701-201 313-2477-016 (Johnson Components) MPMS 004 0005 PH (Building Fasteners) GS03361 47 Ω 10 µF 0Ω –12– REV. 0 AD13465 J13 SMA E68 AGNDA J9 SMA J6 SMA E67 AGNDB E66 J8 SMA LIDA J3 SMA E50 E83 E81 E79 E78 62 61 AGNDB AMP IN B 2 AMP OUT B AMP IN B 1 63 64 E84 B+IN 65 E82 B–IN 66 E80 67 AGNDB 68 AGNDB 1 SHIELD AGNDA AGNDA 2 E76 E75 3 E73 AMP OUT A A–IN 7 8 D12B D11B D3A D10B DRAOUT DGNDB DGNDB –5VAB C33 0.1F AGNDB +5VAB C17 C38 0.1F 0.1F AGNDB 59 58 57 56 55 54 AGNDB ENCB ENCB AGNDB AGNDB OUT 3.3VDB 53 52 51 50 49 48 47 46 45 44 C18 0.1F D13B C37 0.1F D12B D11B DGNDB D10B D9B D8B D7B D6B DGNDB 43 D5B 42 D6B 60 DGNDB D4B D5B D3B 41 D3B 40 39 D2B D1B 38 37 DRBOUT D0B DGNDA 36 DGNDA 35 D7A D4B D7B D2B D6A D1B D8B D0B(LSBB) D9B D5A SHIELD D4A DRAOUT 26 D1A 27 DGNDA 25 D13B(MSB) D2A D13A(MSBA) D7A 24 AD13465 D0A(LSB) 34 D6A 23 +3.3VDB D13A D5A 22 U1 +3VDA D12A D4A 21 AGNDB 33 D3A AGNDA D12A DGNDA 20 ENCB D11A D1A D2A 19 –5.2VAB ENCA 32 D0A 18 AGNDB ENCBB D11A 17 C10 0.1F AGNDB ENCAB D9A C36 0.1F 16 AGNDB AGNDB AGNDB 30 AGNDA OUT 3.3VDA 15 E86 AGNDA D9A ENCA AGNDA AGNDB E52 E85 +5VAB D8A ENCA 14 AGNDB J7 SMA E54 +5VAA 29 AGNDA 13 –5VAA D8A 12 DGNDA 11 AGNDA 28 AGNDA 10 AMP IN A 1 AGNDA –5VAA C9 0.1F AGNDA +5VAA C34 C35 0.1F 0.1F AMP IN A 2 AGNDA 9 AGNDA 4 E77 6 E72 AGNDA E70 A+IN E49 E69 D10A AGNDA 5 E74 E71 E53 E51 31 J4 SMA D10A AGNDA J14 SMA DRBOUT E56 E55 LIDB E65 E48 DGNDA BJ10 1 C29 10F L1 U7 C62 0.1F DGNDB +3VAA 47⍀ ⴞ20% @100MHz BJ6 47⍀ ⴞ20% @100MHz +3VDA E40 DUT 3.3VDA 1 C3 10F –5VAA 47⍀ BJ2 ⴞ20%@100MHz +5VAA L3 U1 C20 0.1F –5VAA L5 U1 C32 0.1F AGNDA AGNDA AGNDA 1 C11 10F AGNDA DGNDA 47⍀ ⴞ20% @100MHz +3VDB BJ9 1 C30 10F +5VAB 47⍀ ⴞ20%@100MHz BJ5 DUT 3.3VDB U8 C16 0.1F DGNDB L2 1 C4 10F AGNDB –5VAB 47⍀ ⴞ20%@100MHz BJ1 +5VAB L4 U1 C21 0.1F AGNDB Figure 10a. Evaluation Board REV. 0 –13– 1 C19 10F AGNDB –5VAB L6 U1 C31 0.1F AGNDB AD13465 U8 25 26 R48 0⍀ DGNDA (LSB) D0A DGNDA D1A DUT 3.3VDA D2A D3A DGNDA D4A D5A D6A D7A DGNDA D8A D9A DUT 3.3VDA D10A D11A DGNDA D12A (MSB) D13A R7 50⍀ 27 28 LE2 OE2 115 O15 114 O14 GND GND 113 29 112 30 VCC 31 111 32 110 33 GND 34 19 35 18 36 17 37 16 38 GND 39 15 40 14 41 VCC 42 13 43 12 44 GND 45 11 46 10 47 LE1 48 24 DGNDA R17, DNI 23 22 21 O13 20 O12 19 VCC 18 O11 17 O10 16 GND 15 O9 14 O8 13 O7 12 O6 11 GND 10 O5 9 O4 8 VCC 7 O3 6 O2 5 GND 4 O1 3 O0 2 OE1 1 R18, DNI H40DM J1 F0A F1A R40, DNI R44, DNI DGNDA B0A (LSB) B1A R14, 100⍀ R13, 100⍀ R12, 100⍀ DGNDA B2A B3A R46, 100⍀ R15, 100⍀ R24, 100⍀ R23, 100⍀ B4A B5A B6A B7A B8A B9A DUT 3.3VDA R22, 100⍀ 40 39 38 37 36 35 7 8 9 R5 B6A 50⍀ E61 10 11 E59 E60 12 B5A 13 B4A 14 B3A 15 B2A 16 B1A 17 (LSB) B0A 18 F1A 19 F0A 20 DGNDA 34 33 32 31 30 29 (MSB) B13A B12A C15 10F B11A B10A B9A DGNDA B8A B7A DUT 3.3VDA R45, 100⍀ 1 2 3 4 5 6 3.3VDA DGNDA BUFLATA DRAOUT R47 0⍀ B10A B11A 28 27 26 25 24 23 22 21 R21, 100⍀ DGNDA R20, 100⍀ R19, 100⍀ DGNDA B12A B13A (MSB) DGNDA LATCHA 74LCX16374 E58 U7 25 26 R50 0⍀ DGNDB (LSB) D0B DGNDB D1B DUT 3.3VDB D2B D3B DGNDB D4B D5B D6B D7B DGNDB D8B D9B DUT 3.3VDB D10B D11B DGNDB D12B (MSB) D13B R8 50⍀ 27 28 LE2 OE2 115 O15 114 O14 GND GND 113 29 112 30 VCC 31 111 32 110 33 GND 34 19 35 18 36 17 37 16 38 GND 39 15 40 14 41 VCC 42 13 43 12 44 GND 45 11 46 10 47 LE1 48 LATCHB E57 24 DGNDB R10, DNI 23 22 21 O13 20 O12 19 VCC 18 O11 17 O10 16 GND 15 O9 14 O8 13 O7 12 O6 11 GND 10 O5 9 O4 8 VCC 7 O3 6 O2 5 GND 4 O1 3 O0 2 OE1 1 H40DN J2 R11, DNI F0B F1B 3.3VDB DGNDB R30, DNI R29, DNI B0B (LSB) B1B DUT 3.3VDB R28, 100⍀ DGNDB R27, 100⍀ R26, 100⍀ R12, 100⍀ R9, 100⍀ R25, 100⍀ DGNDB R36, 100⍀ R35, 100⍀ B2B B3B B4B B5B B6B B7B B8B B9B DUT 3.3VDB R34, 100⍀ R33, 100⍀ DGNDB R32, 100⍀ R31, 100⍀ (MSB) B13B B12B C14 10F B11B B10B B9B DGNDB B10B B11B B12B R2 50⍀ E64 E63 B8B B7B B6B E62 BUFLATB DRAOUT R49 0⍀ B5B B4B B3B B2B B1B (LSB) B0B F1B F0B DGNDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DGNDB B13B (MSB) DGNDB 74LCX16374 Figure 10b. Evaluation Board –14– REV. 0 AD13465 5 NR 3 ERR 1 OUT U5 IN +5VAA 5 ADP3330 SD GND 4 AGNDA J5 ENCODE C1 SMA 0.1F AGNDA R1 50⍀ AGNDA R42 100⍀ C13 0.47F 1 2 J12 SMA R41 25⍀ AGNDA D 3 DB 4 VBB C2 0.1F 8 VCC NC Q U2 C7 0.1F 3.3VA 7 BJ4 ENCA 5 VEE AGNDB 1 ENCA 6 QB BJ3 R43 100⍀ MC10EL16 NC = NO CONNECT AGNDA AGNDA 1 C8 0.1F BJ7 DGNDB 1 DGNDB R56 33k⍀ DGNDA R55 33k⍀ AGNDA AGNDA C6 0.47F NC 8 VCC R3 100⍀ 3.3VDA 2 7 D Q U3 6 3 DB QB 4 5 VBB VEE 1 2 3 R4 100⍀ MC10EL16 NC = NO CONNECT DGNDA 4 DGNDA NC VCC D Q0 U4 Q1 DB VBB VEE 8 DGNDA E15 E7 +3.3VDA LATCHA E23 7 6 E19 BUFLATA 5 DGNDA NC = NO CONNECT NR ERR OUT 5 DGNDA 1 GND 4 AGNDB J10 ENCODE SMA AGNDB C22 0.1F R54 50⍀ AGNDB 2 J11 SMA 3 C23 0.1F VCC NC D U11 DB QB 4 VBB R53 25⍀ Q VEE 8 R52 100⍀ C24 0.1F 3.3VB 7 ENCB 5 R51 100⍀ 1 2 NC D 3 DB 4 VBB VCC U9 Q QB VEE 8 7 DGNDB C26 0.1F R37 100⍀ 6 1 2 R6 100⍀ 3 4 MC10EL16 DGNDB NC = NO CONNECT DGNDB NC D VCC U10 DB VBB Q0 Q1 VEE –15– 8 3.3VDA 7 6 5 MC100EPT23 NC = NO CONNECT DGNDB Figure 10c. Evaluation Board REV. 0 AGNDA E38 E29 E1 E36 E14 E45 E3 E37 E30 E2 E35 E13 E46 E4 SO1 SO2 SO3 SO4 SO5 SO6 DGNDB DGNDB 3.3VDB 5 C28 0.1F AGNDA R38 33k⍀ C25 0.47F DGNDB R39 33k⍀ DGNDA ENCB 6 MC10EL16 NC = NO CONNECT AGNDB AGNDB E18 E28 E26 E20 E31 E43 E41 E9 E34 E5 AGNDB C27 0.47F 1 DGNDB E17 E27 E25 E21 E32 E44 E42 E10 E33 E6 U6 SD E8 E47 DGNDA ADP3330 IN +5VAB E16 E12 DGNDB E11 E39 MC100EPT23 5 3 DGNDA 1 DGND C5 0.47F AGNDA 1 BJ8 LATCHB E24 E22 BUFLATB AGNDB AD13465 Figure 11a. Top Silk Figure 11b. Top Layer –16– REV. 0 AD13465 Figure 11c. GND1 Figure 11d. GND2 REV. 0 –17– AD13465 Figure 11e. Bottom Silk Figure 11f. Bottom Layer –18– REV. 0 AD13465 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier (ES-68C) 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.235 (5.97) MAX 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 60 44 61 1.070 (27.18) MIN 43 PIN 1 0.800 (20.32) BSC 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) TOP VIEW (PINS DOWN) 9 27 10 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 26 DETAIL A 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.175 (4.45) MAX 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.010 (0.254) 30ⴗ 0.050 (1.27) 0.020 (0.508) DETAIL A ROTATED 90ⴗ CCW REV. 0 –19– TOE DOWN ANGLE 0–8 DEGREES AD13465 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C01973–2.5–4/01(0) 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar (ES-68C) 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.350 (8.89) TYP 0.015 (0.3) ⴛ 45ⴗ 3 PLS PIN 1 2.000 (8.89) TYP 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) TOP VIEW (PINS DOWN) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.040 (1.02) ⴛ 45ⴗ 0.040 (1.02) R TYP 0.800 (20.32) BSC 0.175 (4.45) MAX 0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.010 (0.254) 30ⴗ 0.050 (1.27) 0.020 (0.508) PRINTED IN U.S.A. DETAIL A –20– REV. 0