Ordering number : ENN6124 CMOS IC LC73815M FSK 1200 Baud Modem and DTMF Receiver Overview The LC73815M is a telephone IC that integrates on a single chip both an FSK modem, which receives pre-call reporting services such as caller ID and performs other data send/receive functions, and a DTMF receiver circuit that can handle remote control functions for telephone answering machine applications. • Digital guard timer circuits for the DTMF signal detection signal pins • Operating voltage range: 4.5 to 5.5 V • Low-power mode that can contribute to energy savings • 36-pin package (MFP-36S) Package Dimensions Applications unit: mm Pre-call reporting services, such as Caller ID, reception, other data send/receive functions, and remote control of telephone answering machine applications. 3129-MFP36S [LC73815M] 19 36 18 0.25 2.25 2.5max 15.3 0.65 7.9 1 0.4 0.8 0.85 0.1 • FSK modem (1200 bps) • Circuit that automatically generates the start and stop bits used during FSK modulation • Circuit that automatically generates the continuous mark signal at the start of transmission in FSK modulation mode • Circuit that automatically inserts the idle bits (5 or more bits) used in FSK modulation mode • Built-in clock synchronous I/O shift register • Detection of all 16 DTMF signals 9.2 10.5 Features SANYO: MFP36S Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max –0.3 to +7.0 V Maximum input voltage VIN max –0.3 to VDD + 0.3 V Maximum input current IIN max Allowable power dissipation Pd max Ta ≤ 70°C –10 to +10 mA 250 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D2200RM (OT) No. 6124-1/17 LC73815M Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Supply voltage Symbol Conditions Ratings min VDD typ 4.5 IDD(OP1) VDD = 5.0 V, when the DTMF receiver is used. Operating current drain Quiescent current Oscillator frequency Unit max 5.0 5.5 V 5.5 10 mA IDD(OP2) VDD = 5.0 V, during FSK reception 7.5 15 mA IDD(OP3) VDD = 5.0 V, during FSK transmission 7.5 15 mA 3.579545 3.583125 IDD(ST) RES pin = low 10 3.5757965 fOSC µA MHz DC Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V Parameter High-level input voltage Low-level input voltage Input leakage current Symbol Conditions Ratings min typ Unit max VIH Pins other than ACK and RES 0.7 VDD VIHS The ACK and RES input pins 0.8 VDD VIL Pins other than ACK and RES 0.3 VDD VILS The ACK and RES input pins 0.2 VDD V VIH VIN = VDD 10 µA –0.4 mA IIL VIN = GND High-level output current IOH VOUT = VDD – 0.4 V Low-level output current IOL VOUT = 0.4 V V V –10 µA –0.8 1.0 V 2.5 mA AC Electrical Characteristics 1 (FSK reception/transmission) at Ta = 25°C, VDD = 5 V, VSS = 0 V, fOSC = 3.579545 MHz Parameter Symbol Conditions Ratings min typ Input signal detection level FSK reception +3 dBm Reception data transmission speed FSK 1188 1200 1212 baud FSK (Mark) 1180 1250 1320 Hz FSK (Space) 2070 2150 2280 Reception frequency –38 Unit max 1 fACK Shift register data shift speed External oscillator input tCKL 500 tCKH 500 ns EXTOI 0.5 Vrms B/V = H FSK transmission frequency Hz MHz FSK (Mark) 1200 (BELL202) FSK (Space) B/V = L FSK (Mark) (V.23) FSK (Space) FSK output amplitude ns Hz 2204 Hz 1300 Hz 2101 0.5 Transfer rate Hz 0.8 Vp-p 1200 bps FSK modulation delay time tDDEM See the timing chart. 0 0.83 Data output setup time tSDATA See the timing chart. 0 0.42 0.83 ms ms DR output setup time tSDR See the timing chart. 2.2 3.3 µs ACK - DATA setup time tSCKD See the timing chart. 0 300 ns ACK - DR setup time tSCKDR See the timing chart. 1.1 9.0 µs Conditions: For the dBm ratings, 0 dBm is defined to be a 1 mW output into a 600 Ω load. No. 6124-2/17 LC73815M AC Electrical Characteristics 2 (DTMF reception) at Ta = 25°C, VDD = 5 V, VSS = 0 V, fOSC = 3.579545 MHz Parameter Symbol Conditions Input signal detection level 1, 2, 3, 5, 6, 9 Allowable twist 2, 3, 6, 9, 11 Frequency detection band 2, 3, 5, 9 Ratings min typ –45 max +0 Unit dBm ±10 dB –16 dB dB ±1.5% ±2 Hz Frequency non-detection band 2, 3, 5 Allowable third tone 2, 3, 4, 5, 9, 10 ±3.5 % Allowable dial tone 2, 3, 4, 5, 8, 9, 10 22 Allowable noise 2, 3, 4, 5, 7, 9, 10 –12 dB Input signal invalid time tREC See the timing chart. Input signal valid time tREC See the timing chart. Interdigit pause invalid time tDO See the timing chart. Interdigit pause valid time tID See the timing chart. (Present) tGDP See the timing chart. 30 (Absent) tGDA See the timing chart. 20 Input signal (Present) tDP See the timing chart. 3 20 ms detection time (Absent) tDA See the timing chart. 0.5 20 ms Guard time Conditions 20 45 ms ms 20 40 ms ms ms ms 1. The 0 dBm level is defined to be a 1 mW output into a 600 Ω load. 2. All combinations of the 16 DTMF signals. 3. A 40 ms DTMF signal period, and a 40 ms pause period 4. The nominal frequencies are used for DTMF signals. 5. The signal levels of the low group and high group signals are identical. 6. The tolerance for DTMF signal frequency is within ±1.5% or ±2 Hz. 7. Gaussian noise with a band of 0 to 3 kHz 8. Dial tone pair of 350 and 440 Hz 9. The error ratio is under 1 error in 10,000 operations. 10. Referenced to the frequency component with the lowest level in the DTMF signal. 11. Twist: the ratio of the high group tone level to the low group tone level Note: This IC contains a Switched Capacitor Filter (SCF) circuit on chip. Since the internal SCF clock frequency is OSC/56 (= 63.92 kHz), a power supply related noise whose frequency is OSC/56 multiplied by some integer ±3 kHz will prevent the ratings shown above from being achieved. Therefore, care must be taken for the power supply related noise. Input Amplifier Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V, fOSC = 3.579545 MHz Parameter Symbol Input offset voltage VIO Input offset current IIO Conditions Ratings min typ –25 VSS ≤ VIN ≤ VDD +25 Unit mV ±100 nA 60 dB dB Power supply rejection ratio PSRR Common-mode rejection ratio CMRR 60 AO 65 dB 0 dB bandwidth fT 1.5 MHz Maximum output voltage VO VDD – 0.5 Vp-p Allowable load capacitance CL 100 pF Allowable load resistance RL 50 kΩ 3.0 Vp-p Open loop voltage gain Common-mode input voltage range VCM 1 kHz max RL ≥ 100 kΩ No load No. 6124-3/17 LC73815M Pin Functions Pin No. Pin I/O 1 IN+ I 2 IN– I Differential operational amplifier inverting input 3 GS O Differential operational amplifier output 4 AGND O IC internal analog ground output 5 NC 6 FSKOUT O FSK signal output. This is an npn transistor emitter-follower output. 7 AGCO O Connect to pin 8 through a capacitor. Make no other connections to this pin. 8 FSKIN I Connect to pin 7 through a capacitor. Make no other connections to this pin. 9 NC 10 AGND I IC internal analog ground input 11 NC 12 TESTI 13 B/V Function Differential operational amplifier noninverting input I IC test input. This pin must be tied low during normal operation. I Transmission FSK frequency switching input (Bell 202, V.23) High: Bell 202, Low: V.23 14 NC 15 OSCIN I Connect a 3.579545 MHz oscillator element between these pins. An external 3.579545 MHz may also be supplied. 16 OSCOUT O (Consult oscillator element manufacturers concerning the combination of their products with this IC.) 17 NC I Power supply. Connect a capacitor of at least 0.1 µF between this pin and GND. 18 VSS 19 VDD Ground 20 NC 21 S/R I FSK send/receive mode switching input. High: Send, Low: Receive. 22 F/D I FSK modem/DTMF receiver operating mode switching input. High: FSK modem, Low DTMF receiver. 23 NC 24 DATA I/O 25 ACK I Synchronization clock input for serial data readout and write. Serial output of the FSK or DTMF received data in synchronization with the ACK input pin. Also used for serial input of FSK transmission data. 26 EST/DR O In DTMF receiver mode (EST), a high level indicates the presence of a valid DTMF signal. Monitor this pin (or the STD pin), and, after an appropriate wait period has passed, read out the data by applying four pulses to the ACK pin. Note that the received DTMF data is latched internally to the IC on the rising edge of this pin. In FSK reception mode (DR), this pin outputs a high level when the received data is valid, and goes low after the received data has been read out by applying pulse inputs to the ACK pin. In FSK transmission mode (DR), this pin indicates the input ready state for transmission data. A high level indicates that the IC is ready to accept the input of transmission data. 27 STD/DR O In DTMF receiver mode (STD), a high level indicates the presence of a valid DTMF signal. The rise of this signal occurs later than that of the EST signal. However, this signal is not sensitive to burst waveforms. In FSK mode, this pin functions identically to pin 26. 28 RDO O FSK demodulated signal output 29 RES I Reset input. Apply a low level to this pin when power is first applied and after low-power mode. At least 1 µs of low-level input is required for the reset operation. 30 DRCNT I This input controls DR during FSK reception. DR is invalid if this input is high in FSK reception mode. If this pin is low (note that it is pulled down internally) DR is enabled. This pin also functions to select continuous mark signal generation at the start of transmission mode in FSK transmission mode. Low: If the S/R pin is high, continuous mark signals are generated automatically. FSK data will be output following the continuous mark signals generated after the CPU inputs another FSK data to this pin. High: FSK is not output until the CPU inputs the next FSK data, even if the S/R pin is set high. O IC test output pin O IC test output pin 31 TEST01 32, 33 NC 34 TEST02 35, 36 NC No. 6124-4/17 TESTI FSKIN OSCIN Test input circuit AGC Vref circuit OSCOUT Timing generator Anti-aliasing filter Bias circuit VSS Dial tone filter B/V FSK modulator circuit FSK demodulator circuit Low group bandpass filter High group bandpass filter FSK data determination circuit Low-frequency group detection circuit High-frequency group detection circuit Signal discrimination circuit AGCOUT GS IN– IN+ AGNDO AGNDI RES VDD Output signal control circuit Test output circuit DRCNT A12311 FSKOUT RDO S/R F/D DATA ACK EST/DR STD/DR TESTO2 TESTO1 LC73815M Block Diagram I/O control circuit Code comparator circuit No. 6124-5/17 LC73815M Timing Chart (DTMF mode) Timing chart for the normal state (when DTMF signal #n and #n+1 have been input.) INPUT #n #n+1 tDP tDA EST tGDP tGDA STD ACK >20 µs #n DATA LSB #n+1 MSB LSB MSB A12312 When a DTMF signal (#n) is separated into two events due to a burst waveform or other problem. tDO INPUT #n #n #n+1 EST STD ACK #n DATA LSB #n MSB LSB #n+1 MSB LSB MSB A12313 No. 6124-6/17 LC73815M When a pseudo-DTMF signal consisting of noise (#n + α) is input. tREC #n INPUT #n+1 tREC #n+α EST STD ACK #n DATA #n+α #n+1 A12314 When the output data is incorrect due to displacement of the input clock tID INPUT #n #n+1 #n+2 EST STD ACK #n DATA LSB #n+2 MSB LSB MSB A12315 Note: The output data is output from the DATA pin in response to four pulses applied as a set to the ACK pin. The output data are composed of four ACK pulses.There must be a wait time of at least 20 µs between the last of these 4 ACK pulses and the next ACK pulse. No. 6124-7/17 LC73815M Timing Chart (FSK mode reception) Parity RDO b7 Start P 1 0 b1 b2 b3 b4 b5 b6 b7 P 1 0 b1 b2 b3 b4 b5 b6 b7 p 1 Stop DR ACK DATA b1 RDO P b2 b3 b4 b5 b6 b7 P b1 STOP b2 b3 b4 b5 b6 b7 START P b1 b2 tSDATA RDO tSDR DATA b1 b2 tCKL tCKH ACK fACK DR DATA b5 b6 b7 P tSCKD tSCKDR ACK A12316 No. 6124-8/17 LC73815M FSK STOP START b1n b2n b3n b4n b5n b6n b7n STOP START b1n+1 b2n+1 b3n+1 b3n+1 b4n+1 b5n+1 Pn TDDEM RDO STOP START b1n b2n b3n b4n b5n b6n b7n Pn STOP START b1n+1 b2n+1 b3n+1 b3n+1 b4n+1 DR ACK DATA b1n-1 b2n-1 b3n-1 b4n-1 b5n-1 b6n-1 b7n-1 Pn-1 b1n b2n b3n b4n b5n b6n A12317 FSK Channel seizure signal mark signal 01010101010101010101 1111111111111111111 Message data RESET OSCO RDO 0101010101010101--- 1111111111111111--- Message data invalid data Invalid data DR ACK A12318 No. 6124-9/17 LC73815M Timing Chart (FSK mode transmission) DRCNT S/R ACK DATA D0 to D7 DR Start bit Idling FSK D0 D1 D2 D3 D4 D5 D6 D7 Idling Start bit A12319 DRCNT S/R ACK #1 DATA #2 #3 #4 DR Idling Stop bit Stop bit Stop bit Idling Stop bit FSK Start bit #1 Start bit #2 Start bit #3 Start bit Idling #4 At least 5 bits of idling inserted A12320 No. 6124-10/17 LC73815M DRCNT S/R ACK DATA D0 to D7 Idling DR Start bit DC bias D0 FSK D1 Start bit D2 D3 D4 D5 D6 D7 A12321 DRCNT S/R ACK DATA #1 #2 #3 #4 DR DC bias Stop bit Stop bit Idling Stop bit Stop bit FSK Start bit #1 Start bit #2 Start bit #3 Start bit Idling #4 At least 5 bits of idling inserted A12322 No. 6124-11/17 LC73815M DRCNT S/R ACK #1 DATA #2 DR DC bias Idling Stop bit Start bit D0 D1 D2 D3 D4 D5 D6 D7 FSK Stop bit Start bit Idling D0 D1 D2 D3 D4 D5 D6 D7 Idling #1 #2 At least 5 bits of idling inserted A12323 DRCNT S/R ACK #2 #1 DATA DR Idling Idling DC bias Stop bit Start bit D0 D1 D2 D3 D4 D5 D6 D7 FSK Stop bit Start bit Idling D0 D1 D2 D3 D4 D5 D6 D7 DC bias Idling #1 #2 At least 5 bits of idling inserted A12324 No. 6124-12/17 LC73815M Pin Internal Connection Pin No. Pin Internal connection VDD IN– 1 – VDD 2 IN+ IN– 3 GS 1 + IN+ 2 VDD GS 3 A12325 VDD VDD + AGNDI 4 – 4 AGNDI 10 AGNDO VDD AGNDO 10 A12326 VDD VDD 6 FSKOUT FSKOUT 6 A12327 VDD + AGCO 7 – VDD 7 AGCO 8 FSKIN FSKIN 8 – + 1/2VDD TESTI 12 12 TESTI A12328 VDD B/V 13 13 B/V 21 S/R S/R 21 22 F/D F/D 22 A12329 Continued on next page. No. 6124-13/17 LC73815M Continued from preceding page. Pin No. Pin Internal connection VDD OSCIN 15 15 OSCIN 16 OSCOUT VDD SOCOUT 16 A12330 VDD DATA 24 24 DATA VDD VDD A12331 VDD ACK 25 25 ACK 29 RES RES 29 A12332 VDD DRCNT 30 30 DRCNT A1233 EST/DR 26 26 EST/DR 27 STD/DR STD/DR 27 31 TESTO1 TESTO1 31 34 TESTO2 TESTO2 34 VDD VDD A12334 No. 6124-14/17 LC73815M Pin Assignment IN+ 1 (I) 36 NC IN– 2 (I) 35 NC GS 3 (O) (O) 34 AGND 4 (O) 33 NC 5 32 NC NC TESTO2 FSKOUT 6 (O) (O) 31 TESTO1 AGCO 7 (O) (I) 30 DRCNT FSKIN 8 (I) (I) 29 RES (O) 28 RDO 10 (I) (O) 27 STD/DR 11 (O) 26 EST/DR NC 9 LC73815M AGND NC TESTI 12 (I) (I) 25 ACK B/V 13 (I) (I/O) 24 NC 14 23 NC OSCIN 15 (I) 22 F/D OSCOUT 16 (I) 21 S/R NC 17 20 NC VSS 18 19 VDD DATA Top view A12335 No. 6124-15/17 LC73815M Sample Application Circuit This example uses the DTMF receiver and the V.23 modulator, but does not use the FSK demodulator. DTMF IN 100 kΩ 1 IN+ NC 36 2 IN– NC 35 3 GS TESTO2 34 4 AGNDO NC 33 5 NC NC 32 6 FSKOUT TESTO1 31 7 AGCO DRCNT 30 8 FSKIN RES 29 9 NC RDO 28 10 AGNDI STD/DR 27 11 NC EST/DR 26 12 TESTI ACK 25 Clock 13 B/V DATA 24 Data 14 NC NC 23 15 OSCIN F/D 22 16 OSCOUT S/R 21 17 NC NC 20 18 VSS VDD 19 0.1 µF 100 kΩ 33 kΩ Reset (negative logic) DTMF detection FSK/DTMF switching 10 µF 0.1 µF CPU 0.1 µF 0.1 µF 10 kΩ FSK OUT Power supply: 5 V Top view A12336 No. 6124-16/17 LC73815M Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2000. Specifications and information herein are subject to change without notice. PS No. 6124-17/17