a Dual High Speed Low Noise Op Amps AD8022 FEATURES Low Power Amplifiers Provide Low Noise and Low Distortion, Ideal for xDSL Modem Receiver Wide Supply Range: +5 V, 2.5 V to 12 V Voltage Supply Low Power Consumption 4.0 mA/Amp Voltage Feedback Ease of Use Lower Total Noise (Insignificant Input Current Noise Contribution Compared to Current Feedback Amps) Low Noise and Distortion 2.5 nV/√Hz Voltage Noise @ 100 kHz 1.2 pA/√Hz Current Noise MTPR < –66 dBc (G = +7) SFDR 110 dB @ 200 kHz High Speed 130 MHz Bandwidth (–3 dB), G = +1 Settling Time to 0.1%, 68 ns 50 V/s Slew Rate High Output Swing 10.1 V on 12 V Supply Low Offset Voltage, 1.5 mV Typical FUNCTIONAL BLOCK DIAGRAM SOIC, MSOP OUT1 1 –IN1 2 +IN1 3 –VS 4 AD8022 – + – + 8 +VS 7 OUT2 6 –IN2 5 +IN2 APPLICATIONS Receiver for ADSL, VDSL, HDSL, and Proprietary xDSL Systems Low Noise Instrumentation Front End Ultrasound Preamp Active Filters 16-Bit ADC Buffer The AD8022 consists of two low noise, high speed, voltage feedback amplifiers. Each amplifier consumes only 4.0 mA of quiescent current yet has only 2.5 nV/√Hz of voltage noise. These dual amplifiers provide wideband, low distortion performance, with high output current optimized for stability when driving capacitive loads. Manufactured on ADI’s high voltage generation of XFCB bipolar process, the AD8022 operates on a wide range of supply voltages. The AD8022 is available in both an 8-lead MSOP and an 8-lead SOIC package. Fast overvoltage recovery and wide bandwidth make the AD8022 ideal as the receive channel front end to an ADSL, VDSL or proprietary xDSL transceiver design. In an xDSL line interface circuit, the AD8022’s op amps can be configured as the differential receiver from the line transformer or as independent active filters. 100 pA AND nV/ Hz PRODUCT DESCRIPTION 10 en (nV/ Hz) in (pA/ Hz) 1 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 1. Current and Voltage Noise vs. Frequency REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 (@ 25C, VS = 12 V, RL = 500 , G = +1, TMIN = –40C, TMAX = +85C, unless AD8022–SPECIFICATIONS otherwise noted.) Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth1 Slew Rate Rise and Fall Time Settling Time 0.1% Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Multitone Input Power Ratio2 Voltage Noise (RTI) Input Current Noise Conditions Min Typ VOUT = 50 mV p-p VOUT = 50 mV p-p VOUT = 4 V p-p VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p VOUT = 150% of Max Output Voltage, G = +2 110 130 25 4 50 30 62 MHz MHz MHz V/ms ns ns 200 ns –95 –100 dBc dBc –67.2 –66 2.5 1.2 dBc dBc nV/÷Hz pA/÷Hz 40 VOUT = 2 V p-p fC = 1 MHz fC = 1 MHz G = +7 Differential 26 kHz to 132 kHz 144 kHz to 1.1 MHz f = 100 kHz f = 100 kHz DC PERFORMANCE Input Offset Voltage –1.5 TMIN to TMAX ± 120 2.5 Input Offset Current Input Bias Current TMIN to TMAX Open-Loop Gain INPUT CHARACTERISTICS Input Resistance (Differential) Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short Circuit Output Current Capacitive Load Drive 72 VCM = ± 3 V RL = 500 W RL = 2 kW G = +1, RL = 150, DC Error = 1% RS = 0 W, <3 dB of Peaking POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio 5.0 ± 7.5 ± 10.1 ± 10.6 ± 55 100 75 V V mA mA pF ± 13.0 5.5 6.1 V mA/Amp mA/Amp dB +85 ∞C 80 –40 mV mV nA mA mA dB kW pF V dB 4.0 OPERATING TEMPERATURE RANGE ±6 ± 7.25 Unit 20 0.7 –11.25 to +11.75 98 +4.5 TMIN to TMAX VS = ± 5 V to ± 12 V Max NOTES 1 FPBW = Slew Rate/(2 p VPEAK). 2 Multitone testing performed with 800 mV rms across a 500 W load at Points A and B on TPC 20. Specifications subject to change without notice. –2– REV. A SPECIFICATIONS (@ 25C, V = 2.5 V, R = 500 , G = +1, T S Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth1 Slew Rate Rise and Fall Time Settling Time 0.1% Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Multitone Input Power Ratio2 Voltage Noise (RTI) Input Current Noise L AD8022 MIN = –40C, TMAX = +85C, unless otherwise noted.) Conditions Min Typ VOUT = 50 mV p-p VOUT = 50 mV p-p VOUT = 3 V p-p VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p VOUT = 150% of Max Output Voltage, G = +2 100 120 22 4 42 40 75 MHz MHz MHz V/ms ns ns 225 ns –77.5 –94 dBc dBc –69 –66.7 2.3 1 dBc dBc nV/÷Hz pA/÷Hz 30 VOUT = 2 V p-p fC = 1 MHz fC = 1 MHz G = +7 Differential, VS = ± 6 V 26 kHz to 132 kHz 144 kHz to 1.1 MHz f = 100 kHz f = 100 kHz DC PERFORMANCE Input Offset Voltage –0.8 TMIN to TMAX 64 20 0.7 –1.83 to +2.0 98 kW pF V dB –1.38 to +1.48 ± 32 80 75 V mA mA pF TMIN to TMAX Open-Loop Gain INPUT CHARACTERISTICS Input Resistance (Differential) Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short Circuit Output Current Capacitive Load Drive VCM = ± 2.5 V VS = ± 5.0 V RL = 500 W G = +1, RL = 100, DC Error = 1% RS = 0 W, <3 dB of Peaking POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio +4.5 3.5 TMIN to TMAX DVS = ± 1 V 5.0 7.5 ± 13.0 4.25 4.4 V mA/Amp mA/Amp dB +85 ∞C 86 OPERATING TEMPERATURE RANGE –40 NOTES 1 FPBW = Slew Rate/(2 p VPEAK). 2 Multitone testing performed with 800 mV rms across a 500 W load at Points A and B on TPC 20. Specifications subject to change without notice. REV. A ± 5.0 ± 6.25 –3– Unit mV mV nA mA mA dB ± 65 2.0 Input Offset Current Input Bias Current Max AD8022 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 1.6 W MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 0.8 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range RM, R . . . . . . –65∞C to +125∞C Operating Temperature Range (A Grade) . . . –40∞C to +85∞C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C The maximum power that can be safely dissipated by the AD8022 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150∞C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175∞C for an extended period can result in device failure. While the AD8022 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150∞C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air: 8-Lead SOIC Package: qJA = 160∞C/W. 8-Lead MSOP Package: qJA = 200∞C/W. ORDERING GUIDE Model AD8022AR AD8022ARM AD8022AR-EVAL Temperature Range Package Description Package Option –40∞C to +85∞C –40∞C to +85∞C 8-Lead Plastic SOIC 8-Lead MSOP Evaluation Board SO-8 RM-8 SO-8 2.0 MAXIMUM POWER DISSIPATION – W TJ = 150 C 1.5 8-LEAD SOIC PACKAGE 1.0 8-LEAD MSOP 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – C 80 90 Figure 2. Plot of Maximum Power Dissipation vs. Temperature CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8022 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A Typical Performance Characteristics– AD8022 5 5 4 4 3 VIN 2 50 VOUT + 50 50 2 dB dB VIN VIN = 0.05V p-p + 56.2 50 VIN = 0.2V p-p 1 0 –1 0 VIN = 2V p-p –1 RF = 402 –2 –2 –3 VIN = 0.8V p-p –3 RF = 0 –4 VIN = 0.4V p-p –4 –5 0.1 1 10 FREQUENCY – MHz 100 –5 0.1 500 TPC 1. Frequency Response vs. RF, G = +1, VS = ± 12 V, VIN = 63 mV p-p 0.3 FREQUENCY RESPONSE – dB 0.1 0 –0.1 –0.2 12V 5.0V 2.5V –0.5 –0.6 100k 100 500 1M 10M FREQUENCY – Hz RS + 453 VOUT 50 3 CL 2 715 56.2 715 50pF 1 0 –1 30pF –2 0pF –3 –4 –5 0.1 100M TPC 2. Fine-Scale Gain Flatness vs. Frequency, G = +2 1 10 FREQUENCY – kHz 100 500 TPC 5. Frequency Response vs. Capacitive Load, CL = 0 pF, 30 pF, and 50 pF, RS = 0 W 0.4 0.3 VIN 4 0.2 –0.4 10 FREQUENCY – MHz 5 G = +2 RL = 500 –0.3 1 TPC 4. Frequency Response vs. Signal Level, VS = ±12 V, G = +1 0.4 dB VOUT 453 3 RF = 715 1 140 G = +1 RL = 500 G = +1, RF = 402 120 0.2 FREQUENCY – MHz 0.1 0 dB 402 RF –0.1 –0.2 –0.3 12V –0.4 5.0V –0.5 2.5V 100 80 G = +2, RF = 715 60 40 –0.6 100k 1M 10M FREQUENCY – Hz 20 0 100M TPC 3. Fine-Scale Gain Flatness vs. Frequency, G = +1 REV. A 0 2 4 6 8 10 SUPPLY VOLTAGE – V 12 14 TPC 6. Bandwidth vs. Supply, RL = 500 W, VIN = 200 mV p-p –5– AD8022 80 70 60 100 GAIN – dB INPUT 90 50 40 30 20 10 10 0 0% OUTPUT –10 5k 10k 100k 1M 10M FREQUENCY – Hz 100M 500M TPC 7. Open-Loop Gain TPC 10. Noninverting Small Signal Pulse Response, RL = 500 W, VS = ± 2.5 V, G = +1, RF = 0 180 100 INPUT PHASE – Degrees 90 0 10 0% OUTPUT –180 5k 10k 100k 1M 10M FREQUENCY – Hz 100M 500M TPC 8. Open-Loop Phase 100 TPC 11. Noninverting Large Signal Pulse Response, RL = 500 W, VS = ± 12 V, G = +1, RF = 0 100 INPUT 10 10 0% INPUT 90 90 0% OUTPUT TPC 9. Noninverting Small Signal Pulse Response, RL = 500 W, VS = ± 12 V, G = +1, RF = 0 OUTPUT TPC 12. Noninverting Large Signal Pulse Response, RL = 500 W, VS = ± 2.5V, G = +1, RF = 0 –6– REV. A AD8022 –50 0.4 –60 HARMONIC DISTORTION – dB 0.3 SETTLING ERROR – % 0.2 +0.1% 0.1 0 –0.1% –0.1 –0.2 0 20 40 60 TIME – ns 80 100 3RD –110 2ND 0.4 –50 0.3 –60 HARMONIC DISTORTION – dB SETTLING ERROR – % –100 +0.1% 0.1 0 –0.1% –0.1 –0.2 100k FREQUENCY – Hz 1M 10M –70 2ND –80 3RD –90 –100 –110 –120 –0.3 –0.4 10k TPC 16. Distortion vs. Frequency, VS = ± 12 V, RL = 500 W, RF = 0 W, VOUT = 2 V p-p, G = +1 0.2 0 20 40 60 TIME – ns 80 100 –130 1k 120 TPC 14. Settling Time to 0.1%, VS = ± 2.5 V, Step Size = 2 V p-p, G = +2, RL = 500 W 100k FREQUENCY – Hz 1M 10M –20 –30 HARMONIC DISTORTION – dBc 60 NEGATIVE EDGE 50 POSITIVE EDGE 40 30 20 10 0 2.5 10k TPC 17. Distortion vs. Frequency, VS = ± 2.5 V, RL = 500 W, RF = 0 W, VOUT = 2 V p-p, G = +1 70 SLEW RATE – V/s –90 –130 1k 120 TPC 13. Settling Time to 0.1%, VS = ± 12 V, Step Size = 2 V p-p, G = +2, RL = 500 W –40 –50 –60 3RD –70 –80 2ND –90 –100 4.5 6.5 8.5 SUPPLY VOLTAGE – V 10.5 –120 12.5 0 5 10 15 OUTPUT VOLTAGE – V p-p 20 TPC 18. Distortion vs. Output Voltage, VS = ± 12 V, G = +2, f = 1 MHz, RL = 500 W, RF = 715 W TPC 15. Slew Rate vs. Supply Voltage, G = +2 REV. A –80 –120 –0.3 –0.4 –70 –7– AD8022 0 –40 –67.2dBc 10dB/DIV HARMONIC DISTORTION – dBc –20 –60 2ND –80 3RD –100 –120 0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE – V p-p 2.5 3.0 102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4 FREQUENCY – kHz TPC 19. Distortion vs. Output Voltage, VS = ± 2.5 V, G = +1, f = 1 MHz, RL = 500 W, RF = 0 W TPC 22. Multitone Power Ratio: VS = ± 12 V, RL = 500 W, Full Rate ADSL (DMT), Upstream +V AD8022 10dB/DIV 1/2 715 250 500 –66.7dBc 715 AD8022 1/2 549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY – kHz –V TPC 23. Multitone Power Ratio: VS = ± 6 V, RL = 500 W, Full Rate ADSL (DMT), Downstream TPC 20. Multitone Power Ratio Test Circuit 10dB/DIV 10dB/DIV –69.0dBc –66.0dBc 102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4 FREQUENCY – kHz 549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY – kHz TPC 21. Multitone Power Ratio: VS = ± 12 V, RL = 500 W, Full Rate ADSL (DMT), Downstream TPC 24. Multitone Power Ratio: VS = ± 6 V, RL = 500 W, Full Rate ADSL (DMT), Upstream –8– REV. A AD8022 0 –50 –0.5 50 –60 SIDE B 1k SIDE A –1.0 CMRR – dB VOLTAGE OFFSET – mV 1k 1k SIDE A VS = 2.5V SIDE B –1.5 56.7 1k –70 –80 VS = +12V –2.0 –90 –2.5 –60 –40 –20 0 20 40 60 80 TEMPERATURE – C 100 120 –100 1k 140 TPC 25. Voltage Offset vs. Temperature 100k FREQUENCY – Hz 1M TPC 28. CMRR vs. Frequency 8.5 4.5 4.0 SUPPLY CURRENT – Total mA 8.0 3.5 BIAS CURRENT – A 10k VS = 12V 3.0 2.5 VS = 2.5V 2.0 1.5 1.0 VS = 12V 7.5 7.0 6.5 VS = 2.5V 6.0 5.5 0.5 0 –60 –40 –20 0 20 40 60 80 TEMPERATURE – C 100 120 5.0 –50 140 TPC 26. Bias Current vs. Temperature 0 50 TEMPERATURE – C 100 150 TPC 29. Total Supply Current vs. Temperature 0 4 1k VIN 1k VOUT 500 1k VS = 2.5V 1 VOS – mV POWER SUPPLY REJECTION – dB 3 2 –10 1k 0 –1 –2 VS = 12V –3 –4 –12.5 –30 –PSRR –40 –50 +PSRR –60 –70 –80 –90 –10.0 –7.5 –5.0 –2.5 0 2.5 VCM – V 5.0 7.5 10.0 –100 10k 12.5 100k 1M FREQUENCY – Hz 10M 100M TPC 30. Power Supply Rejection vs. Frequency, VS = ± 12 V TPC 27. Voltage Offset vs. Input Common-Mode Voltage REV. A –20 –9– POWER SUPPLY REJECTION – dB AD8022 0 0 –10 –10 –20 –20 –PSRR CROSSTALK – dB –30 –40 +PSRR –50 –60 –30 –50 –60 SIDE B OUT –70 –70 –80 –80 –90 –90 –100 10k SIDE A OUT –40 100k 1M FREQUENCY – Hz 10M –100 100k 100M TPC 31. Power Supply Rejection vs. Frequency, VS = ± 2.5 V 1M 10M FREQUENCY – Hz 100M TPC 33. Output-to-Output Crosstalk vs. Frequency, VS = ± 2.5 V 100 –20 31.6 –30 OUTPUT IMPEDANCE – CROSSTALK – dB 0 –10 SIDE A OUT –40 –50 –60 SIDE B OUT –70 10 3.16 1 0.316 0.1 0.0316 –80 –90 –100 100k 1M 10M FREQUENCY – Hz 30k 100M 100k 1M 10M FREQUENCY – Hz 100M 500M TPC 34. Output Impedance vs. Frequency, VS = ± 12 V TPC 32. Output-to-Output Crosstalk vs. Frequency, VS = ± 12 V –10– REV. A AD8022 THEORY OF OPERATION The AD8022 is a voltage-feedback op amp designed especially for ADSL or other applications requiring very low voltage and current noise along with low supply current, low distortion, and ease of use. The AD8022 is fabricated on Analog Devices’ proprietary eXtraFast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features enable the construction of high frequency, low distortion amplifiers with low supply currents. +VS 15 +IN OUTPUT 15 7.5pF –IN 600A –VS Figure 3. Simplified Schematic As shown in Figure 3, the AD8022 input stage consists of an NPN differential pair in which each transistor operates a 300 mA collector current. This gives the input devices a high transconductance and hence gives the AD8022 low-input noise of 2.5 nV/÷Hz @ 100 kHz. The input stage drives a folded cascode that consists of a pair of PNP transistors. These PNP’s then drive a current mirror that provides a differential input to single-ended-output conversion. The output stage provides a high current gain of 10,000, so that the AD8022 can maintain a high dc openloop gain, even into low load impedances. APPLICATIONS The low noise AD8022 dual xDSL receiver amplifier is specifically designed for the dual differential receiver amplifier function within xDSL transceiver hybrids, as well as other low noise amplifier applications. The AD8022 may be used in receiving modulated signals including discrete multitone (DMT) on either end of the subscriber loop. Communication systems designers can be challenged when designing an xDSL modem transceiver hybrid capable of receiving the smallest signals embedded in noise that inherently exists on twisted pair phone lines. Noise sources include near end crosstalk (NEXT), far end crosstalk (FEXT), REV. A background, and impulse noise, all of which are fed, to some degree, into the receiver front end. Based on a Bellcore noise survey, the background noise level for typical twisted pair telephone loops is said to be –140 dBm/÷Hz or 31 nV/÷Hz. It is therefore important to minimize the noise added by the receiver amplifiers in order to preserve as much signal-to-noise ratio (SNR) as possible. With careful transceiver hybrid design using the AD8022 dual low noise receiver amplifier, maintaining power density levels lower than –140 dBm/÷Hz in ADSL modems is easily achieved. DMT Modulation and Multitone Power Ratio (MTPR) ADSL systems rely on discrete multitone DMT modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. (See TPCs 21, 22, 23, and 24 for MTPR results while the AD8022 receives DMT driving 800 mV rms across 500 W differential load.) A uniquely encoded quadrature amplitude modulation (QAM) signal occurs at the center frequency of each subband or tone. Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line receivers, such as spurious-free dynamic range (SFDR), single tone harmonic distortion or THD, two-tone intermodulation distortion (IMD), and third order intercept (IP3), become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms. A typical xDSL downstream DMT signal may contain as many as 256 carriers (subbands or tones) of QAM signals. MTPR is the relative difference between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal) yielding an empty frequency bin. MTPR, sometimes referred to as the “empty bin test,” is typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third harmonic distortion components. Measurements of MTPR are typically made at the output of the receiver directly across the differential load. Other components aside, the receiver function of an ADSL transceiver hybrid will be affected by the turns ratio of the selected transformers within the hybrid design. Since a transformer reflects the secondary voltage back to the primary side by the inverse of the turns ratio, 1/N, increasing the turns ratio on the secondary side reduces the voltage across the primary side inputs of the differential receiver. Increasing the turns ratio of the transformers may inadvertently cause a reduction of the SNR by reducing the received signal strength. –11– AD8022 Channel Capacity and SNR The efficiency of an ADSL system in delivering the digital data embedded in the DMT signals can be compromised when the noise power of the transmission system increases. The graph below shows the relationship between SNR and the relative maximum number of bits per tone or subband while maintaining a bit error rate at 1E-7 errors per second. 60.00 50.00 SNR – dB 40.00 30.00 20.00 10.00 0.00 0 5 10 15 BITS/TONE Figure 4. ADSL DMT SNR vs. Bits/Tone Generating DMT At this time, DMT modulated waveforms are not typically menu selectable items contained within arbitrary waveform generators (AWG). AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D/A converters and output amplifiers used by AWG manufacturers. Similar to evaluating single tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with Opt 4, (12-bit/24-bit, TTL digital data out), digitally coupled to Analog Devices’ AD9754, a 14-bit TxDAC, buffered by an AD8002 amplifier configured as a differential driver. See Figure 5 for schematics of a circuit used to generate DMT signals that can achieve down to –80 dBc of MTPR performance, sufficient for use in evaluating xDSL receivers. WFM files are needed to produce the necessary digital data required to drive the TxDAC from the optional TTL digital data output of the TEK AWG2021. Copies of .WFM files for upstream and downstream DMT waveforms with a peak-toaverage ratio (crest factor) of ~5.3 can be obtained through the Analog Devices website: http://products.analog.com/products/info.asp?product=AD8022. Upstream data is contained in the ...24.wfm files and downstream data in the ...128.wfm files. These DMT modulated signals are used to evaluate xDSL products for multitone power ratio or MTPR performance. The data files are used in pairs (e.g., adslu24.wfm and adsll24.wfm go together) and are loaded into Tektronics AWG2021 arbitrary waveform generator. The adslu24.wfm is loaded via the TEK AWG2021 floppy drive into Channel 1, while the adsll24.wfm is simultaneously loaded into Channel 2. The number in the file name, prefixed with ‘u,’ goes into CH1 or upper channel and the ‘l’ goes into CH2 or the lower channel. Twelve bits from channel CH1 are combined with two bits from CH2 to achieve 14-bit digital data at the digital outputs of the TEK 2021. The resulting waveforms produced at the AD9754-EB outputs are then buffered and amplified by the AD8002 differential driver to achieve 14-bit performance from this DMT signal source. Power Supply and Decoupling The AD8022 should be powered with a good quality (i.e., low noise) dual supply of ± 12 V for the best overall performance. The AD8022 circuit will also function at voltages lower than ± 12 V. Careful attention must be paid to decoupling the power supply pins. A pair of 10 mF capacitors located in near proximity to the AD8022 is required to provide good decoupling for lower frequency signals. In addition, 0.1 mF decoupling capacitors should be located as close to each of the power supply pins as is physically possible. –12– REV. A REV. A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Figure 5. DMT Signal Generator Schematic –13– A J4 A J3 R1 OUT2 OUT1 R2 C13 22pF C12 22pF A A R5 C4 10F TP4 B3 1F R6 49.9 1F A A 10k 10k 226 AVEE 16 15 14 13 12 11 10 9 AVEE 0.1F AD8002 750 750 AD8002 0.1F 1 2 3 4 5 6 7 A A 16 15 14 13 12 11 10 16 PINDIP RES PK 1 2 3 4 5 6 7 8 16 PINDIP RES PK TP5 TP18 TP19 B4 AVCC C30 C31 C32 C33 C34 C35 C36 C19 C1 C2 C25 C26 C27 C28 C29 A AGND DVDD 1 2 3 4 5 6 7 8 9 10 AVDD 10 9 8 7 6 5 4 3 2 1 49.9 1 2 3 4 5 6 7 8 9 10 10 9 8 7 6 5 4 3 2 1 3 5 7 9 11 TO TEK 13 15 AWG 17 2021 19 21 23 25 27 29 31 33 35 37 39 P1 1 DVDD TP2 TP3 C3 10F B2 DGND B1 DVDD R3 C6 10F TP7 B6 249 249 R4 A A R7 R8 DVDD 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 J1 2 3 4 5 6 7 8 9 10 EXTCLK 10 9 8 7 6 5 4 3 2 1 DVDD A DIFFERENTIAL DMT OUTPUTS 1 2 3 4 5 6 7 8 9 10 A AVCC 10 9 8 7 6 5 4 3 2 1 C5 10F TP6 B5 A TP12 A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 CLK JP1 R17 49.9 CLOCK DVDD DCOM NC AVDD COMP2 IOUTA IOUTB ACOM COMP1 FS ADJ REFIO REFLO SLEEP CT1 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AD9754 U1 1 R15 49.9 TP1 PDIN J2 A 3 B JP2 A 3 2 1 AVDD TP11 AVDD C7 1F A A JP4 TP14 R 20k R16 2k TP10 AVDD C11 0.1F C8 0.1F TP9 OUT 2 TP8 OUT 1 C10 0.1F AVDD A C9 0.1F TP13 AD8022 AD8022 EVALUATION BOARDS Layout Considerations The evaluation board schematic of Figure 8 is our standard dual SOIC noninverting evaluation circuit, offering the ability to evaluate the AD8022 in typical op amp circuits, available from Analog Devices Inc. In addition, the AD8022 receiver function may be added to on our ADSL EVAL boards. The AD8016ARB-EVAL, the AD8016ARP-EVAL, AD8017AR-EVAL, and AD8018ARUEVAL boards are available through Analog Devices. These platforms provide the capability to fully evaluate the Analog Devices ADSL transceiver hybrid. All of the ADSL evaluation boards mentioned above can accommodate the evaluation of the AD8022 as a receiver amplifier when installed in the U2 location. The receiver circuit on these boards is typically unpopulated. Requesting samples of the AD8022 along with the EVAL board of your choice will provide the capability to evaluate the AD8022 along with many other Analog Devices ADSL line driver products in a typical transceiver circuit. The evaluation circuits have been designed to replicate the CPE or CO side analog transceiver hybrid circuits. As is the case with all “high speed” amplifiers, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. Removing the ground plane from the area near the input signal lines will reduce stray capacitance. Chip capacitors should be used for the supply bypassing. One end of the capacitor should be connected to the ground plane and the other no more than 1/8 inch away from each supply pin. An additional large (0.47 mF to 10 mF) tantalum capacitor should be connected in parallel, although not necessarily as close, in order to supply current for fast, large signal changes at the AD8022 output. Signal lines connecting the feedback and gain resistors should be as short as possible, minimizing the inductance and stray capacitance associated with these traces. Locate termination resistors and loads as close as possible to the input(s) and output respectively. Adhere to stripline design techniques for long signal traces (greater than about 1 inch). Following these generic guidelines will improve the performance of the AD8022 in all applications. The ADSL EVAL circuits mentioned above are designed using a two transformer transceiver topology, including a line receiver, line driver, line matching network, an RJ11 jack for interfacing to line simulators, and transformer-coupled inputs for single-todifferential input conversion. 7.5 2.5 6800pF 5% NPO –2.5 –7.5 191 1% 243 1% 3 2 8200pF 10% COMMON MODE VOLTAGE SIGNAL CM LEVEL 0.1F 16V 10% X7R –VIN –17.5 –22.5 –27.5 –32.5 422 1% –37.5 –42.5 –47.5 10k 249 1% 6 7 5 191 1% +V0 249 1% 0.1F 50V 5% NPO 8200pF 10% –12.5 8 AD8022 1 dB +VIN 12V –V0 100k 1M FREQUENCY – Hz 10M Figure 7. Frequency Response of Sallen-Key Filter 4 AD8022 243 1% 6800pF 5% NPO Figure 6. Differential Input Sallen-Key Filter Using AD8022 on Single Supply, +12 V –14– REV. A AD8022 RF 715 RF 715 +VS RO 0 RO 0 J4 J2 J1 RT 49.9 G=2 RG 715 G=2 RG 715 AD8022 RC 0 J3 499 49.9 –VS AMP #2 AMP #1 BYPASSING +VS C3 0.01F C1 10F C4 0.01F C2 10F –VS Figure 8. Evaluation Board Schematic REV. A AD8022 RC 0 –15– 499 AD8022 OUTLINE DIMENSIONS 8-Lead MSOP Package [MSOP] (RM-8) 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 8 5 4.90 BSC 3.00 BSC 6.20 (0.2440) 5.80 (0.2284) C01053–0–9/02(A) 3.00 BSC 1 4 PIN 1 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.33 (0.0130) 0.65 BSC 0.50 (0.0196) ⴛ 45ⴗ 0.25 (0.0099) 1.10 MAX 0.15 0.00 8ⴗ 0.25 (0.0098) 0ⴗ 1.27 (0.0500) 0.41 (0.0160) 0.19 (0.0075) 0.38 0.22 COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.23 0.08 8ⴗ 0ⴗ 0.80 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MS-012AA Revision History Location Page 9/02–Data Sheet changed from REV. 0 to REV. A. Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to TPCs 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 New TPCs 7, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to TPCs 16, 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to TPC 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 –16– REV. A PRINTED IN U.S.A. Edits to TPC 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9