AD AD8022ARZ

Dual High Speed,
Low Noise Op Amp
AD8022
FUNCTIONAL BLOCK DIAGRAM
Low power amplifiers provide low noise and low distortion,
ideal for xDSL modem receiver
Wide supply range: +5 V, ±2.5 V to ±12 V voltage supply
Low power consumption: 4.0 mA/Amp
Voltage feedback
Ease of Use
Lower total noise (insignificant input current noise
contribution compared to current feedback amps)
Low noise and distortion
2.5 nV/√Hz voltage noise @ 100 kHz
1.2 pA/√Hz current noise
MTPR < −66 dBc (G = +7)
SFDR 110 dB @ 200 kHz
High speed
130 MHz bandwidth (−3 dB), G = +1
Settling time to 0.1%, 68 ns
50 V/μs slew rate
High output swing: ±10.1 V on ±12 V supply
Low offset voltage, 1.5 mV typical
OUT1 1
–IN1 2
+IN1 3
AD8022
7 OUT2
–
+
–
+
–VS 4
8 +VS
6 –IN2
5 +IN2
01053-001
FEATURES
Figure 1.
APPLICATIONS
Receiver for ADSL, VDSL, HDSL, and proprietary
xDSL systems
Low noise instrumentation front end
Ultrasound preamps
Active filters
16-bit ADC buffers
100
In an xDSL line interface circuit, the AD8022’s op amps can be
configured as the differential receiver from the line transformer
or as independent active filters.
10
eN (nV/ Hz)
01053-002
The AD8022 consists of two low noise, high speed, voltage
feedback amplifiers. Each amplifier consumes only 4.0 mA of
quiescent current, yet has only 2.5 nV/√Hz of voltage noise.
These dual amplifiers provide wideband, low distortion
performance, with high output current optimized for stability
when driving capacitive loads. Manufactured on ADI’s high
voltage generation of XFCB bipolar process, the AD8022
operates on a wide range of supply voltages. The AD8022 is
available in both an 8-lead MSOP and an 8-lead SOIC. Fast over
voltage recovery and wide bandwidth make the AD8022 ideal as
the receive channel front end to an ADSL, VDSL, or proprietary
xDSL transceiver design.
(pA/ Hz, nV/ Hz)
GENERAL DESCRIPTIONS
iN (pA/ Hz)
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 2. Current and Voltage Noise vs. Frequency
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
AD8022
TABLE OF CONTENTS
Specifications..................................................................................... 3
DMT Modulation and Multitone Power Ratio (MTPR)....... 13
Absolute Maximum Ratings............................................................ 5
Channel Capacity and SNR....................................................... 13
Maximum Power Dissipation ..................................................... 5
Power Supply and Decoupling.................................................. 13
ESD Caution.................................................................................. 5
Layout Considerations............................................................... 15
Typical Performance Characteristics ............................................. 6
Outline Dimensions ....................................................................... 16
Theory of Operation ...................................................................... 12
Ordering Guide .......................................................................... 16
Applications..................................................................................... 13
REVISION HISTORY
5/05—Rev. A to Rev. B
Changes to Format .............................................................Universal
Deleted Evaluation Boards Section.............................................. 14
Deleted Generating DMT Section................................................ 14
Changes to Ordering Guide.......................................................... 16
Updated Outline Dimensions....................................................... 16
9/02—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Applications...................................................................1
Changes to Product Description .....................................................1
Changes to Functional Block Diagram ..........................................1
Changes to Figure 1...........................................................................1
Changes to Specifications Table......................................................2
Edits to TPCs 1, 2, 3, 6 ......................................................................5
New TPCs 7, 8....................................................................................6
Edits to TPCs 16, 17, 18....................................................................7
Edits to TPC 19 ..................................................................................8
Edits to TPC 28 ..................................................................................9
Edits to Figure 3...............................................................................11
Edits to Figure 6...............................................................................14
Updated Outline Dimensions........................................................16
Rev. B | Page 2 of 16
AD8022
SPECIFICATIONS
At 25°C, VS = ±12 V, RL = 500 Ω, G = +1, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth 1
Slew Rate
Rise and Fall Time
Settling Time 0.1%
Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Multitone Input Power Ratio 2
Voltage Noise (RTI)
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Conditions
Min
Typ
VOUT = 50 mV p-p
VOUT = 50 mV p-p
VOUT = 4 V p-p
VOUT = 2 V p-p, G = +2
VOUT = 2 V p-p, G = +2
VOUT = 2 V p-p
VOUT = 150% of max output
voltage, G = +2
110
130
25
4
50
30
62
200
MHz
MHz
MHz
V/μs
ns
ns
ns
−95
−100
dBc
dBc
−67.2
−66
2.5
1.2
dBc
dBc
nV/√Hz
pA/√Hz
40
VOUT = 2 V p-p
fC = 1 MHz
fC = 1 MHz
G = +7 differential
26 kHz to 132 kHz
144 kHz to 1.1 MHz
f = 100 kHz
f = 100 kHz
−1.5
72
20
0.7
−11.25 to +11.75
98
kΩ
pF
V
dB
±10.1
±10.6
±55
100
75
V
V
mA
mA
pF
±120
2.5
TMIN to TMAX
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance (Differential)
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
1
2
VCM = ±3 V
RL = 500 Ω
RL = 2 kΩ
G = +1, RL = 150 Ω, dc error = 1%
RS = 0 Ω, <3 dB of peaking
+4.5
4.0
TMIN to TMAX
VS = ±5V to ±12 V
5.0
±7.5
±13.0
5.5
6.1
80
−40
FPBW = Slew Rate/(2π VPEAK).
Multitone testing performed with 800 mV rms across a 500 Ω load at Point A and Point B on the circuit of Figure 23.
Rev. B | Page 3 of 16
±6
±7.25
Unit
mV
mV
nA
μA
μA
dB
TMIN to TMAX
Input Offset Current
Input Bias Current
Max
+85
V
mA/Amp
mA/Amp
dB
°C
AD8022
At 25°C, VS = ±2.5 V, RL = 500 Ω, G = +1, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth 1
Slew Rate
Rise and Fall Time
Settling Time 0.1%
Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Multitone Input Power Ratio 2
Voltage Noise (RTI)
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Conditions
Min
Typ
VOUT = 50 mV p-p
VOUT = 50 mV p-p
VOUT = 3 V p-p
VOUT = 2 V p-p, G = +2
VOUT = 2 V p-p, G = +2
VOUT = 2 V p-p
VOUT = 150% of max output
voltage, G = +2
100
120
22
4
42
40
75
225
MHz
MHz
MHz
V/μs
ns
ns
ns
−77.5
−94
dBc
dBc
−69
−66.7
2.3
1
dBc
dBc
nV/√Hz
pA/√Hz
30
VOUT = 2 V p-p
fC = 1 MHz
fC = 1 MHz
G = +7 differential, VS = ±6 V
26 kHz to 132 kHz
144 kHz to 1.1 MHz
f = 100 kHz
f = 100 kHz
−0.8
64
20
0.7
−1.83 to +2.0
98
kΩ
pF
V
dB
−1.38 to +1.48
±32
80
75
V
mA
mA
pF
±65
2.0
TMIN to TMAX
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance (Differential)
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
1
2
VCM = ±2.5 V, VS = ±5.0 V
RL = 500 Ω
G = +1, RL = 100 Ω, dc error = 1%
RS = 0 Ω, <3 dB of peaking
+4.5
3.5
TMIN to TMAX
∆VS = ±1 V
±5.0
±6.25
5.0
7.5
±13.0
4.25
4.4
86
−40
FPBW = Slew Rate/(2 π VPEAK).
Multitone testing performed with 800 mV rms across a 500 Ω load at Point A and Point B on the circuit of Figure 23.
Rev. B | Page 4 of 16
Unit
mV
mV
nA
μA
μA
dB
TMIN to TMAX
Input Offset Current
Input Bias Current
Max
+85
V
mA/Amp
mA/Amp
dB
°C
AD8022
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage (+VS to −VS)
Internal Power Dissipation 1
8-Lead SOIC (R)
8-Lead MSOP (RM)
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
(A Grade)
Lead Temperature Range
(Soldering 10 sec)
1
Rating
26.4 V
1.6 W
1.2 W
±VS
±0.8 V
Observe Power Derating Curves
−65°C to +125°C
−40°C to +85°C
300°C
Specification is for the device in free air:
8-Lead SOIC: θJA = 160°C/W.
8-Lead MSOP: θJA = 200°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8022 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
While the AD8022 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves.
2.0
1.5
8-LEAD SOIC PACKAGE
1.0
8-LEAD MSOP
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE (°C)
01053-003
MAXIMUM POWER DISSIPATION (W)
TJ = 150°C
70
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 16
80
90
AD8022
TYPICAL PERFORMANCE CHARACTERISTICS
5
5
RF
402Ω
4
4
VOUT
RF = 715Ω
VIN
2
3
VIN
2
50Ω
56.2Ω
50Ω
(dB)
–1
–1
RF = 402Ω
–3
01053-004
1
10
FREQUENCY (MHz)
100
–4
1
10
FREQUENCY (MHz)
100
500
Figure 7. Frequency Response vs. Signal Level, VS = ±12 V, G = +1
0.4
5
G = +2
RL = 500Ω
VIN
RS
4
453Ω
VOUT
50Ω
FREQUENCY RESPONCE (dB)
0.2
0.1
0
(dB)
VIN = 0.4V p-p
–5
0.1
500
Figure 4. Frequency Response vs. RF, G = +1, VS = ±12 V, VIN = 63 mV p-p
–0.1
–0.3
±12V
–0.4
±5.0V
±2.5V
–0.5
–0.6
100k
1M
10M
FREQUENCY (Hz)
01053-005
–0.2
3
CL
2
715Ω
56.2Ω
715Ω
50pF
1
0
–1
30pF
–2
0pF
–3
–4
–5
0.1
100M
1
10
FREQUENCY (kHz)
100
500
Figure 8. Frequency Response vs. Capacitive Load; CL = 0 pF and 50 pF; RS = 0 Ω
Figure 5. Fine-Scale Gain Flatness vs. Frequency, G = +2
140
0.4
0.3
VIN = 0.8V p-p
–3
RF = 0Ω
–5
0.1
VIN = 2.0V p-p
–2
–4
0.3
0
01053-008
(dB)
0
VIN = 0.2V p-p
50Ω
1
1
–2
VIN = 0.05V p-p
VOUT
453Ω
01053-007
50Ω
3
G = +2
RL = 500Ω
G = +1, RF = 402Ω
120
0.2
100
FREQUENCY (MHz)
0.1
–0.1
–0.2
±12V
–0.4
±5.0V
–0.5
±2.5V
–0.6
100k
1M
10M
FREQUENCY (Hz)
80
G = +2, RF = 715Ω
60
40
100M
20
01053-009
–0.3
01053-006
(dB)
0
0
0
2
4
6
8
10
SUPPLY VOLTAGE (±V)
12
Figure 9. Bandwidth vs. Supply, RL = 500 Ω, VIN = 200 mV p-p
Figure 6. Fine-Scale Gain Flatness vs. Frequency, G = +1
Rev. B | Page 6 of 16
14
AD8022
80
100mV
70
60
100ns
INPUT
100
90
GAIN (dB)
50
40
30
20
10
10
0
OUTPUT
0%
–10
5k 10k
100k
1M
10M
FREQUENCY (Hz)
100M
01053-013
01053-010
100mV
500M
Figure 10. Open-Loop Gain vs. Frequency
Figure 13. Noninverting Small Signal Pulse Response,
RL = 500 Ω, VS = ±2.5 V, G = +1, RF = 0 Ω
2.00V
180
100ns
INPUT
FREQUENCY (Degrees)
100
90
0
10
OUTPUT
01053-011
0%
5k 10k
100k
1M
10M
FREQUENCY (Hz)
100M
2.00V
500M
Figure 11. Open-Loop Phase vs. Frequency
100mV
Figure 14. Noninverting Large Signal Pulse Response,
RL = 500 Ω, VS = ±12 V, G = +1, RF = 0 Ω
1.00V
100ns
INPUT
100
01053-014
–180
100ns
INPUT
100
90
90
10
OUTPUT
OUTPUT
1.00V
01053-012
100mV
0%
Figure 15. Noninverting Large Signal Pulse Response,
RL = 500 Ω, VS = ±2.5 V, G = +1, RF = 0 Ω
Figure 12. Noninverting Small Signal Pulse Response,
RL = 500 Ω, VS = ±12 V, G = +1, RF = 0 Ω
Rev. B | Page 7 of 16
01053-015
10
0%
AD8022
–50
0.3
–60
HARMONIC DISTORTION (dB)
0.4
0
–0.1%
–0.1
–0.2
–0.4
0
20
40
60
TIME (ns)
80
100
–90
–100
2ND
–130
1k
120
Figure 16. Settling Time to 0.1%, VS = ±12 V,
Step Size = 2 V p-p, G = +2, RL = 500 Ω
0.3
–60
HARMONIC DISTORTION (dB)
–50
SETTLING ERROR (%)
0.2
0.1
+0.1%
0
–0.1
–0.1%
–0.2
–0.4
40
60
TIME (ns)
80
100
10M
2ND
–80
3RD
–90
–100
–110
–130
1k
120
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 20. Distortion vs. Frequency, VS = ±2.5 V,
RL = 500 Ω, RF = 0 Ω, VOUT = 2 V p-p, G = +1
70
–20
–30
NEGATIVE EDGE
50
POSITIVE EDGE
40
30
20
01053-018
10
4.5
6.5
8.5
SUPPLY VOLTAGE (V)
10.5
12.5
–40
–50
–60
3RD
–70
–80
2ND
–90
–100
01053-021
HARMONIC DISTORTION (dBc)
60
SLEW RATE (V/μs)
1M
–70
Figure 17. Settling Time to 0.1%, VS = ±2.5 V, Step Size = 2 V p-p,
G = +2, RL = 500 Ω
0
2.5
100k
FREQUENCY (Hz)
–120
01053-017
–0.3
20
10k
Figure 19. Distortion vs. Frequency, VS = ±12 V, RL = 500 Ω,
RF = 0 Ω, VOUT = 2 V p-p, G = +1
0.4
0
3RD
–110
–120
01053-016
–0.3
–80
01053-019
+0.1%
0.1
–70
01053-020
SETTLING ERROR (%)
0.2
–120
0
5
10
15
OUTPUT VOLTAGE (V p-p)
Figure 21. Distortion vs. Output Voltage, VS = ±12 V,
G = +2, f = 1 MHz, RL = 500 Ω, RF = 715 Ω
Figure 18. Slew Rate vs. Supply Voltage, G = +2
Rev. B | Page 8 of 16
20
AD8022
0
–40
10dB/DIV (dBc)
–60
2ND
–80
–67.2dBc
3RD
01053-022
–100
01053-025
HARMONIC DISTORTION (dBc)
–20
–120
0
0.5
1.0
1.5
2.0
OUTPUT VOLTAGE (V p-p)
2.5
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4
FREQUENCY (kHz)
3.0
Figure 22. Distortion vs. Output Voltage, VS = ±2.5 V,
G = +1, f = 1 MHz, RL = 500 Ω, RF = 0 Ω
Figure 25. Multitone Power Ratio: VS = ±12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
+V
AD8022
10dB/DIV (dBc)
1/2
715Ω
250Ω
500Ω
–66.7dBc
715Ω
01053-026
AD8022
1/2
01053-023
–V
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY (kHz)
10dB/DIV (dBc)
Figure 26. Multitone Power Ratio: VS = ±6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
–66.0dBc
–69.0dBc
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY (kHz)
Figure 24. Multitone Power Ratio: VS = ±12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
01053-027
01053-024
10dB/DIV (dBc)
Figure 23. Multitone Power Ratio Test Circuit
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4
FREQUENCY (kHz)
Figure 27. Multitone Power Ratio: VS = ±6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
Rev. B | Page 9 of 16
AD8022
–50
0
1kΩ
1kΩ
SIDE A
50Ω
–60
1kΩ
SIDE B
56.7Ω
SIDE A
–1.0
SIDE B
CMRR (dB)
VS = ±2.5V
–1.5
–80
VS = +12V
–2.0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
01053-031
01053-028
–90
–2.5
–60
–100
1k
140
Figure 28. Voltage Offset vs. Temperature
10k
100k
FREQUENCY Hz)
1M
Figure 31. CMRR vs. Frequency
4.5
8.5
4.0
TOTAL SUPPLY CURRENT (mA)
8.0
3.5
BIAS CURRENT (μA)
1kΩ
–70
VS = ±12V
3.0
2.5
VS = ±2.5V
2.0
1.5
1.0
0
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
7.0
6.5
VS = ±2.5V
6.0
5.5
01053-029
0.5
VS = ±12V
7.5
5.0
–50
140
Figure 29. Bias Current vs. Temperature
01053-032
VOLTAGE OFFSET (mV)
–0.5
0
50
TEMPERATURE (°C)
100
150
Figure 32. Total Supply Current vs. Temperature
4
0
1kΩ
–10
VOUT
1kΩ
1kΩ
500Ω
VS = ±2.5V
0
–1
–2
VS = ±12V
–3
–4
–12.5 –10.0 –7.5
01053-030
VOS (mV)
1
–5.0
–2.5
0
2.5
VCM (V)
5.0
7.5
10.0
12.5
–20
–30
–PSRR
–40
–50
+PSRR
–60
–70
–80
01053-033
2
VIN
1kΩ
POWER SUPPLY REJECTION (dB)
3
–90
–100
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 33. Power Supply Rejection vs. Frequency VS = ±12 V
Figure 30. Voltage Offset vs. Input Common-Mode Voltage
Rev. B | Page 10 of 16
100M
0
0
–10
–10
–20
–20
–30
CROSSTALK (dB)
–PSRR
–40
–50
–60
+PSRR
SIDE A OUT
–40
–50
–60
SIDE B OUT
–70
–70
–80
–80
–90
–100
10k
100k
1M
FREQUENCY (Hz)
10M
01053-036
–30
01053-034
POWER SUPPLY REJECTION (dB)
AD8022
–90
–100
100k
100M
Figure 34. Power Supply Rejection vs. Frequency VS = ±2.5 V
1M
10M
FREQUENCY (Hz)
100M
Figure 36. Output-to-Output Crosstalk vs. Frequency, VS = ±2.5 V
0
100
–10
31
OUTPUT IMPEDANCE (Ω)
–20
SIDE A OUT
–40
–50
–60
SIDE B OUT
–70
3.16
1
0.316
0.1
–90
100k
1M
FREQUENCY (Hz)
10M
100M
01053-037
0.0316
–80
–100
10k
10
01053-035
CROSSTALK (dB)
–30
30k
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 37. Output Impedance vs. Frequency, VS = ±12 V
Figure 35. Output-to-Output Crosstalk vs. Frequency, VS = ±12 V
Rev. B | Page 11 of 16
500M
AD8022
THEORY OF OPERATION
The AD8022 is a voltage-feedback op amp designed especially
for ADSL or other applications requiring very low voltage and
current noise along with low supply current, low distortion, and
ease of use.
The AD8022 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process, which
enables the construction of PNP and NPN transistors with
similar fTs in the 4 GHz region. The process is dielectrically
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features enable the construction of
high frequency, low distortion amplifiers with low supply
currents.
As shown in Figure 38, the AD8022 input stage consists of an
NPN differential pair in which each transistor operates a
300 μA collector current. This gives the input devices a high
transconductance and therefore gives the AD8022 a low input
noise of 2.5 nV/√Hz @ 100 kHz. The input stage drives a folded
cascode that consists of a pair of PNP transistors. These PNPs
then drive a current mirror that provides a differential input to
single-ended output conversion. The output stage provides a
high current gain of 10,000 so that the AD8022 can maintain a
high dc open-loop gain, even into low load impedances.
+VS
15Ω
+IN
OUTPUT
15Ω
7.5pF
–IN
–VS
01053-038
600μA
Figure 38. Simplified Schematic
Rev. B | Page 12 of 16
AD8022
APPLICATIONS
ADSL systems rely on discrete multitone DMT modulation to
carry digital data over phone lines. DMT modulation appears in
the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which is uniformly separated in frequency. (See Figure 24
to Figure 27 for MTPR results while the AD8022 receives DMT
driving 800 mV rms across a 500 Ω differential load.) A
uniquely encoded quadrature amplitude modulation (QAM)
signal occurs at the center frequency of each subband or tone.
Difficulties exist when decoding these subbands if a QAM
signal from one subband is corrupted by the QAM signal(s)
from other subbands, regardless of whether the corruption
comes from an adjacent subband or harmonics of other
subbands. Conventional methods of expressing the output
signal integrity of line receivers, such as spurious-free dynamic
range (SFDR), single tone harmonic distortion (THD), twotone intermodulation distortion (IMD), and third-order
intercept (IP3), become significantly less meaningful when
amplifiers are required to process DMT and other heavily
modulated waveforms. A typical xDSL downstream DMT signal
can contain as many as 256 carriers (subbands or tones) of
QAM signals. MTPR is the relative difference between the
measured power in a typical subband (at one tone or carrier) vs.
the power at another subband specifically selected to contain no
QAM data.
In other words, a selected subband (or tone) remains open or
void of intentional power (without a QAM signal) yielding an
CHANNEL CAPACITY AND SNR
The efficiency of an ADSL system in delivering the digital data
embedded in the DMT signals can be compromised when the
noise power of the transmission system increases. Figure 39
shows the relationship between SNR and the relative maximum
number of bits per tone or subband while maintaining a bit
error rate at 10–7 errors per second.
60
50
40
30
20
10
01053-039
DMT MODULATION AND MULTITONE POWER
RATIO (MTPR)
empty frequency bin. MTPR, sometimes referred to as the
empty bin test, is typically expressed in dBc, similar to
expressing the relative difference between single tone
fundamentals and second or third harmonic distortion
components. Measurements of MTPR are typically made at the
output of the receiver directly across the differential load. Other
components aside, the receiver function of an ADSL transceiver
hybrid is affected by the turns ratio of the selected transformers
within the hybrid design. Since a transformer reflects the
secondary voltage back to the primary side by the inverse of the
turns ratio, 1/N, increasing the turns ratio on the secondary side
reduces the voltage across the primary side inputs of the
differential receiver. Increasing the turns ratio of the
transformers can inadvertently cause a reduction of the SNR by
reducing the received signal strength.
SNR (dB)
The low noise AD8022 dual xDSL receiver amplifier is
specifically designed for the dual differential receiver amplifier
function within xDSL transceiver hybrids, as well as other low
noise amplifier applications. The AD8022 can be used in
receiving modulated signals including discrete multitone
(DMT) on either end of the subscriber loop. Communication
systems designers can be challenged when designing an xDSL
modem transceiver hybrid capable of receiving the smallest
signals embedded in noise that inherently exists on twisted-pair
phone lines. Noise sources include near-end crosstalk (NEXT),
far-end crosstalk (FEXT), background, and impulse noise, all of
which are fed, to some degree, into the receiver front end. Based
on a Bellcore noise survey, the background noise level for
typical twisted-pair telephone loops is −140 dBm/√Hz or
31 nV/√Hz. It is therefore important to minimize the noise
added by the receiver amplifiers to preserve as much signal-tonoise ratio (SNR) as possible. With careful transceiver hybrid
design, using the AD8022 dual, low noise, receiver amplifier to
maintain power density levels lower than −140 dBm/√Hz in
ADSL modems is easily achieved.
0
0
5
10
15
BITS/TONE
Figure 39. ADSL DMT SNR vs. Bits/Tone
POWER SUPPLY AND DECOUPLING
The AD8022 should be powered with a good quality (that is,
low noise) dual supply of ±12 V for the best overall
performance. The AD8022 circuit also functions at voltages
lower than ±12 V. Careful attention must be paid to decoupling
the power supply pins. A pair of 10 μF capacitors located in
near proximity to the AD8022 is required to provide good
decoupling for lower frequency signals. In addition, 0.1 μF
decoupling capacitors should be located as close to each of the
power supply pins as is physically possible.
Rev. B | Page 13 of 16
Figure 40. DMT Signal Generator Schematic
Rev. B | Page 14 of 16
01053-040
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
A
J4
A
J3
C13
22pF
OUT2
C12
22pF
OUT1
R2
A
A
1μF
R6
49.9Ω
1μF
A
A
10kΩ
10kΩ
226Ω
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AVEE
0.1μF
AD8002
750Ω
750Ω
AD8002
0.1μF
A
A
16
15
14
13
12
11
10
9
16 PIN DIP
RES PK
1
2
3
4
5
6
7
8
C6
10μF
249Ω
249Ω
R2
+
A
A
R6
J1
DVDD
1
2 3 4 5 6 7 8 9 10 1
2
3
4
5
6
7
8
9
10
11
12
13
14
R7
EXTCLK
10 9 8 7 6 5 4 3 2
1
DVDD
A
DIFFERENTIAL
DMT OUTPUTS
1
2 3 4 5 6 7 8 9 10
A
TP7
AVCC
B6
10 9 8 7 6 5 4 3 2
1
R3
+
C5
10μF
TP6
AVEE
B5
16 PIN DIP
RES PK
TP5
AVCC
DVDD
C30
C31
C32
C33
C34
C35
C36
C19
C1
C2
C25
C26
C27
C27
C29
A
TP18
TP19
AGND
B4
1
2 3 4 5 6 7 8 9 10
10 9 8 7 6 5 4 3 2
49.9Ω
1
2 3 4 5 6 7 8 9 10
1
R5
DVDD
C4
10μF
10 9 8 7 6 5 4 3 2
1
3
5
7
9
11
TO TEK 13
AWG 15
17
2021
19
21
23
25
27
29
31
33
35
37
39
P1
1
R1
+
TP4
AVDD
B3
C3
10μF
TP2
DGND
B2
+
TP3
DVDD
B1
TP12
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R17
49.9Ω
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
CT1
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AD9754
U1
PDIN
J2
A
B
3
A
2
CLK
JP1
R15 1
49.9Ω
TP1
JP2
A
3
2
1
AVDD
TP11
AVDD
C7
1μF
A
C11
0.1μF
A
TP10
JP4
A
C10
0.1μF
TP9
OUT2
TP8
OUT1
C9
0.1μF
AVDD
TP14
R16
2kΩ
R
20kΩ
AVDD
C8
0.1μF
TP13
AD8022
AD8022
6800pF
5% NPO
191Ω
1%
LAYOUT CONSIDERATIONS
12V
243Ω
1%
3
+VIN
8
AD8022
1
2
+VOUT
8200pF
10%
COMMONMODE
VOLTAGE
SIGNAL CM LEVEL
0.1μF
16V
10%
X7R
8200pF
10%
422Ω
1%
249Ω
1%
0.1μF
50V
5%
NPO
249Ω
1%
6
7
5
191Ω
1%
4
243Ω
1%
–VOUT
AD8022
6800pF
5% NPO
01053-041
–VIN
Figure 41. Differential Input Sallen-Key Filter
Using AD8022 on Single Supply, +12 V
7.5
2.5
–2.5
–7.5
As is the case with all high speed amplifiers, careful attention to
printed circuit board layout details prevent associated board
parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the
board to provide a low impedance return path. Removing the
ground plane from the area near the input signal lines reduces
stray capacitance. Chip capacitors should be used for supply
bypassing. One end of the capacitor should be connected to the
ground plane, and the other should be connected no more than
1/8 inch away from each supply pin. An additional large
(0.47 μF to 10 μF) tantalum capacitor should be connected in
parallel, although not necessarily as close, in order to supply
current for fast, large signal changes at the AD8022 output.
Signal lines connecting the feedback and gain resistors should
be as short as possible, minimizing the inductance and stray
capacitance associated with these traces. Locate termination
resistors and loads as close as possible to the input(s) and
output, respectively. Adhere to stripline design techniques for
long signal traces (greater than about 1 inch). Following these
generic guidelines improves the performance of the AD8022 in
all applications.
–17.5
–22.5
–27.5
–32.5
01053-042
(dB)
–12.5
–37.5
–42.5
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 42. Frequency Response of Sallen-Key Filter
Rev. B | Page 15 of 16
AD8022
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
× 45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)—Dimensions shown in millimeters and (inches)
3.00
BSC
8
3.00
BSC
1
5
4.90
BSC
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
8°
0°
0.23
0.08
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)—Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8022AR
AD8022AR-REEL
AD8022AR-REEL7
AD8022ARZ 1
AD8022ARZ-REEL1
AD8022ARZ-REEL71
AD8022ARM
AD8022ARM-REEL
AD8022ARM-REEL7
AD8022ARMZ1
AD8022ARMZ-REEL1
AD8022ARMZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Z = Pb-free part.
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01053−0–5/05(B)
Rev. B | Page 16 of 16
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8