Synchronous, Step-Down DC-to-DC Controller with Voltage Tracking and Synchronization ADP1853 Data Sheet Input voltage range: 2.75 V to 20 V Output voltage range: 0.6 V to 90% VIN Maximum output current of more than 25 A Current mode architecture with current sense input Configurable to voltage mode ±1% output voltage accuracy over temperature Voltage tracking input Programmable frequency: 200 kHz to 1.5 MHz Synchronization input Internal clock output Power saving mode at light load Precision enable input Power good with internal pull-up resistor Adjustable soft start Programmable current sense gain Integrated bootstrap diode Starts into a precharged load Externally adjustable slope compensation Suitable for any output capacitor Overvoltage and overcurrent-limit protection Thermal overload protection Input undervoltage lockout (UVLO) Available in 20-lead, 4 mm × 4 mm LFCSP Supported by ADIsimPower™ design tool APPLICATIONS Intermediate bus and POL systems requiring sequencing and tracking, including Telecom base station and networking Industrial and Instrumentation Medical and healthcare current, improve EMI, and reduce the size of the input bulk capacitance. The ADP1853 can also be configured as a slave device for current sharing. Additionally, the ADP1853 includes accurate tracking, precision enable, and power good functions for sequencing. The ADP1853 provides a high speed, high peak current gate driving capability to enable energy efficient power conversion. The device can be configured to operate in power saving mode by skipping pulses, reducing switching losses and improving efficiency at light load and standby conditions. The accurate current limit allows design within a narrower range of tolerances and can reduce overall converter size and cost. The ADP1853 can regulate down to 0.6 V output using a high accuracy reference with ±1% tolerance over the temperature range from −40°C to 125°C. With a wide range input voltage, the ADP1853 is designed to provide the designer with maximum flexibility for use in a variety of system configurations; loop compensation, soft start, frequency setting, power saving mode, current limit, and current sense gain can all be programmed using external components. In addition, the external RAMP resistor allows choosing optimal slope and VIN feedforward in both current and voltage mode for excellent line rejection. The linear regulator and the boot strap diode for the high-side driver are internal. Protection features include undervoltage lock out, overvoltage, overcurrent/short circuit, and overtemperature. VIN RRAMP VMA RAMP DH BST GENERAL DESCRIPTION TRK The ADP1853 is a wide range input, dc-to-dc, synchronous buck controller capable of running from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs. The device nominally operates in current mode with valley current sensing providing the fastest step response for digital loads. It can also be configured as a voltage mode controller with low noise and crosstalk for sensitive loads. VCCO The ADP1853 can be used as a master synchronization clock for the power system and for convenient synchronization between controllers. The CLKOUT signal can synchronize other devices in the ADP185x family such that slave devices are phase-shifted from the master to reduce the input ripple VIN M1 EN L VOUT SW CS ILIM ADP1853 M2 DL RCSG SYNC PGND HI LO FREQ FB COMP SS AGND PGOOD CLKOUT 10594-001 FEATURES Figure 1. Typical Operation Circuit Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ADP1853 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Overload Protection .................................................. 16 Applications ....................................................................................... 1 Interleaved Dual-Phase Operation .......................................... 16 General Description ......................................................................... 1 Applications Information .............................................................. 17 Revision History ............................................................................... 2 ADIsimPower Design Tool ....................................................... 17 Specifications..................................................................................... 3 Setting the Output Voltage ........................................................ 17 Absolute Maximum Ratings ............................................................ 6 Soft Start ...................................................................................... 17 ESD Caution .................................................................................. 6 Setting the Current Limit .......................................................... 17 Simplified Block Diagram ............................................................... 7 Accurate Current-Limit Sensing .............................................. 17 Pin Configuration and Function Descriptions ............................. 8 Input Capacitor Selection .......................................................... 17 Typical Performance Characteristics ........................................... 10 VIN Pin Filter ............................................................................. 18 Theory of Operation ...................................................................... 12 Boost Capacitor Selection ......................................................... 18 Control Architecture .................................................................. 12 Inductor Selection ...................................................................... 18 Oscillator Frequency .................................................................. 12 Output Capacitor Selection....................................................... 18 Synchronization .......................................................................... 13 MOSFET Selection ..................................................................... 19 PWM or Pulse Skip Mode of Operation ................................. 13 Loop Compensation—Voltage Mode ...................................... 20 CLKOUT Signal .......................................................................... 13 Loop Compensation—Current Mode ..................................... 21 Synchronous Rectifier and Dead Time ................................... 14 Switching Noise and Overshoot Reduction ............................ 23 Input Undervoltage Lockout ..................................................... 14 Voltage Tracking ......................................................................... 23 Internal Linear Regulator .......................................................... 14 PCB Layout Guidlines ............................................................... 24 Overvolage Protection ............................................................... 14 Typical Operating Circuits ............................................................ 25 Power Good ................................................................................. 14 Outline Dimensions ....................................................................... 27 Short-Circuit and Current-Limit Protection .......................... 15 Ordering Guide .......................................................................... 27 Enable/Disable Control ............................................................. 15 REVISION HISTORY 5/12—Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet ADP1853 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1. Parameter POWER SUPPLY Input Voltage Undervoltage Lockout Threshold VIN UVLOTRSH Undervoltage Lockout Hysteresis Quiescent Current UVLOHYST IIN Shutdown Current ERROR AMPLIFIER FB Input Bias Current Open-Loop Gain 1 Gain-Bandwidth Product1 TRK Input Bias Current CURRENT SENSE AMPLIFIER GAIN OUTPUT CHARACTERICTISTICS Feedback Accuracy Voltage Symbol IIN_SD Test Conditions/Comments Min VIN rising VIN falling 2.75 2.55 2.35 EN = VIN = 12 V, VFB = VCCO in forced pulse width modulation (PWM) mode (no switching) EN = VIN = 12 V, VFB = VCCO in PSM mode EN = GND, VIN = 5.5 V or 20 V IFB ITRK ACS VFB Line Regulation of PWM Load Regulation of PWM1 OSCILLATOR Frequency VFB/VIN VFB/VCOMP SYNC Input Frequency Range1 SYNC Input Pulse Width1 SYNC Pin Capacitance to GND CLKOUT Frequency Range1 CLKOUT Pulse Duty Cycle CLKOUT Rise and Fall Time LINEAR REGULATOR VCCO Output Voltage VCCO Load Regulation VCCO Line Regulation VCCO Current Limit1 VCCO Short-Circuit Current1 VIN to VCCO Dropout Voltage 2 fSYNC tSYNCMIN CSYNC fCLKOUT DCLKOUT fOSC −100 Max Unit 20 2.75 2.50 2.65 2.45 0.2 4.2 5.7 V V V V mA 2.5 100 200 mA µA 0 V ≤ VTRK ≤ 5 V Gain resistor connected to DL, RCSG = 47 kΩ ± 5% Gain resistor connected to DL, RCSG = 22 kΩ ± 5% Default setting, RCSG = open Voltage mode operation, resistor DL to PGND, RCSG = 100 kΩ ± 5% −100 2.6 +1 80 20 +1 3 5.2 6 6.8 V/V 10.5 12 0 13.5 V/V V/V TJ = −40°C to +85°C TJ = −40°C to +125°C 597 594 600 600 ±0.015 ±0.3 603 606 mV mV %/V % RFREQ = 332 kΩ to AGND RFREQ = 78.7 kΩ to AGND RFREQ = 40.2 kΩ to AGND FREQ to AGND FREQ to VCCO RFREQ range from 332 kΩ to 40.2 kΩ 170 720 1275 240 480 170 100 200 800 1500 300 600 230 880 1725 360 720 1725 fOSC range from 170 kHz to 1725 kHz 170 kHz kHz kHz kHz kHz kHz ns pF kHz % ns VCOMP range = 0.9 V to 2.2 V +100 +100 3.4 nA dB MHz nA V/V 5 IVCCO = 100 mA IVCCO = 0 mA to 100 mA VIN = 5.5 V to 20 V, IVCCO = 20 mA VCCO drops to 4 V from 5 V VCCO < 0.5 V IVCCO = 100 mA, VIN ≤ 5 V Rev. 0 | Page 3 of 28 1725 50 10 CCLKOUT = 47 pF VDROPOUT Typ 4.7 5.0 35 10 350 370 0.33 5.3 400 V mV mV mA mA V ADP1853 Parameter LOGIC INPUTS EN EN Hysteresis EN Input Leakage Current SYNC Logic Input Low SYNC Logic Input High SYNC Input Pull-Down Resistance GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DH to DL Dead Time DH or DL Driver RON, Sourcing Current1 DH or DL Driver RON, Tempco DH or DL Driver RON, Sinking Current1 DH Maximum Duty Cycle1 DH Maximum Duty Cycle1 Minimum DH On Time Minimum DH Off Time Minimum DL On Time COMP VOLTAGE RANGE COMP Pulse Skip Threshold COMP Clamp High Voltage THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis OVERVOLTAGE AND POWER GOOD THRESHOLDS FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis TRK INPUT VOLTAGE RANGE1 FB TO TRK OFFSET VOLTAGE SOFT START SS Output Current SS Pull-Down Resistor FB to SS offset Data Sheet Symbol Test Conditions/Comments Min Typ Max Unit EN rising 0.57 0.63 0.03 1 0.68 1 V V nA V V MΩ RON_SOURCE CDH = 3 nF, VBST − VSW = 5 V CDH = 3 nF, VBST − VSW = 5 V CDL = 3 nF CDL = 3 nF External 3 nF is connected to DH and DL Sourcing 2 A with a 100 ns pulse 16 14 16 14 25 2 ns ns ns ns ns Ω TCRON RON_SINK Sourcing 1 A with a 100 ns pulse, VIN = 3 V VIN = 3 V or 12 V Sinking 2 A with a 100 ns pulse 2.3 0.3 1.5 Ω %/oC Ω 2 Ω % % ns ns ns IEN VIN = 2.75 V to 20 V 200 1.3 1.9 RSYNC Sinking 1 A with a 100 ns pulse, VIN = 3 V fOSC = 300 kHz fOSC = 1500 kHz fOSC = 200 kHz to 1500 kHz fOSC = 200 kHz to 1500 kHz fOSC = 200 kHz to 1500 kHz VCOMP,THRES VCOMP,HIGH 90 50 85 345 295 In pulse skip mode (PSM) TTMSD VOV VFB rising 0.630 VUV VFB falling 0.525 TRK = 0.1 V to 0.57 V; offset = VFB − VTRK 0 −10 ISS 0.9 V V 155 20 °C °C 2.2 During startup During a fault condition VSS = 0.1 V to 0.6 V; offset = VFB − VSS Rev. 0 | Page 4 of 28 4.6 −10 0.65 18 0.55 15 0 6.5 3 0.670 0.575 5 +10 8.4 +10 V mV V mV V mV µA kΩ mV Data Sheet Parameter PGOOD PGOOD Pull-Up Resistor PGOOD Delay Overvoltage or Undervoltage Minimum Duration ILIM Threshold Voltage1 ILIM Output Current Current Sense Blanking Period INTEGRATED RECTIFIER (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET (SW TO PGND)1 1 2 ADP1853 Symbol Test Conditions/Comments RPGOOD Internal pull-up resistor to VCCO This is the minimum duration required to trip the PGOOD signal Relative to PGND ILIM = PGND After DL goes high, current limit is not sensed during this period At 20 mA forward current In pulse skip mode only; fOSC = 300 kHz Guaranteed by design. Connect VIN to VCCO when VIN < 5.5 V. Rev. 0 | Page 5 of 28 Min Typ Max 12.5 12 10 −5 45 0 50 100 kΩ µs µs +5 55 16 0 2 Unit mV µA ns Ω 4 mV ADP1853 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VIN, EN, RAMP FB, COMP, SS, TRK, FREQ, SYNC, VCCO, PGOOD, CLKOUT ILIM, SW, CS to PGND BST, DH to PGND DL to PGND BST to SW BST to PGND to PGND 20 ns Transients SW, CS to PGND 20 ns Transients DL, SW, CS, ILIM to PGND 20 ns Negative Transients PGND to AGND PGND to AGND 20 ns Transients θJA (Natural Convection)1, 2 Operating Junction Temperature Range3 Storage Temperature Range Maximum Soldering Lead Temperature Rating 21 V −0.3 V to +6 V −0.3 V to +21 V −0.3 V to +28 V −0.3 V to VCCO + 0.3 V −0.3 V to +6 V 32 V 25 V −8 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. ESD CAUTION −0.3 V to +0.3 V −8 V to +4 V 40°C/W −40°C to +125°C −65°C to +150°C 260°C 1 Measured with exposed pad attached to PCB. Junction-to-ambient thermal resistance (θJA) of the package was calculated or simulated on multilayer PCB. 3 The junction temperature (TJ) of the device is dependent on the ambient temperature (TA) the power dissipation of the device (PD) and the junction to ambient thermal resistance of the package (θJA). Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula TJ = TA + PD × θJA. 2 Rev. 0 | Page 6 of 28 Data Sheet ADP1853 SIMPLIFIED BLOCK DIAGRAM VCCO VIN THERMAL SHUTDOWN OV 0.6V UV REF LDO AGND UVLO SL_TH 0.6V LOGIC EN_SW SLAVE FB VCCO EN OV LOGIC CLKOUT UV 12.5kΩ SYNC 1MΩ PGOOD OV_TH OSCILLATOR FREQ FB SLAVE COMP VCCO UV_TH ERROR AMPLIFIER CLK VREF = 0.6V – VCCO 6.5µA LOGIC FAULT 3kΩ 0.9V OV EN_SW OVER_LIM OV PULSE SKIP + EN OVER_LIM SW CS VCCO DL + SLOPE COMPENSATION AND RAMP GENERATOR CURRENT-LIMIT CONTROL DCM ZERO CROSS DETECT – CURRENT SENSE + AMPLIFIER A V = 0,* 3, 6, 12 OVER_LIM DH DRIVER LOGIC CONTROL AND STATE MACHINE – PWM COMPARATOR CS GAIN RAMP BST + – *0 (ZERO) GAIN IS FOR VOLTAGE MODE WITH RAMP FROM 0.7V TO 2.2V. Figure 2. Rev. 0 | Page 7 of 28 + PGND – VCCO 50µA ILIM 10594-002 – + + + FB TRK SS ADP1853 Data Sheet 20 19 18 17 16 TRK FREQ RAMP PGOOD ILIM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 ADP1853 TOP VIEW 15 14 13 12 11 BST DH SW CS DL NOTES 1. CONNECT THE BOTTOM OF THE EXPOSED PAD TO THE SYSTEM AGND PLANE. 10594-003 SYNC 6 CLKOUT 7 VIN 8 VCCO 9 PGND 10 EN SS FB COMP AGND Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic EN 2 SS 3 FB 4 COMP 5 6 AGND SYNC 7 CLKOUT 8 VIN 9 VCCO 10 11 PGND DL 12 CS 13 SW 14 DH 15 BST 16 ILIM Description Enable Input. Drive EN high to turn on the controller, and drive EN low to turn the controller off. Tie EN to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND, and tie the midpoint to this pin. Soft Start Input. Connect a capacitor from SS to AGND to set the soft start period. This node is internally pulled up to VCCO through a 6.5 µA current source. Output Voltage Feedback. Connect this pin to an output via a resistor divider. Tie FB to VCCO for slave mode operation in interleaved dual-phase configuration. Compensation Node. Output of the error amplifier. Connect a resistor-capacitor network from COMP to FB to compensate the regulation control loop. In interleaved dual-phase configuration, tie this pin to the COMP pin of the second channel. Analog Ground. Connect to the system AGND plane. Frequency Synchronization Input. This pin accepts an external clock signal with a frequency close to 1× the internal oscillator frequency, fOSC, set by the FREQ pin. The controller operates in forced PWM when a periodic clock signal is detected at SYNC or when SYNC is high. The resulting switching frequency is 1× the SYNC frequency. When SYNC is low or left floating, the controller operates in pulse skip mode. Internal Clock Output. The CLKOUT is 1× the internal oscillator or input SYNC signal frequency, 180° phase-shifted. This pin can be used to synchronize another ADP1853 or other controllers. Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as possible and AGND. Output of the Internal Low Dropout Regulator (LDO). The internal circuitry and gate drivers are powered from VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output remains active even when EN is low. For operations at VIN below 5 V, VIN may be jumped to VCCO. Do not use the LDO to power other auxiliary system loads. Power Ground. Ground for internal driver. Differential current. Low-Side Synchronous Rectifier Gate Driver Output. To program the gain of the current sense amplifier in a current mode or to set voltage mode control, connect a resistor between DL and PGND. This pin is capable of driving MOSFETs with a total input capacitance up to 20 nF. Current Sense Amplifier Input. Differential current is sensed between CS and PGND. Connect this pin to the current sense resistor or to the SW pin to sense the current. Tie this pin to PGND for voltage mode operation. Power Switch Node. Connect this pin to the source of the high-side N-channel MOSFET and the drain of the lowside N-channel MOSFET. High-Side Switch Gate Driver Output. This pin is capable of driving MOSFETs with a total input capacitance up to 20 nF. Boot Strapped Upper Rail of High-Side Internal Driver. Connect a 0.1 µF to a 0.22 µF multilayer ceramic capacitor (MLCC) between BST and SW. There is an internal boost diode rectifier connected between VCCO and BST. Current-Limit Sense Comparator Inverting Input. Connect a resistor between ILIM and SW to set the currentlimit offset. For accurate current-limit sensing, connect ILIM to a current sense resistor at the source of the low-side MOSFET. Rev. 0 | Page 8 of 28 Data Sheet Pin No. 17 Mnemonic PGOOD 18 RAMP 19 FREQ 20 TRK EPAD ADP1853 Description Power Good. The open-drain power good indicator logic output with an internal 12.5 kΩ resistor is connected between PGOOD and VCCO. PGOOD is pulled to ground when the output is outside the regulation window. An external pull-up resistor is not required. If the controller is configured as a slave in the interleaved dual-phase application by tying the FB pin high to VCCO, the pulse skip mode is enabled by driving the PGOOD pin low externally in cases when the master is in pulse skip mode at light loads. Otherwise, if the master is configured to forced PWM operation, PGOOD of the slave controller must be connected to the PGOOD of the master. Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to VIN. The voltage at RAMP is 0.2 V during operation. This pin is high impedance when the channel is disabled. Internal Oscillator Frequency, fOSC. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or tie FREQ to VCCO for 600 kHz operating frequency. Tracking Input. Connect TRK to VCCO if tracking is not used. Exposed Pad. Connect the bottom of the exposed pad to the system AGND plane. Rev. 0 | Page 9 of 28 ADP1853 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 60 50 40 30 30 20 20 10 10 PULSE SKIP FORCED PWM 1 10 100 LOAD (A) 10594-004 0 0.1 PULSE SKIP FORCED PWM 0 0.1 1 10 100 LOAD (A) Figure 4. Efficiency Plot 12 VIN to 3.3 VOUT, 300 kHz, see Figure 36 for Circuit Figure 7. Efficiency Plot 15 VIN to 5 VOUT, 600 kHz, see Figure 35 for Circuit LOAD CURRENT LOAD CURRENT 4 4 2 VOUT_AC VOUT_AC A CH4 14.2A CH2 200mV BW CH4 10A Ω BW Figure 5. 10 A to 20 A Load Step, 12 VIN to 3.3 VOUT, 300 kHz, Current Mode M 100µs 5.0MS/s 200ns/pt A CH4 14.2A 10594-007 M 100µs 5.0MS/s 200ns/pt 12.6V 10594-009 CH2 200mV BW CH4 10A Ω BW 10594-006 2 Figure 8. 10 A to 20 A Load Step, 12 VIN to 3.3 VOUT, 300 kHz, Voltage Mode VIN VIN 1 1 VOUT_AC VOUT_AC 2 CH1 5V CH2 100mV B W B W M 100µs 250MS/s 4ns/pt A CH1 12.6V 10594-008 2 CH1 5V CH2 100mV Figure 6. 9 V to 15 V Line Step, 3.3 VOUT, 15 A Load, Current Mode B W B W M 100µs 250MS/s 4ns/pt A CH1 Figure 9. 9 V to 15 V Line Step, 3.3 VOUT, 15 A Load, Voltage Mode Rev. 0 | Page 10 of 28 10594-005 EFFICIENCY (%) 100 Data Sheet ADP1853 EN 1 SYNC 1 SW 3 DH 3 CLKOUT VOUT 2 W CH2 5V M 1.0µs 1.25GS/s 400ps/pt B W B W A CH1 3.6V 2 CH1 2V CH3 10V Figure 10. Synchronization and CLKOUT, fSYNC = 300 kHz W B W CH2 1V B W M 2ms 250kS/s 4µs/pt A CH1 560mV Figure 13. Soft Start with Precharged Output, 3.3 VOUT Forced PWM 35 45 VIN = 12V 34 OUTPUT IS LOADED HS FET = BSC080N03LS 33 LS FET = BSC030N03LS TA = 25°C OUTPUT IS LOADED HS FET = BSC080N03LS LS FET = BSC030N03LS 43 41 32 30 29 37 35 33 28 31 27 29 26 27 DEAD TIME BETWEEN SW FALLING EDGE AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME 25 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) DEAD TIME BETWEEN SW FALLING EDGE AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME 25 0 5 10 15 20 VIN (V) 10594-014 DEAD TIME (ns) 39 31 10594-011 DEAD TIME (ns) B 10594-017 B 10594-016 CH1 5V CH3 10V Figure 14. Dead Time vs. VIN Figure 11. Dead Time vs. Temperature 350 4.5 4.0 300 DH MINIMUM OFF TIME DRIVER RESISTANCE (Ω) 3.5 200 150 3.0 VIN = 12V, SOURCING 2.5 VIN = 2.75V, SINKING 2.0 1.5 VIN = 12V, SINKING 1.0 100 DH MINIMUM ON TIME 5.0 7.5 10.0 12.5 15.0 0.5 17.5 VIN (V) 20.0 0 –40 –15 10 35 60 85 110 TEMPERATURE (°C) Figure 15. Driver Resistance vs. Temperature Figure 12. Typical DH Minimum On Time and Off Time Rev. 0 | Page 11 of 28 135 10594-015 50 2.5 10594-012 TIME (ns) 250 VIN = 2.75V, SOURCING ADP1853 Data Sheet THEORY OF OPERATION The ADP1853 is a fixed frequency, step-down, synchronous switching controller with integrated drivers and bootstrapping for external N-channel power MOSFETs. The current mode control loop can also be configured into the voltage mode. The controller can be set to operate in pulse skip mode for power saving at a light load or in forced PWM. The ADP1853 includes programmable soft start, output overvoltage protection, programmable current limit, power good, and tracking functions. The controller can operate at a switching frequency between 200 kHz and 1.5 MHz that is programmed with a resistor or synchronized to an external clock. It also has the internal clock out signal that can be used to synchronize other devices. CONTROL ARCHITECTURE The ADP1853 is based on a fixed frequency, emulated peak current mode, PWM control architecture. The inductor current is sensed by the voltage drop measured across the external lowside MOSFET, RDSON, or across the sense resistor placed in series between the low-side MOSFET source and the power ground. The current is sensed during the off period of the switching cycle and is conditioned with the internal current sense amplifier. The gain of the current sense amplifier is programmable to 3 V/V, 6 V/V, or 12 V/V during the controller power-up initialization before the device starts switching. A 47 kΩ resistor between DL and PGND programs the gain of 3 V/V; a 22 kΩ resistor sets a gain of 6 V/V. Without a resistor, the gain is programmed to 12 V/V. The output signal of the current sense amplifier is held, added to the emulated current ramp in the next switching cycle during the DH on time, and fed into the PWM comparator, as shown in Figure 16. This signal is compared with the COMP signal from the error amplifier and resets the flip-flop, which generates the PWM pulse. If voltage mode control is selected by placing a 100 kΩ resistor between DL and PGND, the emulated ramp is fed to the PWM comparator without adding the current sense signal. OSC VIN FF RRAMP R The internal oscillator frequency, which ranges from 200 kHz to 1.5 MHz, is set by an external resistor, RFREQ, at the FREQ pin. Some popular fOSC values are shown in Table 4, and a graphical relationship is shown in Figure 17. For instance, a 78.7 kΩ resistor sets the oscillator frequency to 800 kHz. Furthermore, connecting FREQ to AGND or FREQ to VCCO sets the oscillator frequency to 300 kHz or 600 kHz, respectively. For other frequencies that are not listed in Table 4, the values of RFREQ and fOSC can be obtained from Figure 17, or use the following empirical formula to calculate these values: RFREQ (kΩ) = 96,568 × fOSC (kHz )−1.065 Table 4. Setting the Oscillator Frequency RFREQ 332 kΩ 78.7 kΩ 60.4 kΩ 51 kΩ 40.2 kΩ FREQ to AGND FREQ to VCCO fOSC (Typical) 200 kHz 800 kHz 1000 kHz 1200 kHz 1500 kHz 300 kHz 600 kHz 410 RFREQ (kΩ) = 96,568 fOSC (kHz)–1.065 360 310 TO DRIVERS Q AR 260 210 160 110 CR 60 CS 10 100 ACS PGND FROM ERROR AMP 10594-022 VCS Figure 16. Simplified Control Architecture Rev. 0 | Page 12 of 28 400 700 1000 1300 fOSC (kHz) Figure 17. RFREQ vs. fOSC 1600 1900 10594-023 IRAMP Q S OSCILLATOR FREQUENCY RFREQ (kΩ) VIN As shown in Figure 16, the emulated current ramp is generated inside the IC, but offers programmability through the RAMP pin. Selecting an appropriate value resistor between VIN to the RAMP pin programs a desired slope compensation value, and at the same time, provides a VIN feed forward feature. Control logic enforces antishoot-through operation to limit cross conduction of the internal drivers and external MOSFETs. Data Sheet ADP1853 SYNCHRONIZATION The switching frequency of the ADP1853 can be synchronized to an external clock signal by connecting it to the SYNC pin. The internal oscillator frequency, programmed by the resistor at the FREQ pin must be set close to the external clock frequency; therefore, the external clock frequency may vary between 0.85× and 1.3× of the internal clock set. The resulting switching frequency is 1× of the external SYNC frequency. When synchronized, the ADP1853 operates in PWM. PWM OR PULSE SKIP MODE OF OPERATION COMP (CH2) VOUT RIPPLE 3 INDUCTOR CURRENT 4 2 CH1 10V CH3 20mV CH2 200mV CH4 2A Ω M200µs A CH1 7.8V 10594-024 When an external clock is detected at the first SYNC edge, the internal oscillator is reset, and the clock control shifts to SYNC. The SYNC edges then trigger subsequent clocking of the PWM outputs. The DH rising edge appears approximately 100 ns after the corresponding SYNC edge, and the frequency is locked to the external signal. If the external SYNC signal disappears during operation, the ADP1853 reverts to its internal oscillator. When the SYNC function is used, it is recommended to connect a pull-up resistor from SYNC to VCCO so that when the SYNC signal is lost, the ADP1853 continues to operate in PWM. SW 1 Figure 18. Example of Pulse Skip Mode Under a Light Load When the output load is greater than the pulse skip threshold current, that is, when VCOMP reaches the threshold of 0.9 V, the ADP1853 exits the pulse skip mode of operation and enters the fixed frequency discontinuous conduction mode (DCM), as shown in Figure 19. When the load increases further, the ADP1853 enters continuous conduction mode (CCM). The SYNC pin is a multifunctional pin. PWM mode is enabled when SYNC is connected to VCCO or a high logic. With SYNC connected to ground or left floating, pulse skip mode is enabled. Switching SYNC from low to high or high to low on the fly causes the controller to transition from forced PWM to pulse skip mode or from pulse skip mode to forced PWM, respectively, in two clock cycles. DH 1 DL 2 OUTPUT RIPPLE 3 Table 5. Mode of Operation Mode of Operation Pulse skip mode Forced PWM Pulse skip mode Forced PWM 4 INDUCTOR CURRENT CH1 10V CH3 20mV CH2 5V CH4 2A Ω M1µs A CH1 13.4V 10594-025 SYNC Pin Low High No Connect Clock Signal Figure 19. Example of Discontinuous Conduction Mode (DCM) Waveform The ADP1853 has pulse skip sensing circuitry that allows the controller to skip PWM pulses, reducing the switching frequency at light loads and, therefore, maintaining better efficiency during a light load operation. The resulting output ripple is larger than that of the fixed frequency forced PWM. Figure 18 shows the ADP1853 operating in PSM under a light load. Pulse skip frequency under a light load is dependent on the inductor, output capacitance, output load, and input and output voltages. In forced PWM, the ADP1853 always operates in CCM at any load; therefore, the inductor current is always continuous. CLKOUT SIGNAL The ADP1853 has a clock output, CLKOUT, which can be used for synchronizing other ADP1853 controllers, thus eliminating the need for an external clock source. The CLKOUT frequency is 1× the internal oscillator frequency, fOSC, and is 180° out of phase. Rev. 0 | Page 13 of 28 ADP1853 Data Sheet SYNCHRONOUS RECTIFIER AND DEAD TIME VIN = 2.75V TO 5.5V When the bias input voltage at the VIN pin is less than the undervoltage lockout (UVLO) threshold of 2.6 V typical, the switch drivers stay inactive. If EN is high, the controller starts switching and the VIN pin voltage exceeds the UVLO threshold. INTERNAL LINEAR REGULATOR The internal linear regulator is a low dropout (LDO) VCCO. VCCO powers up the internal control circuitry and provides power for the gate drivers. It is guaranteed to have more than 200 mA of output current capability, which is sufficient to handle the gate driver requirements of typical logic threshold MOSFETs driven at up to 1.5 MHz. VCCO is always active and cannot be shut down by the EN signal; however, the overtemperature protection event disables the LDO together with the controller. Bypass VCCO to AGND with a 1 µF or greater capacitor. VCCO ADP1853 Figure 20. Configuration for VIN < 5.5 V OVERVOLAGE PROTECTION The ADP1853 has a built-in circuit for detecting output overvoltage at the FB node. When the FB voltage, VFB, rises above the overvoltage threshold, the high-side N-channel MOSFET (NMOSFET) is turned off, and the low-side NMOSFET is turned on until the VFB drops below the undervoltage threshold. This action is known as the crowbar overvoltage protection. If the overvoltage condition is not removed, the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds, and the output is regulated to within typically +8% and −8% of the regulation voltage. During an overvoltage event, the SS node discharges toward zero through an internal 3 kΩ pull-down resistor. When the voltage at FB drops below the undervoltage threshold, the soft start sequence restarts. Figure 21 shows the overvoltage protection scheme in action in PSM. DH 1 PGOOD 2 VOUT = 1.8V SHORTED TO 2V SOURCE Because the LDO supplies the gate driver current, the output of VCCO is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. The LDO has been optimized to handle these transients without overload faults. Due to the gate drive loading, using the VCCO output for other external auxiliary system loads is not recommended. 3 VIN 4 CH1 20V CH3 1V CH2 5V CH4 10V M100µs A CH1 10V 10594-027 INPUT UNDERVOLTAGE LOCKOUT VIN 10594-026 In the ADP1853, the antishoot-through circuit monitors the DH to SW and DL to PGND voltages and adjusts the low-side and high-side drivers to ensure break-before-make switching that prevents cross-conduction or shoot-through between the high-side and low-side MOSFETs. This break-before-make switching is known as dead time, which is not fixed and depends on how fast the MOSFETs are turned on and off. In a typical application circuit that uses medium sized MOSFETs with an input capacitance of approximately 3 nF, the typical dead time is approximately 25 ns. When small and fast MOSFETs with fast diode recovery times are used, the dead time can be as low as 13 ns. Figure 21. Overvoltage Protection in PSM POWER GOOD The LDO includes a current limit that is well above the expected maximum gate driver load. This current limit also includes a short-circuit foldback to further limit the VCCO current in the event of a short-circuit fault. For an input voltage of less than 5.5 V, it is recommended to bypass the LDO by connecting VIN to VCCO, as shown in Figure 20, thus eliminating the dropout voltage. However, if the input range is 4 V to 7 V, the LDO cannot be bypassed by shorting VIN to VCCO because the 7 V input has exceeded the maximum voltage rating of the VCCO pin. In this case, use the LDO to drive the internal drivers, but keep in mind that there is a dropout when VIN is less than 5 V. The PGOOD pin is an open-drain NMOSFET with an internal 12.5 kΩ pull-up resistor connected between PGOOD and VCCO. PGOOD is internally pulled up to VCCO during normal operation and is active low when tripped. When the feedback voltage, VFB, rises above the overvoltage threshold or drops below the undervoltage threshold, the PGOOD output is pulled to ground after a delay of 12 µs. The overvoltage or undervoltage condition must exist for more than 10 µs for PGOOD to become active. The PGOOD output also becomes active if a thermal overload condition is detected. Rev. 0 | Page 14 of 28 Data Sheet ADP1853 SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION ENABLE/DISABLE CONTROL When the output is shorted or the output current exceeds the current limit set by the current-limit setting resistor (between ILIM and CS) for eight consecutive cycles, the ADP1853 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. The SS node discharges to zero through an internal 3 kΩ resistor during an overcurrent or short-circuit event. Figure 22 shows that the ADP1853 on a high current application circuit maintains current-limit hiccup mode when the output is shorted. The EN pin is used to enable or disable the controller ADP1853; the precision enable typical threshold is 0.63 V. When the voltage at EN rises above the threshold voltage, the controller is enabled and starts normal operation after initialization of the internal oscillator, references, settings, and the soft start period. When the voltage at EN drops to typically 30 mV (hysteresis) below the threshold voltage, the driver and the internal controller circuits in the ADP1853 are turned off. The initial settings are still valid; therefore re-enabling the controller does not change the settings until the power at the VIN pin is cycled. In addition, the EN signal does not shut down the LDO at VCCO, which is always active when VIN is above the UVLO threshold. For the purpose of start-up power sequencing, the startup of the ADP1853 can be programmed by connecting an appropriate resistor divider from the master power supply to the EN pin, as shown in Figure 23. For instance, if the desired start-up voltage from the master power supply is 10 V, R1 and R2 can be set to 156 kΩ and 10 kΩ, respectively. 1 SW SS 3 MASTER SUPPLY VOLTAGE INDUCTOR CURRENT VOUT 4 M2ms A CH1 11.2V CH4 10A Ω ADP1853 EN R2 Figure 22. Current-Limit Hiccup Mode, 20 A Current Limit RTOP FB RBOT 10594-029 CH1 10V CH3 500mV 10594-028 R1 Figure 23. Optional Power-Up Sequencing Circuit Rev. 0 | Page 15 of 28 ADP1853 Data Sheet THERMAL OVERLOAD PROTECTION VIN RRAMP The ADP1853 has an internal temperature sensor that senses the junction temperature of the chip. When the junction temperature of the ADP1853 reaches approximately 155°C, the ADP1853 goes into thermal shutdown, the converter is turned off, and SS discharges toward zero through an internal 3 kΩ resistor. At the same time, VCCO discharges to zero. When the junction temperature drops below 135°C, the ADP1853 resumes normal operation after the soft start sequence. INTERLEAVED DUAL-PHASE OPERATION Two ADP1853 controllers can be configured to design a dual-phase, interleaved, step-down, switching dc-to-dc regulators. In dual-phase operation, the two outputs of the switching regulators are tied together and can source more than 50 A of output current depending on the selection of the power components. See Figure 24 for a configuration of a typical dual-phase application circuit. Note that only one error amplifier, in the master ADP1853, works; the error amplifier in the slave ADP1853 output is turned to tristate by tying FB to VCCO. The CLKOUT signal from the master is connected to the SYNC input of the slave controller; the SS signals of the master and slave are tied together; COMP of the slave must be tied to COMP of the master; and PGOOD of the slave must be tied to PGOOD of the master. VIN RAMP EN M1 TRK ADP1853 MASTER M2 DL RCSG SYNC FREQ PGND FB SS COMP PGOOD CLKOUT AGND VIN RRAMP VIN RAMP EN VCCO ADP1853 SLAVE L2 SW CS ILIM M4 DL RCSG SYNC PGND COMP FB PGOOD CLKOUT 10594-030 AGND M3 DH BST TRK SS VOUT SW CS ILIM VCCO FREQ L1 DH BST Figure 24. Dual-Phase Application Rev. 0 | Page 16 of 28 Data Sheet ADP1853 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL The ADP1853 is supported by the ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized to a specific design goal. The tools allow the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the IC and all real external components. The ADIsimPower tool can be found at www.analog.com/ADIsimPower and the user can request an unpopulated board through the tool. SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB. For RBOT, use a 1 kΩ to 20 kΩ resistor. Choose RTOP to set the output voltage by using the following equation: V − VFB RTOP = R BOT OUT VFB where: RTOP is the high-side voltage divider resistance. RBOT is the low-side voltage divider resistance. VOUT is the regulated output voltage. VFB is the feedback regulation threshold, 0.6 V. The current limit is set by an external current-limit resistor, RILIM, between ILIM and CS. The current sense pin, ILIM, sources nominally 50 μA to this external resistor. This creates an offset voltage of RILIM multiplied by 50 μA. When the drop across the current sense element RCS (a sense resistor or lowside MOSFET, RDSON) is equal to or greater than this offset voltage, the ADP1853 flags a current-limit event. R ILIM = 1.06 × I LPK × RCS where: ILPK is the peak inductor current. ACCURATE CURRENT-LIMIT SENSING RDSON of the MOSFET can vary by more than 50% over the temperature range. Accurate current-limit sensing is achieved by adding a current sense resistor from the source of the lowside MOSFET to PGND. Make sure that the power rating of the current sense resistor is adequate for the application. Figure 25 illustrates the implementation of accurate current-limit sensing. VIN ADP1853 DH CS RILIM ILIM SOFT START 0.6 V 6.5 μA C SS The SS pin reaches a final voltage equal to VCCO. When a controller is disabled, for instance, if EN is pulled low or experiences an overcurrent limit condition, the soft start capacitor is discharged through an internal 3 kΩ pull-down resistor. SETTING THE CURRENT LIMIT The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. RSENSE 10594-031 DL The soft start period is set by an external capacitor between SS and AGND. The soft start function limits the input inrush current and prevents output overshoot. When EN is enabled, a current source of 6.5 µA starts charging the capacitor, and the regulation voltage is reached when the voltage at SS reaches 0.6 V. The soft start time is approximated by t SS = 50 μA Figure 25. Accurate Current-Limit Sensing INPUT CAPACITOR SELECTION Use two parallel capacitors placed close to the drain of the highside switch MOSFET (one bulk capacitor of sufficiently high current rating and a 10 μF ceramic decoupling capacitor). Select an input bulk capacitor based on its ripple current rating. The minimum input capacitance required for a particular load is C IN , MIN = I O × D(1 − D) (VPP − I O × DR ESR ) f SW where: IO is the output current. D is the duty cycle. VPP is the desired input ripple voltage. RESR is the equivalent series resistance of the capacitors. Rev. 0 | Page 17 of 28 ADP1853 Data Sheet VIN PIN FILTER OUTPUT CAPACITOR SELECTION It is recommended to have a low-pass filter at the VIN pin. Connecting a resistor, between 2 Ω and 10 Ω, in series with VIN and a 1 µF ceramic capacitor between VIN and AGND creates a low-pass filter that effectively filters out any unwanted glitches caused by the switching regulator. Keep in mind that the input current could be larger than 100 mA when driving large MOSFETs. A 100 mA across a 10 Ω resistor creates a 1 V drop, which is the same voltage drop in VCCO. In this case, a lower resistor value is desirable. For maximum allowed switching ripple at the output, choose an output capacitor that is larger than 2Ω TO 10Ω VIN ADP1853 VIN AGND 10594-032 1µF Figure 26. Input Filter Configuration BOOST CAPACITOR SELECTION Connect a boost capacitor between the SW and BST pins to provide the current for the high-side driver during switching. Choose a ceramic capacitor with a value between 0.1 µF and 0.22 µF. INDUCTOR SELECTION For most applications, choose an inductor value such that the inductor ripple current is between 20% and 40% of the maximum dc output load current. ∆I L 1 × 2 2 8 f SW ∆VOUT − ∆I L × (R ESR 2 − (4 f SW × LESL )2 ) where: ∆VOUT is the target maximum output ripple voltage. ∆IL is the inductor ripple current. RESR is the equivalent series resistance of the output capacitor (or the parallel combination of ESR of all output capacitors). LESL is the equivalent series inductance of the output capacitor (or the parallel combination of ESL of all capacitors). The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (ESR), and the equivalent series inductance (ESL). Usually the capacitor impedance is dominated by ESR. The maximum ESR rating of the capacitor, such as in electrolytic or polymer capacitors, is provided in the manufacturer’s data sheet; therefore, the output ripple reduces to ∆VOUT ≅ ∆I L × RESR Electrolytic capacitors also have significant ESL, on the order of 5 nH to 20 nH, depending on type, size, and geometry. PCB traces contribute some ESR and ESL, as well. However, using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL may not be required. Choose the inductor value by the following equation: L= COUT ≅ V IN − VOUT VOUT × f SW × ∆I L V IN where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. VIN is the input voltage. ∆IL is the peak-to-peak inductor ripple current. In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates, so the output capacitance must be larger than Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. COUT ≅ ∆I L 8 ∆VOUT × f SW Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. To meet the requirement of the output voltage overshoot during load release, the output capacitance should be larger than COUT ≅ (VOUT ∆I STEP 2 L + ∆VOVERSHOOT )2 − VOUT 2 where: ∆VOVERSHOOT is the maximum allowed overshoot. Select the largest output capacitance given by either of the previous two equations. Rev. 0 | Page 18 of 28 Data Sheet ADP1853 MOSFET SELECTION If QGSW is not given in the data sheet, it can be approximated by The choice of MOSFET directly affects the dc-to-dc converter performance. A MOSFET with low on resistance reduces I2R losses, and low gate charge reduces transition losses. The MOSFET should have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature. The high-side MOSFET carries the load current during on time and usually carries most of the transition losses of the converter. Typically, the lower the on resistance of the MOSFET, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances the two losses. The conduction loss of the high-side MOSFET is determined by the equation PC = (I LOAD( RMS ) )2 × R DSON where: RDSON is the MOSFET on resistance. The gate charging loss is approximated by the equation PG ≅ VPV × QG × f SW where: VPV is the gate driver supply voltage. QG is the MOSFET total gate charge. Note that the gate charging power loss is not dissipated in the MOSFET but rather in the ADP1853 internal drivers. This power loss should be taken into consideration when calculating the overall power efficiency. The high-side MOSFET transition loss is approximated by the equation PT ≅ VIN × I LOAD × (t R + t F ) × f SW 2 where: PT is the high-side MOSFET switching loss power. tR is the rise time in charging the high-side MOSFET. tF is the fall time in discharging the high-side MOSFET. tR and tF can be estimated by tR ≅ tF ≅ Q GSW I DRIVER _ RISE Q GSW ≅ Q GD + Q GS 2 where: QGD and QGS are the gate-to-drain and gate-to-source charges given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL can be estimated by I DRIVER _ RISE ≅ VDD − VSP RON _ SOURCE + RGATE I DRIVER _ FALL ≅ VSP RON _ SINK + RGATE where: VDD is the input supply voltage to the driver and is between 2.75 V and 5 V, depending on the input voltage. VSP is the switching point where the MOSFET fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the MOSFET data sheet. RON_SOURCE is the on resistance of the ADP1853 internal driver, given in Table 1, when charging the MOSFET. RON_SINK is the on resistance of the ADP1853 internal driver, given in Table 1, when discharging the MOSFET. RGATE is the on gate resistance of MOSFET given in the MOSFET data sheet. If an external gate resistor is added, add this external resistance to RGATE. The total power dissipation of the high-side MOSFET is the sum of conduction and transition losses: PHS ≅ PC + PT The synchronous rectifier, or low-side MOSFET, carries the inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in the calculation. For high input voltage and low output voltage, the low-side MOSFET carries the current most of the time. Therefore, to achieve high efficiency, it is critical to optimize the low-side MOSFET for low on resistance. In cases where the power loss exceeds the MOSFET rating or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel. The equation for low-side MOSFET conduction power loss is PCLS = ( I LOAD( RMS ) )2 × R DSON Q GSW I DRIVER _ FALL where: QGSW is the gate charge of the MOSFET during switching and is given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL are the driver current output from the ADP1853 internal gate drivers. Rev. 0 | Page 19 of 28 ADP1853 Data Sheet There is also additional power loss during the time, known as dead time, between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the lowside MOSFET conducts the output current. The power loss in the body diode is given by Type III Compensation Note that MOSFET on resistance, RDSON, increases with increasing temperature with a typical temperature coefficient of 0.4%/oC. The MOSFET junction temperature (TJ) rise over the ambient temperature is fP fZ CHF RFF CFF RZ CI RTOP RBOT FB EA COMP INTERNAL VREF 10594-033 VOUT If the output capacitor ESR zero frequency is greater than ½ of the crossover frequency, use the Type III compensator as shown in Figure 27. Calculate the output LC filter resonant frequency as follows: f LC = TJ = TA + θJA × PD where: θJA is the thermal resistance of the MOSFET package. TA is the ambient temperature. PD is the total power dissipated in the MOSFET. 1 2π LC (2) Chose a crossover frequency that is 1/10 of the switching frequency: fCO = LOOP COMPENSATION—VOLTAGE MODE f SW 10 (3) Set the poles and zeros as follows: Set the controller to voltage mode operation by placing a 100 kΩ resistor between DL and PGND. Chose the larger possible ramp amplitude for the voltage mode below 1.5 V. The ramp voltage is programmed by a resistor value between VIN and the RAMP pin: VIN − 0.2 V f P1 = f P2 = 1 f SW 2 (4) f Z1 = f Z2 = fCO f SW 1 = = 4 40 2πRZ C I (5) f Z1 = f Z2 = f LC 1 = 2 2πRZ C I (6) or 100 pF × f SW × VRAMP The voltage at the RAMP pin is fixed at 0.2 V, and the current going into RAMP should be between 10 µA and 160 µA. Make sure that the following condition is satisfied: ≤ 160 μA PE Figure 27. Type III Compensation PLS = PCLS + PBODYDIODE RRAMP –1 SL O –270° Then the power loss in the low-side MOSFET is VIN − 0.2 V PE PHASE where: VF is the forward voltage drop of the body diode, typically 0.7 V. tD is the dead time in the ADP1853, typically 30 ns when driving a medium size MOSFETs with input capacitance, Ciss, of approximately 3 nF. The dead time is not fixed. Its effective value varies with gate drive resistance and Ciss; therefore, PBODYDIODE increases in high load current designs and low voltage designs. 10 μA ≤ O SL +1 PE –90° PBODYDIODE = VF × t D × f SW × I O RRAMP = –1 SL O G (dB) Use the lower zero frequency from Equation 5 or Equation 6. Calculate the compensator resistor, RZ, as follows: (1) For instance, with an input voltage of 12 V, RRAMP should not be less than 73.8 kΩ. Assuming that the LC filter design is complete, the feedback control system can be compensated. In general, aluminum electrolytic capacitors have high ESR; however, if several aluminum electrolytic capacitors are connected in parallel and produce a low effective ESR, then Type III compensation is needed. In addition, ceramic capacitors have very low ESR (only a few milliohms) making Type III compensation a better choice. RZ = RTOP V RAMP f Z1 f CO V IN f LC 2 (7) Next, calculate CI: CI = 1 2πR Z f Z1 (8) Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. Rev. 0 | Page 20 of 28 Data Sheet ADP1853 Because CHF << CI, calculate CHF as follows: 1 πf SW R Z (9) Next, calculate the feedforward capacitor, CFF, assuming RFF << RTOP: R FF = 1 πC FF f SW (10) Check that the calculated component values are reasonable. For instance, capacitors smaller than about 10 pF should be avoided. In addition, RZ values less than 3 kΩ and CI values greater than 10 nF should be avoided. If necessary, recalculate the compensation network with a different starting value for RTOP. If RZ is too small or CI is too big, start with a larger value for RTOP. This compensation technique should yield a good working solution. 10 μA ≤ ≤ 160 μA Figure 28 illustrates the connection of the slope compensation resistor, RRAMP, and the current sense gain resistor, RCSG. LOOP COMPENSATION—CURRENT MODE VIN RRAMP RAMP ADP1853 DH CS RILIM ILIM DL Compensate the ADP1853 error voltage loop in current mode using Type II compensation. RCSG Figure 28. Slope Compensation and CS Gain Connection Setting the Slope Compensation In a current-mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. The external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the RAMP pin. To set the effective slope compensation, connect a resistor (RRAMP) between the RAMP pin and the input voltage (VIN). RRAMP is calculated by 7 ×106 × L ACS × RCS where: L is the inductor value measured in µH. RCS (mΩ) is resistance of the current sense element between CS and PGND (for instance, RDSON_MAX is the low-side MOSFET maximum on resistance). ACS is the current sense amplifier gain and is 3 V/V, 6 V/V, or 12 V/V. Thus, the voltage ramp amplitude, VRAMP, is: VRAMP = RRAMP For instance, with an input voltage of 12 V, RRAMP should not exceed 1.1 MΩ. If the calculated RRAMP produces less than 10 µA, then select an RRAMP value that produces between 10 µA and 15 µA. When precise compensation is needed, use the ADIsimPower design tool. RRAMP = VIN − 0.2 V 10594-034 C HF = The voltage at the RAMP pin is fixed at 0.2 V, and the current going into RAMP should be between 10 µA and 160 µA. Make sure that the following condition is satisfied: VIN − 0.2 V 100 pF × f SW × R RAMP where 100 pF is the effective capacitance of the internal ramp capacitor, CRAMP, with ±4% tolerance over the temperature and VIN range. Rev. 0 | Page 21 of 28 ADP1853 Data Sheet Type II Compensation The voltage drop across the external low-side MOSFET is sensed by a current sense amplifier by multiplying the peak inductor current and the RDSON of the MOSFET. The result is then amplified by a gain factor of 3 V/V, 6 V/V, or 12 V/V, which is programmable by an external resistor, RCSG, connected to the DL pin. This gain is sensed only during power-up and not during normal operation. The amplified voltage is summed with the slope compensation ramp voltage and fed into the PWM controller for a stable regulation voltage. The voltage range of the internal node, VCS, is between 0.4 V and 2.2 V. Select the current sense gain such that the internal minimum amplified voltage (VCSMIN) is above 0.4 V and the maximum amplified voltage (VCSMAX) is 2.1 V. Note that VCSMIN or VCSMAX is not the same as VCOMP, which has a range of 0.85 V to 2.2 V. Make sure that the maximum VCOMP (VCOMPMAX) does not exceed 2.2 V to account for temperature and part-to-part variations. See the following equations for VCSMIN, VCSMAX, and VCOMPMAX: VCSMIN 0.75 V 1 I L R DSON _ MIN ACS 2 VCSMAX 0.75 V ( I LOADMAX VCOMPMAX (VIN 0.2 V) t ON 100 pF RRAMP G (dB) –1 S LO PE –1 S fZ PHASE LO PE fP –180° –270° CHF RZ VOUT CI RTOP FB RBOT EA COMP INTERNAL VREF 10594-035 Setting the Current Sense Gain Figure 29. Type II Compensation In this case, use the circuit shown in Figure 29. Calculate the compensation resistor, RZ, with the following equation: RZ RTOP RS 2 COUT f CO (11) where: fCO is chosen to be 1/10 of fSW. RS = ACS × RDSON_MIN. ACS is the current sense gain of either 3 V/V, 6 V/V, or 12 V/V, set by the gain resistor between DL and PGND. RDSON_MIN is the low-side MOSFET minimum on resistance. 1 I L ) R DSON _ MAX ACS 2 VCSMAX where: VCSMIN is the minimum amplified voltage of the internal current sense amplifier at zero output current. IL is the peak-to-peak ripple current in the inductor. RDSON_MIN is the low-side MOSFET minimum on resistance. The zero current level voltage of the current sense amplifier is 0.75 V. VCSMAX is the maximum amplified voltage of the internal current sense amplifier at the maximum output current. ILOADMAX is the maximum output dc load current. VCOMPMAX is the maximum voltage at the COMP pin. tON is the high-side driver (DH) on time. If the current is sensed on a current sense resistor, RCS, then RCS becomes RS ACS RCS Next, choose the compensation capacitor to set the compensation zero, fZ1, to the lesser of 1/5 of the crossover frequency or ½ of the LC resonant frequency f Z1 f CO f SW 1 5 50 2RZ C I (12) f Z1 f LC 1 2 2RZ C I (13) or Replace RDSON with the resistance value of the current sense element, RCS, if it is used. Solving for CI in Equation 12 yields CI 25 RZ f SW (14) Solving for CI in Equation 13 yields CI Rev. 0 | Page 22 of 28 1 RZ f LC (15) Data Sheet ADP1853 Use the larger value of CI from Equation 14 or Equation 15. Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. Next, choose the high frequency pole, fP1, to be ½ of fSW. (16) Because CHF << CI, f P1 = 1 2πR Z C HF (17) Coincident Tracking Combine Equation 16 and Equation 17, and solve for CHF, C HF = 1 πf SW R Z Two tracking configurations are possible with the ADP1853: coincident and ratiometric tracking. (18) For maximally precise compensation solutions, use the ADIsimPower design tool. SWITCHING NOISE AND OVERSHOOT REDUCTION To reduce voltage ringing and noise, it is recommended to add an RC snubber between SW and PGND for high current applications, as illustrated in Figure 30. The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking forces the ramp rate of the output voltage to be the same for the master and slave until the slave output reaches its regulation. Connect the slave TRK input to a resistor divider from the master voltage that is the same as the divider used on the slave FB pin. This forces the slave voltage to be the same as the master voltage. For coincident tracking, use RTRKT = RTOP and RTRKB = RBOT, as shown in Figure 32. MASTER VOLTAGE VOLTAGE (V) In most applications, RSNUB is typically 2 Ω to 4 Ω, and CSNUB is typically 1.2 nF to 3 nF. The size of the RC snubber components must be chosen correctly to handle the power dissipation. The power dissipated in RSNUB is SLAVE VOLTAGE PSNUB = V IN 2 × C SNUB × f SW 10594-037 1 f SW 2 The ADP1853 includes a tracking feature that tracks a master voltage. In all tracking configurations, the output can be set as low as 0.6 V for a given operating condition. The soft start time setting of the master voltage should be longer than the soft start of the slave voltage. This forces the rise time of the master voltage to be imposed on the slave voltage. If the soft start setting of the slave voltage is longer, the slave comes up more slowly, and the tracking relationship is not seen at the output. TIME Figure 31. Coincident Tracking In most applications, a component size of 0805 for RSNUB is sufficient. The RC snubber does not reduce the voltage overshoot. A resistor, shown as RRISE in Figure 30, at the BST pin helps to reduce overshoot and is generally between 2 Ω and 4 Ω. Adding a resistor in series, typically between 2 Ω and 4 Ω, with the gate driver also helps to reduce overshoot. If a gate resistor is added, then RRISE is not needed. 3.3V VOUT_MASTER 1.8V VOUT_SLAVE ADP1853 RTRKT 20kΩ 1.1V TRK RTOP 20kΩ FB RBOT 10kΩ RTRKB 10kΩ ADP1853 RRISE VIN CSS 20nF BST SS M1 L SW M2 DL Figure 32. Example of a Coincident Tracking Circuit VOUT The ratio of the slave output voltage to the master voltage is a function of the two dividers. RSNUB COUT CSNUB PGND 10594-036 DH 10594-038 f P1 = VOLTAGE TRACKING VOUT _ SLAVE Figure 30. Application Circuit with a Snubber VOUT _ MASTER Rev. 0 | Page 23 of 28 R 1 + TOP R BOT = RTRKT 1 + RTRKB ADP1853 Data Sheet As the master voltage rises, the slave voltage rises identically. Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the TRK input continues to increase, thus removing itself from influencing the output voltage. VOLTAGE (V) MASTER VOLTAGE 10594-039 To ensure that the output voltage accuracy is not compromised by the TRK pin being too close in voltage to the reference voltage (VFB, typically 0.6 V), make sure that the final value of the TRK voltage of the slave channel is at least 30 mV above VFB. SLAVE VOLTAGE TIME Figure 33. Ratiometric Tracking 3.3V VOUT_MASTER Ratiometric tracking limits the output voltage to a fraction of the master voltage, as illustrated in Figure 33 and Figure 34. The final TRK voltage of the slave channel should be set to at least 30 mV below the FB voltage of the master channel. When the TRK voltage of the slave channel drops to a level that is below the minimum on time condition, the slave channel operates in pulse skip mode while keeping the output regulated and tracked to the master channel. In addition, when TRK or FB drops below the PGOOD undervoltage threshold, the PGOOD signal is tripped and becomes active low. 1.8V VOUT_SLAVE ADP1853 RTRKT 49.9kΩ 0.55V TRK RTRKB 10kΩ CSS 20nF SS FB RTOP 22.6kΩ 0.55V RBOT 10kΩ 10594-040 Ratiometric Tracking Figure 34. Example of a Ratiometric Tracking Circuit PCB LAYOUT GUIDLINES The recommended board layout practices for the synchronous buck controller are described in the AN-1119 Application Note. Rev. 0 | Page 24 of 28 Data Sheet ADP1853 TYPICAL OPERATING CIRCUITS VIN = 12V TO 18V ILIM FREQ 14 ADP1853 3 13 4 12 EP 5 6 7 11 8 9 VCCO 16pF 15 2 BST 0.1µF DH M1 L SW CS COUT VOUT 5V 15A M2 DL 10 PGND COMP AGND 2.74kΩ CIN 1 VIN SS FB 32.4kΩ 390pF RAMP TRK EN SYNC 20kΩ 1.3kΩ 20 19 18 17 16 CLKOUT 0.1µF PGOOD 348kΩ TO VCCO 22kΩ 0.003Ω 2W 1µF 2Ω TO VIN fSW = 600kHz CIN: OS-CON 150µF/20V, 20SEP150M, SANYO + CAP CER 10µF 25V X7R 1210, MURATA GRM32DR71E106KA12 L: 1.8µH WURTH ELECTRONIK WE-HCI 1050 744 325 180 M1: VISHAY SILICONIX SiR462DP M2: VISHAY SILICONIX SiR866DP COUT: POSCAP 100µF/6.3V SANYO 6TPE100MI + 2× CAP CER 22µF 10V X5R 1210 MURATA GRM32ER61A226KE20L Figure 35. 15 A Circuit Operating in Current Mode Rev. 0 | Page 25 of 28 10594-041 1µF ADP1853 Data Sheet VIN = 9V TO 15V 510pF AGND ILIM FREQ RAMP 2 14 ADP1853 3 13 4 12 EP 5 SYNC 6 7 11 8 9 BST 0.1µF DH M1 L SW CS COUT VOUT 3.3V 25A M2 DL 10 PGND 21.5kΩ 1600pF COMP 15 VCCO FB 7.15kΩ CIN 1 VIN EN SS 75pF 2.74kΩ 20 19 18 17 16 CLKOUT 0.1µF TRK 2kΩ PGOOD 196kΩ TO VCCO 32.4kΩ 100kΩ 1µF 2Ω TO VIN fSW = 300kHz CIN: OS-CON 150µF/20V, 20SEP150M, SANYO + CAP CER 10µF 25V X7R 1210, MURATA GRM32DR71E106KA12 L: 1µH COILCRAFT SER1412-102ME M1: INFINEON BSC052N03LS M2: INFINEON BSC0902NS COUT: POSCAP 330µF/6.3V SANYO 6TPE330MFL + CAP CER 22µF 10V X5R 1210 MURATA GRM32ER61A226KE20L Figure 36. 25 A Circuit Operating in Voltage Mode Rev. 0 | Page 26 of 28 10594-042 1µF Data Sheet ADP1853 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 061609-B TOP VIEW Figure 37. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP1853ACPZ-R7 1 Temperature Range −40°C to +125°C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option CP-20-10 ADP1853 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10594-0-5/12(0) Rev. 0 | Page 28 of 28