www.fairchildsemi.com
RC7144
133MHz Spread Spectrum Motherboard Integrated
Clock/Buffer
Description
• Employs Fairchild’s proprietary Spread Spectrum
Technology
• Reduces measured EMI by as much as 10dB
• Supports up to 150MHz
¥ I2C programmable
• Two copies of CPU clock with one free running
• One copy 24MHz clock
• One copy 48MHz clock
• One copy IOAPIC
• Two copy REF 14.318MHz clock (3.3V)
• Six copies PCI clock
• Thirteen copies of SDRAM clock with one free running
• PCI/CPU stop capability
The RC7144 is a clock synthesizer for motherboard applications. It meets the requirements for the 133MHz 13x/zx
chipset. The clock frequencies can be set with the 4 select
pins or can be set via the I2C interface.
Preliminary Information
Features
Block Diagram
X1
X2
XTAL
OSC
REF1/FS2
REF0/PCI_STOP#
IOAPIC
PLL1
Spread
Spectrum
PLL2 USB
SDRAMIN
SCL
SDA
I2C
Registers
C
O
N
T
R
O
L
L
O
G
I
C
CPU1
CPU_F
PCI_F/MODE
PCI1/FS3
PCI2:5
SDRAM_F
SDRAM0:11
CLK_STOP#
24MHz/FS1
48MHz/FS0
I2C is a trademark of Philips Corporation
Rev. 0.8.2
Preliminary Specification describes products that are not in full production at the time of printing. Specifications are based on design goals and
limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7144
PRODUCT SPECIFICATION
Pin Assignments
Preliminary Information
VDDQ3
REF0/PCI_STOP#
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PC12
PC13
PC14
PC15
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDA
2
I C
SCL
{
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RC7144
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU_F
CPU1
VDDQ2
CLK_STOP#
SDRAM_F
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
PRODUCT SPECIFICATION
RC7144
Pin Description
Pin Name
Pin #
Pin Type
Pin Function
1, 6, 14, 19,
27, 30, 36
PWR
Power connection: Power supply for core logic, PLL circuitry SDRAM
outputs, PCI outputs, reference, 48 & 24 MHz outputs. Connect to 3.3
Volts.
2
OUT/IN
3, 9, 16, 22,
33, 39, 45
PWR
Ground connection: Connect all ground pins to the common system
ground plane.
X1
4
IN
Crystal Connection: An input connection for an external 14.318 MHz
crystal. 18 pF internal cap.
X2
5
OUT
Crystal Connection or External Reference Frequency: This pin has
dual functions. It can be used as an external 14.318 MHz crystal
connection or as an external reference frequency input.
PCI_F/MODE
7
OUT/IN
Fixed PCI clock output: Upon power up MODE input will be latched,
which will enable or disable REF0.
PCI1/FS3
8
OUT/IN
PCI clock output: Upon power up FS3 input will be latched, which will
set clock frequencies as frequency selection table. This pin has internal
pull down.
10, 11, 12, 13
OUT
15
IN
17, 18, 20, 21,
28, 29, 31, 32,
34, 35, 37, 38,
40
OUT
SDA
23
IN/OUT
Data pin for I2C circuitry.
SCL
24
IN
Clock pin for I2C circuitry.
24MHz/FS1
25
OUT/IN
24 MHz clock output: 24 MHz is provided in normal operation. In
standard systems, this output can be used as the clock input for Super
I/O chip. Upon power up FS1 input will be latched, which will set clock
frequencies as frequency selection table.
48MHz/FS0
26
OUT/IN
48 MHz clock output: 48 MHz is provided in normal operation. In
standard systems, this output can be used as the reference for
universal Serial Bus. Upon power up FS0 input will be latched, which
will set clock frequencies as frequency selection table.
CLK_STOP#
41
IN
CLK_STOP# Input: When 0, this pin stops the CPU outputs after
completing a full clock cycle. This pin does not effect CPU_F.
VDDQ2
42, 48
PWR
Power supply for IOAPIC & all CPU outputs. Connect to 2.5 or 3.3
Volts.
CPU1,
CPU_F
43, 44
OUT
CPU output clocks: VDDQ2 controls output Voltage. Stopped when
CLK_STOP# is 0. CPU_F is not affected by CLK_STOP#.
REF1/FS2
46
OUT/IN
Reference Clock output: 14.31818 MHz reference output. Upon
power up FS2 input will be latched, which will set clock frequencies as
frequency selection table.
IOAPIC
47
OUT
IOAPIC clock: Provides 14.31818 MHz fixed clock. VDDQ2 contols the
output Voltage.
VDDQ3
REF0/
PCI_STOP#
GND
SDRAM_IN
SDRAM0:11;
SDRAM_F
PCI clock output 2 through 5: These five PCI clock outputs are
controlled by the PCI_STOP# control pin.
Buffered input pin: The signal provided to this input pin is buffered to
13 outputs.
SDRAM Clock Ouputs: SDRAM0:11 clock are determined by
FS0: FS3. SDRAM_F is a free running clock which is not controlled
by the I2C.
3
Preliminary Information
PCI2:5
I/O Dual function REF0 & PCI_STOP#: Function determined by
MODE pin. When high, this pin is an output with 14.31818 MHz of
reference clock. When MODE is low, PCI_STOP# stops all the PCI
clocks.
RC7144
PRODUCT SPECIFICATION
Frequency Selection Table
Preliminary Information
Input Address
FS3
FS2
FS1
FS0
CPU (MHz)
PCI (MHz)
1
1
1
1
133.3
33.3
1
1
1
0
124
31
1
1
0
1
150
37.5
1
1
0
0
140
35
1
0
1
1
105
35
1
0
1
0
110
36.7
1
0
0
1
115
38.3
1
0
0
0
120
40
0
1
1
1
100
33.3
0
1
1
0
133.3
44.43
0
1
0
1
112
37.3
0
1
0
0
103
34.3
0
0
1
1
66.8
33.4
0
0
1
0
83.3
41.7
0
0
0
1
75
37.5
0
0
0
0
124
41.3
Power Management Control
4
Mode
PCI_STOP#
PCI
REF0
PCI_F
0
0
Stopped
Disable
Running
0
1
Running
Disable
Running
1
X
Running
Running
Running
CLK_STOP#
CPU
CPU_F
REF1, 24/48MHZ, SDRAM 0:11
0
Stopped
Running
Running
1
Running
Running
Running
PRODUCT SPECIFICATION
RC7144
Functional Description
I/O Pin Operation
Dual Purpose I/O pins such as pin 8 FS3/PCI1, act as a logic
input upon power up. This allows the determination of
assigned device function. For example, FS3 along with the
other three select pins will determine the clock frequencies
as shown in the table. A short time after power up, the logic
state is latched and the pin becomes a clock output pin. For
example, pin 8 becomes a PCI clock output. This feature
reduces device pin count by combining clock outputs with
input select pins.
Upon power up, the first 2mS of operation is used for input
logic selection. The clock output pins are tri-stated, allowing
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of outputs is 20 ohms (nominal) which is minimally
affected by the 10kohm strap to ground or VDD. As with the
series termination resistor, the output strapping resistor
should be placed as close to the I/O pin as possible in order
to keep the interconnecting trace short. The trace from the
resistor to ground or VDD should be kept less than two
inches in length to prevent system noise coupling during
input logic sampling.
VDD
RC7144
10K Load
Option 1
10K Load
Option 0
Series
Terminating
Resistor
Clock Load
Figure 1. Input Logic Selection through Resistor Load Option
5
Preliminary Information
An external 10k ohm “strapping” resistor is connected
between the I/O pin and VDD or VSS (ground). A connection to ground sets a “0” bit and a connection to VDD sets a
“1” bit. See Figure 1.
the output strapping resistor on the I/O pin to pull the pin and
its associated capacitive clock load to either a logic high or
low state. At the end of the 2mS period, the established logic
“0” or “1” condition of the I/O pin is then latched. Next the
output buffer is enabled which converts the I/O pin into an
operating clock output. The 2mS timer is started when VDD
(3.3V) reaches 2.0V. The input bits can only be reset by turning the VDD off and then back on again.
RC7144
PRODUCT SPECIFICATION
I2C Interface Information
device pins SDA and SCL. In motherboard applications,
SDA and SCL are typically driven by two logic outputs of
the chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power management functions. Table 1 summarizes the control functions of
the serial data interface.
The RC7144 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions. Upon power-up, the RC7144 initializes with default register settings therefore, the use of this
serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of
Preliminary Information
Table 1. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output
Disable
Any individual clock output(s) can be
disabled. Disabled outputs are actively
held low.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
CPU Clock
Provides CPU/PCI frequency selections
Frequency Selection other than the 100MHz provided upon
power-on. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
Spread Spectrum
Enabling
Turns spread spectrum on or off.
EMI reduction.
Output Tristate
Puts all clock outputs into a high
impedance state.
Production PCB testing.
Test Mode
All clock ouputs toggle in relation to X1
input, internal PLL is bypassed. Refer to
Table 6.
Production PCB testing.
Reserved
Reserved function for future device
revision or production device testing.
No user application. Register bit must be
written as 0.
RC7144 I2C Interface Write Sequence Example
Signal from Motherboard Clock Chip
START MSB
LSB
Slave Address (First Byte)
SDA
1
1
0
1
0
0
1
0
SCL
1
2
3
4
5
6
7
8
Command Code (2nd Byte)
MSB
A
1
Byte Count (3rd Byte)
LSB
2
3
8
MSB
A
1
Last Data Byte
LSB
2
8
MSB
A
1
STOP
LSB
2
8
A
SDA
(ACK Signal
From Buffer Chip)
Note:
6
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDA at every 8th bit. The 8 bit data
from SDA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The
COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
PRODUCT SPECIFICATION
RC7144
I2C Register Operation
The RC7144 is programmed by writing 10 bytes
of eight bits each. See Table 2 for byte order.
Table 2. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit
Sequence
Byte Description
Slave
Address
11010010
Commands the RC7144 to accept the bits in Data Bytes 0-6 or internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the RC7144
is 11010010. Register setting will not be made if the Slave Address is
not correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the RC7144, therefore, bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the RC7144, therefore, bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
4
Data Byte 0
5
Data Byte 1
Refer to
Table 3
6
Data Byte 2
The data bits in these bytes set internal RC7144 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map.
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
7
Preliminary Information
1
RC7144
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit of the 8 data bytes controls a particular device function except for the “reserved bits”. These must be preserved
by writing a logic 0. Bit 7, the MSB, is written first. See
Table 3 for bit descriptions of Data Bytes 1-4.
Table 5 shows additional frequency selections that are
programmable via the serial data interface.
Table 4 shows the mode select for byte 0, Bit 1and 0.
Table 3. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Bit Control
Pin Name
Control Function
0
1
Default
Center
Down
0
Preliminary Information
Data Byte 0
7
-
-
Spread Mode
6
-
-
FS 2
-
-
0
5
-
-
FS 1
-
-
0
4
-
-
FS 0
-
-
0
3
-
-
Hardware/Software
Frequency Select
2
-
-
FS3
1–0
-
-
Bit 1
0
0
1
1
7
-
-
Reserved
-
-
0
6
-
-
Reserved
-
-
0
5
-
-
Reserved
-
-
0
4
-
-
Test Mode
Test Mode
Normal
1
3
40
SDRAM_F
Low
Active
1
2
-
-
-
-
0
1
43
CPU1
Clock Output Disabled
Low
Active
1
0
44
CPU_F
Clock Output Disabled
Low
Active
1
7
-
-
-
-
0
6
7
PCI_F
Low
Active
1
Hardware
-
Bit 0
0
1
0
0
Software
-
0
0
00
Function (see Table 4)
Normal Operation
Reserved
Spread Spectrum on
All Outputs Tristated
Data Byte 1
Clock Output Disabled
Reserved
Data Byte 2
Reserved
Clock Output Disabled
5
-
-
-
0
4
13
PCI5
Reserved
Clock Output Disabled
Low
Active
1
3
12
PCI4
Clock Output Disabled
Low
Active
1
2
11
PCI3
Clock Output Disabled
Low
Active
1
1
10
PCI2
Clock Output Disabled
Low
Active
1
0
8
PCI1
Clock Output Disabled
Low
Active
1
7
-
-
Reserved
-
-
0
6
-
-
Reserved
-
-
0
5
26
48 MHz
Clock Output Disabled
Low
Active
1
4
25
24MHz
Clock Output Disabled
Low
Active
1
3
-
-
-
-
0
Data Byte 3
8
Reserved
PRODUCT SPECIFICATION
RC7144
Table 3. Data Bytes 0–7 Serial Configuration Map (Continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
0
1
Default
2
21, 20, 18, 17
SDRAM8:11
Clock Output Disabled
Control Function
Low
Active
1
1
32, 31, 29, 28
SDRAM4:7
Clock Output Disabled
Low
Active
1
0
38, 37, 35, 34
SDRAM0:3
Clock Output Disabled
Low
Active
1
Data Byte 4
-
-
Reserved
-
-
0
6
-
-
Reserved
-
-
0
5
-
-
Reserved
-
-
0
4
-
-
Reserved
-
-
0
3
-
-
Reserved
-
-
0
2
-
-
Reserved
-
-
0
1
-
-
Reserved
-
-
0
0
-
-
Reserved
-
-
0
7
-
-
Reserved
-
-
0
6
-
-
Reserved
-
-
0
5
-
-
Reserved
-
-
0
4
47
IOAPIC
Low
Active
1
3
-
-
Reserved
-
-
0
2
-
-
Reserved
-
-
0
1
46
REF1
Clock Output Disabled
Low
Active
1
0
2
REF0
Clock Output Disabled
Low
Active
1
7
-
-
Reserved
-
-
0
6
-
-
Reserved
-
-
0
5
-
-
Reserved
-
-
0
4
-
-
Reserved
-
-
0
3
-
-
Reserved
-
-
0
2
-
-
Reserved
-
-
0
1
-
-
Reserved
-
-
0
0
-
-
Reserved
-
-
0
7
-
-
Reserved
-
-
0
6
-
-
Reserved
-
-
0
5
-
-
Reserved
-
-
0
4
-
-
Reserved
-
-
0
3
-
-
Reserved
-
-
0
2
-
-
Reserved
-
-
0
1
-
-
Reserved
-
-
0
0
-
-
Reserved
-
-
0
Preliminary Information
7
Data Byte 5
Clock Output Disabled
Data Byte 6
Data Byte 7
9
RC7144
PRODUCT SPECIFICATION
Table 4. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Output Conditons
Data Byte 0
Function
Normal Operation
Bit 1
Bit 0
CPU
PC1
IOAPIC
REF0:1
48 MHz
24 MHz
0
0
NOTE 1
NOTE 1
14.318 M
48 M
24 M
Spread Spectrum
1
0
±0.5%
±0.5%
14.318 M
48 M
24 M
Tristate
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 5. Frequency Selection Table Through I2C Programming
Input Conditons
Preliminary Information
Data Byte 0, Bit 3 = 1
Bit 2
FS3
Bit 6
FS2
Bit 5
FS1
Bit 4
FS0
CPU (MHz)
PCI (MHz)
1
1
1
1
133.3
33.3
1
1
1
0
124
31
1
1
0
1
150
37.5
1
1
0
0
140
35
1
0
1
1
105
35
1
0
1
0
110
36.7
1
0
0
1
115
38.3
1
0
0
0
120
40
0
1
1
1
100
33.3
0
1
1
0
133.3
44.43
0
1
0
1
112
37.3
0
1
0
0
103
34.3
0
0
1
1
66.8
33.4
0
0
1
0
83.3
41.7
0
0
0
1
75
37.5
0
0
0
0
124
41.3
Table 6. Test Mode
Function
Input Condition Data Byte4
CPU
PCI
REF, IOAPIC
48MHz
24MHz
Normal
1
Note 1
Note 1
14.318
48
24
Test Mode
0
X1
CPU/2 or 3
X1
X1/2
X1/4
Note:
1. See table 5 for frequency selection.
10
PRODUCT SPECIFICATION
RC7144
Absolute Maximum Ratings
Symbol
Parameter
Ratings
Units
VDD, VIN
Voltage on any pin with respect to ground
-0.5 to 7.0
V
TSTG
Storage Temperature
-65 to 150
oC
TB
Ambient Temperature
-55 to 125
oC
TA
Operating Temperature
0 to 70
o
ESDPROT
Input ESD Protection
2 (min)
kV
C
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may affect reliability.
TA = 0°C to 70°C; Supply Voltage 3.3V±5% (unless otherwise stated)
Symbol
Parameter
Test Condition
VIL
Input Low Voltage
VIH
Input High Voltage
IIL
Input Low Current
VIN=0; inputs with no pull-up resistors
Min.
Typ.
Max.
Units
VSS-0.3
0.8
V
2.0
VDD+0.3
V
-5
5
µA
-25
µA
-5
µA
5
pF
VIN=0; inputs with pull-up resistors
IIH
Input High Current
Capacitance1
VIN=VDD
-5
CIN
Input
All except X1 and X2.
COUT
Output Capacitance1
6
pF
LIN
Input Pin Inductance1
7
nH
X1 and X2 Pins. X2 unconnected.
Threshold1
VTH
Crystal Input
IDD
Supply Current
IDDL
18
pF
VDD=3.3V
1.5
V
Freq=100M: CL max. on all outputs
300
mA
VDD=2.5V 0.5%; Freq-100M
24
TSTAB
Clock Stabilization1
From VDD=3.3V to 1% Target
TCPU-PCI
Skew1
VDDL=2.5V; VDD=3.3V; CPU
VTH=1.25V, PCI VTH=1.5V
1.5
mA
3
mS
4
nS
Note:
1. Guaranteed by design, not subject to 100% production testing.
11
Preliminary Information
Electrical Characteristics—Common Parameters
RC7144
PRODUCT SPECIFICATION
Electrical Characteristics—CPU Outputs
TA=0°C to 70°C; Supply Voltage VDD=3.3V±5%; VDDL=2.5V±5% (unless otherwise stated)
Symbol
Test Condition
Min.
Typ.
Max.
Units
0.5
V
VOL
Output Low Voltage
IOL=1 mA
VOH
Output High Voltage
IOH=-1 mA
2.0
IOL
Output Low Current
VOL=1.2 V
27
93
mA
IOH
Output High Currents
VOH=1.2 V
-101
-25
mA
TR
1
Rise Time
0.4 to 2.0 V: CL=20 pF
0.4
1.6
nS
TF
Fall Time1
2.0 to 0.4 V; CL=20 pF
0.4
1.6
nS
Duty
Cycle1
VTH=1.25 V; CL=20 pF
45
55
%
TJIT
Jitter
(Cycle-cycle)1
VTH=1.25 V; CL=20 pF
200
pS
TSK
Skew1
VTH=1.25 V; CL=20 pF
175
pS
DT
Preliminary Information
Parameter
ZO
AC Output
Impedance1
V
Ω
20
Note:
1. Guaranteed by design, not subject to 100% production testing.
Electrical Characteristics—IOAPIC Outputs
TA=0°C to 70°C; Supply Voltage VDD=3.3V±5%; VDDL=2.5V±5% (unless otherwise stated)
Symbol
Parameter
VOL
Output Low Voltage
Test Condition
Min.
Typ.
IOL=1 mA
Max.
Units
0.5
V
VOH
Output High Voltage
IOH=-1 mA
2.0
IOL
Output Low Current
VOL=1.25 V
27
93
mA
IOH
Output High Currents
VOH=1.2 V
-101
-25
mA
0.4 to 2.0 V: CL=20 pF
0.4
1.6
nS
2.0 to 0.4 V; CL=20 pF
0.4
1.6
nS
VTH=1.25 V; CL=20 pF
45
TR
TF
Rise
Fall
Time1
Time1
Cycle1
DT
Duty
TJIT
Jitter (Cycle-cycle)1
ZO
AC Output Impedance1
VTH=1.25 V; CL=20 pF
Note:
1. Guaranteed by design, not subject to 100% production testing.
12
V
15
55
%
500
pS
Ω
PRODUCT SPECIFICATION
RC7144
Electrical Characteristics—PCI Outputs
TA=0°C to 70°C; Supply Voltage VDD=3.3V±5%; VDDL=2.5V±5% (unless otherwise stated)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
0.5
V
VOL
Output Low Voltage
IOL=1 mA
VOH
Output High Voltage
IOH=-1 mA
2.4
IOL
Output Low Current
VOL=1.5 V
26
139
mA
IOH
Output High Currents
VOH=1.5 V
-189
-31
mA
TR
1
Rise Time
0.4 to 2.4 V: CL=30 pF
0.5
2.0
nS
TF
Fall Time1
2.4 to 0.4 V; CL=30 pF
0.5
2.0
nS
Duty
Cycle1
VTH=1.5 V; CL=30 pF
45
55
%
TJIT
Jitter
(Cycle-cycle)1
VTH=1.5 V; CL=30 pF
250
pS
TSK
Skew1
VTH=1.5 V; CL=30 pF
500
pS
DT
AC Output
Ω
30
Note:
1. Guaranteed by design, not subject to 100% production testing.
Electrical Characteristics—REF Outputs
TA=0°C to 70°C; Supply Voltage VDD=3.3V±5%; VDDL=2.5V±5% (unless otherwise stated)
Symbol
Parameter
VOL
Output Low Voltage
Test Condition
Min.
Typ.
IOL=1 mA
Max.
Units
0.5
V
VOH
Output High Voltage
IOH=-1 mA
2.4
IOL
Output Low Current
VOL=1.5 V
25
76
mA
IOH
Output High Currents
VOH=1.5 V
-94
-27
mA
0.4 to 2.4 V: CL=20 pF
1
4
nS
2.4 to 0.4 V; CL=20 pF
1
4
nS
VTH=1.5 V; CL=20 pF
45
TR
TF
Rise
Fall
Time1
Time1
Cycle1
DT
Duty
TJIT
Jitter (Cycle-cycle)1
ZO
AC Output Impedance1
V
VTH=1.5 V; CL=20 pF
30
55
%
500
pS
Ω
Note:
1. Guaranteed by design, not subject to 100% production testing.
13
Preliminary Information
ZO
Impedance1
V
RC7144
PRODUCT SPECIFICATION
Electrical Characteristics—48/24 MHz Outputs
TA=0°C to 70°C; Supply Voltage VDD=3.3V±5%; VDDL=2.5V±5% (unless otherwise stated)
Symbol
Test Condition
Min.
Typ.
Max.
Units
0.5
V
VOL
Output Low Voltage
IOL=1 mA
VOH
Output High Voltage
IOH=-1 mA
2.4
IOL
Output Low Current
VOL=1.5 V
25
76
mA
IOH
Output High Currents
VOH=1.5 V
-94
-27
mA
Frequency Accuracy
TR
Rise Time1
DT
ZO
V
1
FACCU
TF
Preliminary Information
Parameter
Fall
Time1
Duty
Cycle1
AC Output
167
ppm
0.4 to 2.4 V: CL=20 pF
1
4.0
nS
2.4 to 0.4 V; CL=20 pF
1
4.0
nS
VTH=1.5 V; CL=20 pF
45
55
%
Impedance1
Ω
40
Note:
1. Guaranteed by design, not subject to 100% production testing.
Electrical Characteristics—SDRAM outputs
TA=0°C to 70°C; Supply Voltage VDD=3.3V±5%; VDDL=2.5V±5% (unless otherwise stated)
Symbol
Parameter
Test Condition
Min.
VOL
Output Low Voltage
IOL=1 mA
VOH
Output High Voltage
IOH=-1 mA
2.4
IOL
Output Low Current
VOL=0.4 V
53
IOH
Output High Currents
VOH=2.0 V
TR
TF
DT
Rise
Fall
Time1
Time1
Duty
Cycle1
TJIT
Jitter (Cycle to
TSK
Skew1
ZO
AC Output
Cycle)1
Max.
Units
0.5
V
V
mA
-54
mA
0.4 to 2.4 V: CL=30 pF
0.5
1.6
nS
2.4 to 0.4 V; CL=30 pF
0.5
1.6
nS
VTH=1.5 V; CL=30 pF
45
55
%
VTH=1.5 V; CL=30 pF
250
pS
VTH=1.5 V; CL=30 pF
250
pS
Impedance1
Note:
1. Guaranteed by design, not subject to 100% production testing.
14
Typ.
40
Ω
PRODUCT SPECIFICATION
RC7144
Mechanical Dimensions
48 pin SSOP
Symbol
Millimeters
Min.
Max.
.095
.008
.110
.016
.0135
.008
.005
.010
.620
.630
.395
.420
.291
.299
.025 BSC
.020
.040
48
0°
8°
--.004
Min.
2.41
0.20
Notes:
Notes
Max.
1. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
2.79
0.41
2. "D" and "E1" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
0.34
0.20
0.25
0.13
16.00
15.75
10.67
10.03
7.59
7.39
0.64 BSC
0.51
1.02
48
0°
8°
--0.13
5
5
2, 4
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
2
5. "b" & "c" dimensions include solder finish thickness.
3
6
6. Symbol "N" is the maximum number of terminals.
Preliminary Information
A
A1
b
c
D
E
E1
e
L
N
a
ccc
Inches
E
E1
1
D
A
e
b
A1
SEATING PLANE
-C-
c
a
L
LEAD COPLANARITY
ccc C
15
RC7144
PRODUCT SPECIFICATION
Ordering Information
Package
RC7144
48 pin SSOP
Preliminary Information
Product Number
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8/6/99 0.0m 009
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1998 Fairchild Semiconductor Corporation