PRELIMINARY W150 440BX AGPset Spread Spectrum Frequency Synthesizer Features Table 1. Mode Input Table • Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Single chip system frequency synthesizer for Intel® 440BX AGPset • Three copies of CPU output • Seven copies of PCI output • One 48-MHz output for USB / One 24-MHz for SIO • Two buffered reference outputs • Two IOAPIC outputs • 17 SDRAM outputs provide support for 4 DIMMs • Supports frequencies up to 150 MHz • I2C™ interface for programming • Power management control inputs Key Specifications Mode Pin 3 0 PCI_STOP# 1 REF0 Table 2. Pin Selectable Frequency Input Address FS3 FS2 FS1 FS0 CPU_F, 1:2 (MHz) PCI_F, 0:5 (MHz) 1 1 1 1 133.3 33.3 (CPU/4) 1 1 1 0 124 31 (CPU/4) 1 1 0 1 150 37.5 (CPU/4) 1 1 0 0 140 35 (CPU/4) 1 0 1 1 105 35 (CPU/3) 1 0 1 0 110 36.7 (CPU/3) 38.3 (CPU/3) 1 0 0 1 115 CPU Cycle-to-Cycle Jitter: ......................................... 250 ps 1 0 0 0 120 40 (CPU/3) CPU to CPU Output Skew: ........................................ 175 ps 0 1 1 1 100 33.3 (CPU/3) PCI to PCI Output Skew: ............................................ 500 ps 0 1 1 0 133.3 44.43 (CPU/3) SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ. 0 1 0 1 112 37.3 (CPU/3) VDDQ3: .................................................................... 3.3V±5% 0 1 0 0 103 34.3 (CPU/3) VDDQ2: .................................................................... 2.5V±5% 0 0 1 1 66.8 33.4 (CPU/2) SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ. 0 0 1 0 83.3 41.7 (CPU/2) REF1/FS2 PLL Ref Freq Stop Clock Control I/O Pin Control CLK_STOP# VDDQ2 IOAPIC_F IOAPIC0 Stop Clock Control CPU1 CPU2 ÷2,3,4 VDDQ3 PCI_F/MODE PCI0/FS3 Stop Clock Control PCI1 PCI2 PCI3 SDATA SCLK I2C Logic PCI4 PCI5 VDDQ3 75 37.5 (CPU/2) 0 124 41.3 (CPU/3) VDDQ3 REF1/FS2 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI0/FS3 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 SDRAMIN SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 IOAPIC0 IOAPIC_F GND CPU_F CPU1 VDDQ2 CPU2 GND CLK_STOP# SDRAM_F VDDQ3 SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 VDDQ3 24MHz/FS0 48MHz/FS1 48MHz/FS1 PLL2 SDRAMIN 1 0 W150 VDDQ2 CPU_F PLL 1 0 0 Pin Configuration VDDQ3 REF0/(PCI_STOP#) XTAL OSC 0 0 [1] Logic Block Diagram X1 X2 0 Stop Clock Control 24MHz/FS0 VDDQ3 SDRAM0:15 16 SDRAM_F Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation. Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 February 10, 2000, rev. *A PRELIMINARY W150 Pin Definitions Pin Name CPU1:2 Pin No. 51, 49 CPU_F 52 PCI1:5 11, 12, 13, 14, 16 9 PCI0/FS3 PCI_F/MODE 8 CLK_STOP# 47 IOAPIC_F 54 IOAPIC0 55 48MHz/FS1 29 24MHz/FS0 30 REF1/FS2 2 REF0 (PCI_STOP#) 3 SDRAMIN 17 SDRAM0:15 SDRAM_F 44, 43, 41, 40, 39, 38, 36, 35, 22, 21, 19, 18, 33, 32, 25, 24 46 Pin Type Pin Description CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input O interface, see Tables 2 and 6. These outputs are affected by the CLK_STOP# input. Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial O input interface, see Tables 2 and 6. This output is not affected by the CLK_STOP# input. PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input O interface, see Tables 2 and 6. These outputs are affected by the PCI_STOP# input. I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When an input, selects function of pin 3 as described in Table 1. CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after comI pleting a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs start beginning with a full clock cycle (2–3 CPU clock latency). Free-running IOAPIC Output: This output is a buffered version of the reference input O which is not affected by the CPU_STOP# logic input. It’s swing is set by voltage applied to VDDQ2. I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW. I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be latched, setting output frequencies as described in Table 2. I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched, setting output frequencies as described in Table 2. I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input will be latched, setting output frequencies as described in Table 2. I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz). Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs I (SDRAM0:15, SDRAM_F). Buffered Outputs: These sixteen dedicated outputs provide copies of the signal proO vided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. O SCLK SDATA X1 28 27 5 I I/O I X2 6 I 1, 7, 15, 20, 31, 37, 45 P VDDQ3 Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input. Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI output buffers, reference output buffers, and 48-MHz/24-MHz output buffers. Connect to 3.3V. 2 PRELIMINARY W150 Pin Definitions (continued) Pin Name VDDQ2 GND Pin No. 50, 56 4, 10, 23, 26, 34, 42, 48, 53 Pin Type Pin Description Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V P or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. G tor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. Overview The W150 was designed as a single-chip alternative to the standard two-chip Intel 440BX AGPset clock solution. It provides sufficient outputs to support most single-processor, four SDRAM DIMM designs. Functional Description It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output (<40Ω, nominal) is minimally affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to minimize system noise coupling during input logic sampling. I/O Pin Operation Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-kΩ “strapping” resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. When the clock outputs are enabled following the 2-ms input period, the corresponding specified output frequency is delivered on the pins, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Upon W150 power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (2, 8, 9, 29, 30) are three-stated, allowing the output strapping resis- VDD O utput S trapping R esistor S eries Term ination Resistor 10 kΩ (Load O ption 1) W150 Power-on Reset Timer Clock Load Output Buffer Hold Output Low Output Three-state Q 10 kΩ (Load O ption 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Jumper Options Output Strapping Resistor V DD Series Termination Resistor 10 kΩ W150 Power-on Reset Timer R Output Buffer Q Resistor Value R Hold Output Low Output Three-state D Data Latch Figure 2. Input Logic Selection Through Jumper Option 3 Clock Load PRELIMINARY W150 Spread Spectrum Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 6. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the I2C data stream. Refer to Table 7 for more details. dB = 6.5 + 9*log10(P) + 9*log10(F) 5 dB/div Typical Clock Amplitude (dB) SSFTG –1.0 –0.5% –SS% 0 +1.0 +0.5% +SS% Frequency Span (MHz) Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN Figure 4. Typical Modulation Profile 4 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX PRELIMINARY W150 chipset. If needed, clock device register changes are normally made upon system initialization. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Serial Data Interface The W150 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W150 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the Operation Data is written to the W150 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4. Table 3. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. CPU Clock Frequency Selection Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Spread Spectrum Enabling Enables or disables spread spectrum clocking. For EMI reduction. Output Three-state Puts clock output into a high-impedance state. Production PCB testing. Test Mode All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 5. Production PCB testing. (Reserved) Reserved function for future device revision or production device testing. No user application. Register bit must be written as 0. Table 4. Byte Writing Sequence Byte Sequence Byte Name Bit Sequence Byte Description 1 Slave Address 11010010 Commands the W150 to accept the bits in Data Bytes 0–7 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W150 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W150, therefore bit values are ignored (“don’t care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W150, therefore bit values are ignored (“don’t care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Refer to Table 5 The data bits in Data Bytes 0–5 set internal W150 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map. Don’t Care Unused by the W150, therefore bit values are ignored (don’t care). 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 11 Data Byte 7 5 PRELIMINARY W150 Table 6 details additional frequency selections that are available through the serial data interface. Writing Data Bytes Each bit in Data Bytes 0–7 control a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 5 gives the bit formats for registers located in Data Bytes 0–7. Table 7 details the select functions for Byte 0, bits 1 and 0. Table 5. Data Bytes 0–5 Serial Configuration Map Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default -- -- 0 Data Byte 0 7 -- -- (Reserved) 6 -- -- SEL_2 See Table 6 0 5 -- -- SEL_1 See Table 6 0 4 -- -- SEL_0 See Table 6 0 3 -- -- Frequency Table Selection 2 -- -- SEL3 1–0 -- -- 7 -- -- -- -- -- 0 6 -- -- -- -- -- 0 5 -- -- -- -- -- 0 -- Bit 1 0 0 1 1 Frequency Controlled by FS (3:0) Table 2 Frequency Controlled by SEL (3:0) Table 6 Refer to Table 6 Bit 0 0 1 0 1 0 0 00 Function (See Table 7 for function details) Normal Operation (Reserved) Spread Spectrum On All Outputs Three-stated Data Byte 1 4 -- -- -- -- 0 3 46 SDRAM_F Clock Output Disable Low Active 1 2 49 CPU2 Clock Output Disable Low Active 1 1 51 CPU1 Clock Output Disable Low Active 1 0 52 CPU_F Clock Output Disable Low Active 1 7 -- -- -- -- 0 6 8 PCI_F Clock Output Disable Low Active 1 5 16 PCI5 Clock Output Disable Low Active 1 4 14 PCI4 Clock Output Disable Low Active 1 3 13 PCI3 Clock Output Disable Low Active 1 2 12 PCI2 Clock Output Disable Low Active 1 1 11 PCI1 Clock Output Disable Low Active 1 0 9 PCI0 Clock Output Disable Low Active 1 -- -- (Reserved) -- -- 0 (Reserved) Data Byte 2 (Reserved) Data Byte 3 7 6 -- -- -- -- 0 5 29 48MHz Clock Output Disable Low Active 1 4 30 24MHz Clock Output Disable Low Active 1 6 PRELIMINARY W150 Table 5. Data Bytes 0–5 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. 3 33, 32, 25, 24 2 Pin Name Bit Control Control Function 0 1 Default SDRAM12:15 Clock Output Disable Low Active 1 22, 21, 19, 18 SDRAM8:11 Clock Output Disable Low Active 1 1 39, 38, 36, 35 SDRAM4:7 Clock Output Disable Low Active 1 0 44, 43, 41, 40 SDRAM0:3 Clock Output Disable Low Active 1 Data Byte 4 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 54 IOAPIC_F Disabled Low Active 1 4 55 IOAPICO Disabled Low Active 1 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 2 REF1 Clock Output Disable Low Active 1 0 3 REF0 Clock Output Disable Low Active 1 Data Byte 5 7 PRELIMINARY W150 Table 6. Frequency Selections through Serial Data Interface Data Bytes Input Conditions Output Frequency Spread On Data Byte 0, Bit 3 = 1 Bit 2 SEL_3 Bit 6 SEL_2 Bit 5 SEL_1 Bit 4 SEL_0 CPU, SDRAM Clocks (MHz) PCI Clocks (MHz) Spread Percentage 1 1 1 1 133.3 33.3 (CPU/4) ± 0.5% Center 1 1 1 0 124 31 (CPU/4) ± 0.5% Center 1 1 0 1 150 37.5 (CPU/4) ± 0.5% Center 1 1 0 0 140 35 (CPU/4) ± 0.5% Center 1 0 1 1 105 35 (CPU/3) ± 0.5% Center 1 0 1 0 110 36.7 (CPU/3) ± 0.9% Center 1 0 0 1 115 38.3 (CPU/3) ± 0.5% Center 1 0 0 0 120 40 (CPU/3) ± 0.5% Center 0 1 1 1 100 33.3 (CPU/3) ± 0.5% Center 0 1 1 0 133.3 44.43 (CPU/3) ± 0.5% Center 0 1 0 1 112 37.3 (CPU/3) ± 0.5% Center 0 1 0 0 103 34.3 (CPU/3) ± 0.5% Center 0 0 1 1 66.8 33.4 (CPU/2) ± 0.5% Center 0 0 1 0 83.3 41.7 (CPU/2) ± 0.9% Center 0 0 0 1 75 37.5 (CPU/2) ± 0.5% Center 0 0 0 0 124 41.3 (CPU/3) ± 0.5% Center Table 7. Select Function for Data Byte 0, Bits 0:1 Input Conditions Output Conditions Data Byte 0 Function Bit 1 Bit 0 CPU_F, 1:2 PCI_F, PCI0:5 REF0:1, IOAPIC0,_F 48MHZ 24MHZ Normal Operation 0 0 Note 2 Note 2 14.318 MHz 48 MHz 24 MHz Test Mode 0 1 X1/2 CPU/(2 or 3) X1 X1/2 X1/4 Spread Spectrum 1 0 Note 2 Note 2 14.318 MHz 48 MHz 24 MHz Tristate 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note: 2. CPU and PCI frequency selections are listed in Table 2 and Table 6. 8 PRELIMINARY W150 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min) kV DC Electrical Characteristics: TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPU_F, 1:2= 100 MHz Outputs Loaded[3] 320 mA IDD 2.5V Supply Current CPU_F, 1:2= 100 MHz Outputs Loaded[3] 40 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 2.0 V VIH Input High Voltage VDD + 0.3 V IIL Input Low Current[4] –25 µA IIH Input High Current[4] 10 µA IIL Input Low Current (SEL100/66#) –5 µA IIH Input High Current (SEL100/66#) +5 µA 50 mV Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = 1 mA 3.1 VOH Output High Voltage CPU_F, 1:2, IOAPIC IOH = –1 mA 2.2 IOL Output Low Current CPU_F, 1:2 VOL = 1.25V 60 73 85 mA PCI_F, PCI1:5 VOL = 1.5V 96 110 130 mA IOAPIC0, IOAPIC_F VOL = 1.25V 72 92 110 mA REF0:1 VOL = 1.5V 61 71 80 mA 48-MHz VOL = 1.5V 60 70 80 mA 24-MHz VOL = 1.5V 60 70 80 mA SDRAM0:15, _F VOL = 1.5V 95 110 130 CPU_F, 1:2 VOH = 1.25V 43 60 80 mA PCI_F, PCI1:5 VOH = 1.5V 76 96 120 mA IOAPIC VOH = 1.25V 60 90 130 mA REF0:1 VOH = 1.5V 50 60 72 mA 48-MHz VOH = 1.5V 50 60 72 mA 24-MHz VOH = 1.5V 50 60 72 mA SDRAM0:15, _F VOH = 1.5V 75 95 120 IOH Output High Current V V Notes: 3. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors. 4. W150 logic inputs have internal pull-up devices (not to full CMOS level). Logic input FS3 has an internal pull-down device. 9 PRELIMINARY W150 DC Electrical Characteristics: (continued) TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input threshold Voltage[5] CLOAD Load Capacitance, Imposed on External Crystal[6] CIN,X1 X1 Input Capacitance[7] VDDQ3 = 3.3V Pin X2 unconnected 1.65 V 14 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Notes: 5. X1 input threshold voltage (typical) is VDDQ3/2. 6. The W150 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). AC Electrical Characteristics TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; V DDQ2 = 2.5V±5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25 15 tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. tSK Output Skew Measured on rising edge at 1.25V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 10 15.5 1 4 20 10 10.5 1 ns 4 V/ns 1 4 V/ns 45 55 % 250 250 ps 175 175 ps 3 3 ms 20 Ω PRELIMINARY W150 PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12.0 ns tL Low Time Duration of clock cycle below 0.4V 12.0 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V tF Output Fall Edge Rate Measured from 2.4V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle tSK 1 4 V/ns 1 4 V/ns 45 55 % Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance 1.5 Average value during switching transition. Used for determining series termination value. Ω 15 IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. 14.31818 Unit f Frequency, Actual Frequency generated by crystal oscillator tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. MHz Ω 15 REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments f Frequency, Actual Frequency generated by crystal oscillator Min. Typ. Max. 14.318 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 11 25 Ω PRELIMINARY W150 SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 22 pF) CPU = 66.8 MHz Parameter t P Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. 15.5 10 Max. Unit 10.5 ns Period Measured on rising edge at 1.5V 15 tH High Time Duration of clock cycle above 2.4V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.0 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 45 55 % tSK Output Skew Measured on rising and falling edge at 1.5V 250 ps tPD Propagation Delay Measured from SDRAMIN 3.7 3.7 ns Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 15 Ω 250 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter f Description Test Condition/Comments Min. Typ. Max. Unit Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz m/n PLL Ratio (48.008 – 48)/48 +167 ppm (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 12 25 Ω PRELIMINARY W150 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz CPU = 66.8/100 MHz Parameter Description f Frequency, Actual fD Test Condition/Comments Min. Determined by PLL divider ratio (see m/n below) Typ. Max. Unit 24.004 MHz Deviation from 24 MHz (24.004 – 24)/24 +167 ppm m/n PLL Ratio 57/34 (14.31818 MHz x 57/34 = 24.004 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ordering Information Ordering Code W150 Package Name H Package Type 56-Pin SSOP (300-mil) Document #: 38-00857-A 13 25 Ω PRELIMINARY W150 Package Diagram 56-Pin Shrink Small Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 © Cypress Semiconductor Corporation, 2000. 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