DATA SHEET MOS INTEGRATED CIRCUIT µPD43256B-X 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The µPD43256B-X is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. The µPD43256B-X is an extended-operating-temperature version of the µPD43256B (X version : TA = –25 to +85 °C). And A and B versions are low voltage operations. Battery backup is available. The µPD43256B-X is packed in 28-pin plastic TSOP (I) (8 x 13.4 mm). Features • 32,768 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150 ns (MAX.) • Operating ambient temperature: TA = –25 to +85 °C • Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) • Low VCC data retention: 2.0 V (MIN.) • /OE input for easy application Part number Access time Operating supply Operating ambient ns (MAX.) • µPD43256B-xxX Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) Note1 −25 to +85 45 50 2 70, 85 4.5 to 5.5 µPD43256B-AxxX 85 Note2, 100, 120 Note2 3.0 to 5.5 µPD43256B-BxxX Note2 100, 120 Note2, 150 Note2 2.7 to 5.5 40 Notes 1. TA ≤ 40 °C, VCC = 3.0 V 2. 100 s (MAX.) (VCC = 4.5 to 5.5 V) Version X This Data sheet can be applied to the version X. Each version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X. JAPAN D43256B-X Lot number The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M11012EJ4V0DSJ1 (4th edition) Date Published December 2000 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 1995 µPD43256B-X • Ordering Information Part number Package Access time ns (MAX.) µPD43256BGW-70X-9JL 28-PIN PLASTIC TSOP(I) 70 µPD43256BGW-85X-9JL (8x13.4) (Normal bent) 85 µPD43256BGW-A85X-9JL 85 µPD43256BGW-A10X-9JL 100 µPD43256BGW-A12X-9JL 120 µPD43256BGW-B10X-9JL 100 µPD43256BGW-B12X-9JL 120 µPD43256BGW-B15X-9JL 150 µPD43256BGW-70X-9KL 28-PIN PLASTIC TSOP(I) 70 µPD43256BGW-85X-9KL (8x13.4) (Reverse bent) 85 µPD43256BGW-A85X-9KL 85 µPD43256BGW-A10X-9KL 100 µPD43256BGW-A12X-9KL 120 µPD43256BGW-B10X-9KL 100 µPD43256BGW-B12X-9KL 120 µPD43256BGW-B15X-9KL 150 2 Data Sheet M11012EJ4V0DS Operating supply Operating ambient voltage temperature V °C 4.5 to 5.5 –25 to +85 Remark 3.0 to 5.5 A version 2.7 to 5.5 B version 4.5 to 5.5 3.0 to 5.5 A version 2.7 to 5.5 B version µPD43256B-X • Pin Configurations (Marking Side) /xxx indicates active low signal. 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) [µPD43256BGW-xxX-9JL] [µPD43256BGW-AxxX-9JL] [µPD43256BGW-BxxX-9JL] /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) [µPD43256BGW-xxX-9KL] [µPD43256BGW-AxxX-9KL] [µPD43256BGW-BxxX-9KL] A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11012EJ4V0DS 3 µPD43256B-X Block Diagram A0 Address buffer A14 Row decoder I/O1 Input data controller I/O8 Memory cell array 262,144 bits Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CS /OE /WE VCC GND Truth Table /CS /OE /WE Mode I/O Supply current H × × Not selected High impedance ISB L H H Output disable L × L Write DIN L L H Read DOUT ICCA Remark × : VIH or VIL 4 Data Sheet M11012EJ4V0DS µPD43256B-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC –0.5 –0.5 Note Note Unit to +7.0 V to VCC + 0.5 V Input / Output voltage VT Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter µPD43256B-xxX Symbol Condition µPD43256B-AxxX µPD43256B-BxxX MIN. MAX. MIN. MAX. MIN. MAX. Unit Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V High level input voltage VIH 2.4 VCC+0.5 2.4 VCC+0.5 2.4 VCC+0.5 V +0.4 V +85 °C Low level input voltage VIL Operating ambient temperature TA –0.3 Note –25 +0.6 –0.3 +85 Note +0.4 –25 +85 –0.3 Note –25 Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 5 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M11012EJ4V0DS 5 µPD43256B-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition µPD43256B-xxX MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 µA mA /CS = VIH or /WE = VIL • Operating supply current ICCA1 /CS = VIL, Minimum cycle time, II/O = 0 mA 45 ICCA2 /CS = VIL, II/O = 0 mA 15 ICCA3 /CS ≤ 0.2 V, Cycle = 1 MHz, 15 II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current High level output voltage Low level output voltage ISB /CS = VIH ISB1 /CS ≥ VCC − 0.2 V VOH1 IOH = –1.0 mA 2.4 VOH2 IOH = –0.1 mA VCC–0.5 VOL IOL = 2.1 mA 1.0 Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. 6 Data Sheet M11012EJ4V0DS 3 mA 50 µA V 0.4 V µPD43256B-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol µPD43256B-AxxX Test condition MIN. TYP. µPD43256B-BxxX MAX. MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0 µA mA /CS = VIH or /WE = VIL Operating supply current ICCA1 µPD43256B-A85X 45 – Minimum cycle time, µPD43256B-A10X 40 – µPD43256B-A12X 40 – µPD43256B-B10X – 40 µPD43256B-B12X – 40 µPD43256B-B15X – 40 VCC ≤ 3.3 V – 25 15 15 – 10 /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA, 15 15 VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V – 10 /CS = VIH 3 3 – 2 /CS = VIL, II/O = 0 mA ICCA2 /CS = VIL, II/O = 0 mA VCC ≤ 3.3 V ICCA3 Standby supply current ISB VCC ≤ 3.3 V ISB1 /CS ≥ VCC − 0.2 V 1.0 VCC ≤ 3.3 V High level output voltage VOH1 VOH2 Low level output voltage VOL VOL1 50 1.0 – µA 25 IOH = –1.0 mA, VCC ≥ 4.5 V 2.4 2.4 IOH = –0.5 mA, VCC < 4.5 V 2.4 2.4 VCC– VCC– 0.1 0.1 IOH = –0.02 mA 50 mA V IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 0.4 IOL = 1.0 mA, VCC < 4.5 V 0.4 0.4 IOL = 0.02 mA 0.1 0.1 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. Data Sheet M11012EJ4V0DS 7 µPD43256B-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [µPD43256B-70X, µPD43256B-85X] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 0.6 V Output Waveform Output Load AC characteristics should be measured with the following output load conditions. Figure 1 Figure 2 (tAA, tACS, tOE, tOH) (tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW) +5 V +5 V 1.8 kΩ 1.8 kΩ I/O (Output) I/O (Output) 990 Ω 990 Ω 100 pF CL 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [µPD43256B-A85X, µPD43256B-A10X, µPD43256B-A12X, µPD43256B-B10X, µPD43256B-B12X, µPD43256B-B15X] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 0.4 V Output Waveform • Output Load AC characteristics should be measured with the following output load conditions. 8 tAA, tACS, tOE, tOH tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW 1TTL + 50 pF 1TTL + 5 pF Data Sheet M11012EJ4V0DS µPD43256B-X Read Cycle (1/2) Parameter VCC ≥ 4.5 V Symbol • µPD43256B-70X Unit µPD43256B-85X µPD43256B-AxxX Condition µPD43256B-BxxX MIN. MAX. MIN. MIN. 85 MAX. Read cycle time tRC Address access time tAA 70 85 100 ns /CS access time tACS 70 85 100 ns /OE access time tOE 35 40 50 ns Output hold from address change tOH 10 10 10 ns /CS to output in low impedance tCLZ 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /CS to output in high impedance tCHZ 30 30 35 ns /OE to output in high impedance tOHZ 30 30 35 ns Note 70 MAX. 100 ns Note See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle (2/2) Parameter VCC ≥ 3.0 V Symbol VCC ≥ 2.7 V Unit Con- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256BA85X A10X A12X B10X B12X B15X MIN. MAX. 85 MIN. MAX. 100 MIN. MAX. 120 MIN. MAX. 100 MIN. MAX. 120 MIN. dition MAX. Read cycle time tRC 150 ns Address access tAA 85 100 120 100 120 150 ns /CS access time tACS 85 100 120 100 120 150 ns /OE access time tOE 50 60 60 60 60 70 ns Output hold from tOH 10 10 10 10 10 10 ns tCLZ 10 10 10 10 10 10 ns tOLZ 5 5 5 5 5 5 ns Note time address change /CS to output in low impedance /OE to output in low impedance /CS to output in tCHZ 35 35 40 35 40 50 ns tOHZ 35 35 40 35 40 50 ns high impedance /OE to output in high impedance Note See the output load. Remark These AC characteristics are in common regardless of package types. Data Sheet M11012EJ4V0DS 9 µPD43256B-X Read Cycle Timing Chart tRC Address (Input) tAA tOH /CS (Input) tCHZ tACS tCLZ /OE (Input) tOHZ tOE tOLZ I/O (Output) Remark 10 High impedance In read cycle, /WE should be fixed to high level. Data Sheet M11012EJ4V0DS Data out µPD43256B-X Write Cycle (1/2) Parameter VCC ≥ 4.5 V Symbol • µPD43256B-70X µPD43256B-85X MIN. MIN. Unit Con- µPD43256B-AxxX dition µPD43256B-BxxX MAX. MAX. MIN. MAX. Write cycle time tWC 70 85 100 ns /CS to end of write tCW 60 70 80 ns Address valid to end of write tAW 60 70 80 ns Write pulse width tWP 55 60 70 ns Data valid to end of write tDW 30 35 40 ns Data hold time tDH 5 5 5 ns Address setup time tAS 0 0 0 ns Write recovery time tWR 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 30 30 5 35 5 Note ns 5 ns See the output load. Note Remark These AC characteristics are in common regardless of package types and L, LL versions. Write Cycle (2/2) Parameter VCC ≥ 3.0 V Symbol VCC ≥ 2.7 V Unit Con- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256BA85X A10X A12X B10X B12X B15X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. dition MAX. Write cycle time tWC 85 100 120 100 120 150 ns /CS to end of write tCW 70 70 90 70 90 100 ns Address valid to tAW 70 70 90 70 90 100 ns Write pulse width tWP 60 60 80 60 80 90 ns Data valid to end tDW 60 60 70 60 70 80 ns Data hold time tDH 5 5 5 5 5 5 ns Address setup time tAS 0 0 0 0 0 0 ns Write recovery time tWR 0 0 0 0 0 0 ns /WE to output in tWHZ end of write of write 35 35 40 35 40 40 ns Note high impedance Output active tOW 5 5 5 5 5 5 ns from end of write Note See the output load. Remark These AC characteristics are in common regardless of package types. Data Sheet M11012EJ4V0DS 11 µPD43256B-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 12 Data Sheet M11012EJ4V0DS µPD43256B-X Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tDW tDH High impedance Data in I/O (Input) High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M11012EJ4V0DS 13 µPD43256B-X Low VCC Data Retention Characteristics (TA = −25 to +85 °C) Parameter Symbol Test Condition MIN. TYP. MAX. Unit 5.5 V VCCDR /CS ≥ VCC − 0.2 V Data retention supply current ICCDR VCC = 3.0 V, /CS ≥ VCC − 0.2 V Chip deselection to data retention mode tCDR 0 ns tR 5 ms Data retention supply voltage Operation recovery time 2.0 0.5 Note 2 µA (TA ≤ 40 °C), 7 µA (TA ≤ 70 °C) Data Retention Timing Chart tCDR Data retention mode VCC 4.5 V Note /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state. 14 Data Sheet M11012EJ4V0DS tR 20 Note µA µPD43256B-X • Package Drawings 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end S R 14 Q 15 P A J I G S L B C H N S D M M K NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM A MILLIMETERS 8.0±0.1 B C 0.6 MAX. 0.55 (T.P.) D 0.22 +0.08 −0.07 G H 1.0 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L 0.5±0.1 M 0.08 N 0.10 P 13.4±0.2 Q 0.1±0.05 R S 3° +7° −3° 1.2 MAX. P28GW-55-9JL-2 Data Sheet M11012EJ4V0DS 15 µPD43256B-X 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end Q R 14 15 S K N H D S L M M C B S G I J A P NOTE 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM MILLIMETERS A 8.0±0.1 B C 0.6 MAX. 0.55 (T.P.) D 0.22 +0.08 −0.07 G H 1.0 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L M 0.5±0.1 0.08 N 0.10 P 13.4±0.2 Q 0.1±0.05 R 3° +7° −3° S 1.2 MAX. P28GW-55-9KL-2 16 Data Sheet M11012EJ4V0DS µPD43256B-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD43256B-X. Types of Surface Mount Device µPD43256BGW-xxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD43256BGW-xxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) µPD43256BGW-AxxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD43256BGW-AxxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) µPD43256BGW-BxxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) µPD43256BGW-BxxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent) Data Sheet M11012EJ4V0DS 17 µPD43256B-X [MEMO] 18 Data Sheet M11012EJ4V0DS µPD43256B-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M11012EJ4V0DS 19 µPD43256B-X • The information in this document is current as of December, 2000. The information is subject to change without notice. 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