ETC UPD78P048AGF-3B9

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78P048A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78P048A is a product in the µPD78044F subseries within the 78K/0 series, in which the internal ROM
of the µPD78042F, 78043F, 78044F, and 78045F is replaced with one-time PROM or EPROM.
As the µPD78P048A is user-programmable, it is ideal for evaluation in system development, short-run and multipledevice production, and early start-up.
Caution The µPD78P048AKL-S does not provide the reliability intended for mass production of user
systems. Use this model only for experiments and evaluation of functions.
Details of functions are described in the User's Manuals shown below. Be sure to read in design.
µPD78044F subseries User's Manual: U10908E
78K/0 series User's Manual -Instruction: U12326E
FEATURES
• Pin compatible with mask ROM products (except the VPP pin)
• Internal PROM: 60K bytesNote 1
• µPD78P048AKL-S: Reprogrammable. (ideal for system evaluation)
• µPD78P048AGF-3B9: Programmable only once (ideal for limited production)
• Internal high-speed RAM: 1024 bytesNote 1
• Internal expansion RAM: 1024 bytesNote 2
• Buffer RAM: 64 bytes
• FIPTM display RAM: 48 bytes
• Operable in the same supply voltage as mask ROM products: VDD = 2.7 to 6.0 V (except A/D converter)
A/D converter supply voltage: AVDD = 4.0 to 6.0
Notes 1.
2.
Internal PROM and internal high-speed RAM capacities can be changed by memory size switching register (IMS).
Internal expansion RAM capacity can be changed by internal expansion RAM size switching
register (IXS).
Remark For the difference between ROM products and mask ROM products, refer to 1. DIFFERENCES
BETWEEN µPD78P048A AND MASK ROM PRODUCTS.
In this document, “PROM” is used in parts common to one-time PROM products and EPROM products.
The information in this document is subject to change without notice.
Document No. U10611EJ2V0DS00 (2nd edition)
Date Published June 1997 N
Printed in Japan
The mark
shows major revised points.
©
1995
µPD78P048A
ORDERING INFORMATION
Part Number
Package
Internal ROM
Quality Grade
µPD78P048AGF-3B9
µPD78P048AKL-S
80-pin plastic QFP (14 × 20 mm)
80-pin ceramic WQFN
One-time PROM
EPROM
Standard
Not applicable
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD78P048A
78K/0 SERIES PRODUCT DEVELOPMENT
The following shows the 78K/0 Series products development. Subseries name are shown inside frames.
Products in
mass production
Products under
development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
µPD78075B
µPD78075BY
µPD78078
µPD78078Y
µ PD78070A
µPD78070AY
µPD780018Note µ PD780018YNote
µ PD780058
µ PD780058YNote
µ PD78058F
µ PD78058FY
µ PD78054
µ PD78054Y
µ PD780034
µ PD780034Y
µ PD780024
µPD780024Y
µ PD78014H
µPD78018F
µ PD78018FY
µPD78014
µ PD78014Y
µPD780001
µPD78002
µPD78002Y
µPD78083
EMI-noise reduced version of the µ PD78078
A timer was added to the µPD78054 and external interface was enhanced
ROM-less version of the µPD78078
Serial I/O of the µ PD78078 was enhanched and the function is limited
Serial I/O of the µ PD78054 was enhanced and EMI-noise was reduced
EMI-noise reduced version of the µ PD78054
UART and D/A converter were added to the µ PD78014 and I/O was enchanced
A/D converter of the µPD780024 was enchanced
Serial I/O of the µPD78018F was added and EMI-noise was reduced
EMI-noise reduced version of µ PD78018F
Low-voltage (1.8 V) operation version of the µPD78014, with larger
selection of ROM and RAM capacities
An A/D converter and 16-bit timer were added to the µPD78002
An A/D converter was added to the µPD78002
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
64-pin
78K/0
Series
A/D converter of the µPD780924 was enhanced
µ PD780964
µ PD780924
On-chip inverter control circuit and UART. EMI-noise was reduced.
FIP drive
100-pin
100-pin
80-pin
80-pin
The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53
The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48
N-ch open drain was added to the µPD78044F, Display output total: 34
µPD780208
µ PD780228
µPD78044H
µPD78044F
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
100-pin
100-pin
µ PD780308
µPD780308Y
The SIO of the µPD78064 was enhanced and ROM, RAM capacity increased
µ PD78064B
µPD78064
µ PD78064Y
EMI-noise reduced version of the µPD78064
Basic subseries for driving LCDs, On-chip UART
IEBusTM supported
80-pin
80-pin
µ PD78098B
µPD78098
EMI-noise reduced version of the µPD78098
An IEBus controller was added to the µ PD78054
Meter control
80-pin
100-pin
µ PD780973
µ PD780805
General-purpose version of the µ PD780805 controller/driver for driving automobile meters
On-chip controller/driver for automobile meters
LV
64-pin
µ PD78P0914
On-chip PWM output, LV digital code decoder, and Hsync counter
Note Under planning
3
µPD78P048A
The following lists the main functional differences between subseries products.
Function
Subseries Name
Control
ROM
Capacity
µPD78075B
32 K-40 K
µPD78078
48 K-60 K
µPD78070A
–
µPD780018
48 K-60 K
µPD780058
24 K-60 K
µPD78058F
48 K-60 K
µPD78054
16 K-60 K
µPD780034
8 K-32 K
Timer
8-bit 16-bit Watch WDT
8-bit 10-bit
A/D A/D
8-bit
D/A
4 ch
8 ch
2 ch
1 ch
1 ch
1 ch
–
2 ch
–
8 ch
8 K-60 K
µPD78014
8 K-32 K
µPD780001
8K
µPD78002
8 K-16 K
1.8 V
61
2.7 V
88
2 ch
3 ch (time division
UART: 1ch)
68
1.8 V
3 ch (UART: 1 ch)
69
2.7 V
8 ch
–
3 ch (UART: 1 ch, time
51
1.8 V
division 3-wire: 1 ch)
–
53
2.7 V
–
µPD78083
–
–
–
8 ch
µPD780964
control
µPD780924
FIP
µPD780208
32 K-60 K
2 ch
1 ch
1 ch
drive
µPD780228
48 K-60 K
3 ch
–
–
µPD78044H
32 K-48 K
2 ch
1 ch
1 ch
µPD78044F
16 K-40 K
µPD780308
48 K-60 K
µPD78064B
32 K
µPD78064
16 K-32 K
IEBus
µPD78098B
40 K-60 K
supported
µPD78098
32 K-60 K
Meter
µPD780973
control
LV
3 ch
Note
1 ch
1 ch
Inverter
8 K-32 K
88
2 ch (time division
3-wire: 1ch)
2 ch
µPD78018F
VDD MIN. External
Value Expansion
–
µPD78014H
–
1 ch
1 ch
39
–
53
–
8 ch
8 ch
–
8 ch
–
1 ch (UART: 1 ch)
33
1.8 V
–
2 ch (UART: 2 ch)
47
2.7 V
–
2 ch
74
2.7 V
1 ch
72
4.5 V
68
2.7 V
57
2.0 V
–
–
2 ch
2 ch
1 ch
1 ch
1 ch
8 ch
–
–
3 ch (time division
UART: 1ch)
–
2 ch (UART : 1 ch)
2 ch
1 ch
1 ch
1 ch
8 ch
–
2 ch
3 ch (UART : 1 ch)
69
2.7 V
24 K-32 K
3 ch
1 ch
1 ch
1 ch
5 ch
–
–
2 ch (UART : 1 ch)
56
4.5 V
µPD780805
40 K-60 K
2 ch
39
2.7 V
µPD78P0914
32 K
6 ch
54
4.5 V
Note 10-bit timer: 1 channel
4
3 ch (UART : 1 ch)
I/O
2.0 V
µPD780024
LCD
drive
Serial
Interface
8 ch
–
–
1 ch
8 ch
–
–
2 ch
–
µPD78P048A
FUNCTION DESCRIPTION
Item
Internal
memory
Function
bytesNote 1
PROM
60 K
High-speed RAM
1024 bytesNote 1
Expansion RAM
1024 bytesNote 2
Buffer RAM
64 bytes
FIP display RAM
48 bytes
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
Instruction execution time variable function is built in.
When main system clock is selected
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (when operating at 5.0 MHz)
When subsystem clock is selected
122 µs (when operating at 32.768 kHz)
Instruction set
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, boolean operation)
I/O ports
(including FIP dual-function pin)
Total
• CMOS input
• CMOS input/output
• N-ch open-drain input/output
• P-ch open-drain input/output
• P-ch open-drain output
FIP controller/driver
Display output total
• No. of segments
• No. of digits
:
:
:
:
:
:
68
2
27
5
16
18
: 34
: 9 to 24
: 2 to 16
A/D converter
• 8-bit resolution × 8 ch
• Supply voltage: AVDD = 4.0 to 6.0 V
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable
: 1 ch
• 3-wire serial I/O mode (on-chip max. 64 bytes automatic data transmit/receive function): 1 ch
Timer
•
•
•
•
•
Timer output
3 (14-bit PWM output capability : 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(When operating at main system clock 5.0 MHz)
32.768 kHz (when operating at subsystem clock 32.768 kHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz (when operating at main system clock 5.0 MHz)
Vectored
interrupt
sources
Maskable
Internal: 10, External: 4
Non-maskable
Internal: 1
Software
1
16-bit timer/event counter :
8-bit timer/event counter :
Clock timer
:
Watchdog timer
:
6-bit up/down counter
:
1
2
1
1
1
channel
channels
channel
channel
channel
Test input
Internal: 1
Supply voltage
VDD = 2.7 to 6.0 V
Package
• 80-pin plastic QFP (14 × 20 mm)
• 80-pin ceramic WQFN
Notes 1. Internal PROM/internal high-speed RAM capacity can be changed by memory size switching register (IMS).
2. Internal expansion RAM capacity can be changed by internal expansion RAM size switching register (IXS).
5
µPD78P048A
PIN CONFIGURATION (Top View)
(1) Normal operating mode
• 80-pin plastic QFP (14 × 20 mm)
µPD78P048AGF-3B9
• 80-pin ceramic WQFN
P113/FIP21
P112/FIP20
P111/FIP19
P110/FIP18
P107/FIP17
P106/FIP16
VLOAD
P105/FIP15
P94/FIP6
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
P114/FIP22
P93/FIP5
2
63
P115/FIP23
P92/FIP4
3
62
P116/FIP24
P91/FIP3
4
61
P117/FIP25
P90/FIP2
5
60
P120/FIP26
P81/FIP1
6
59
P121/FIP27
P80/FIP0
7
58
P122/FIP28
VDD
8
57
P123/FIP29
P27/SCK0
9
56
P124/FIP30
P26/SO0/SB1
10
55
P125/FIP31
P25/SI0/SB0
11
54
P126/FIP32
P24/BUSY
12
53
P127/FIP33
P23/STB
13
52
VDD
P22/SCK1
14
51
P70
P21/SO1
15
50
P71
P20/SI1
16
49
P72
RESET
17
48
VPP
P74
18
47
P00/INTP0/TI0
3. Connect AVSS pin to VSS.
P33/TI1
P32/TO2
P34/TI2
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P35/PCL
P14/ANI4
P36/BUZ
P31/TO1
X2
42
P37
23
X1
P30/TO0
P15/ANI5
VSS
P03/INTP3/CI0
43
XT2
44
22
AVREF
21
P16/ANI6
P04/XT1
P17/ANI7
AVDD
P02/INTP2
P10/ANI0
P01/INTP1
45
P11/ANI1
46
20
P12/ANI2
19
P13/ANI3
P73
AVSS
Cautions 1. Connect VPP pin directly to VSS.
2. Connect AVDD pin to VDD.
6
P104/FIP14
P103/FIP13
P102/FIP12
P101/FIP11
P100/FIP10
P97/FIP9
P96/FIP8
P95/FIP7
µPD78P048AKL-S
µPD78P048A
P00 to P04
: Port 0
SCK0, SCK2
: Serial Clock
P10 to P17
P20 to P27
: Port 1
: Port 2
PCL
BUZ
: Programmable Clock
: Buzzer Clock
P30 to P37
P70 to 74
: Port 3
: Port 7
STB
BUSY
: Strobe
: Busy
P80, P81
P90 to P97
: Port 8
: Port 9
FIP0 to FIP33
VLOAD
: Fluorescent Indicator Panel
: Negative Power Supply
P100 to P107
P110 to P117
: Port 10
: Port 11
X1, X2
XT1, XT2
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
P120 to 127
INTP0 to INTP3
: Port 12
: Interrupt from Peripherals
RESET
ANI0 to ANI7
: Reset
: Analog Input
TI0 to TI2
TO0 to TO2
: Timer Input
: Timer Output
AVDD
AVSS
: Analog Power Supply
: Analog Ground
CI0
SB0, SB1
: Clock Input
: Serial Bus
AVREF
VDD
: Analog Reference Voltage
: Power Supply
SI0, SI1
SO0, SO1
: Serial Input
: Serial Output
VPP
VSS
: Programming Power Supply
: Ground
7
µPD78P048A
(2) PROM programming mode
• 80-pin plastic QFP (14 × 20 mm)
µPD78P048AGF-3B9
• 80-pin ceramic WQFN
A11
A10
A16
A8
(L)
VSS
(L)
µPD78P048AKL-S
59
7
58
VDD
8
57
A7
9
56
A6
10
55
A5
11
54
A4
12
53
A3
13
52
A2
14
51
A1
15
50
A0
16
49
RESET
17
48
18
47
A9
19
46
20
45
(L)
PGM
21
44
22
43
(L)
D0
CE
23
42
D1
OE
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
D2
VSS
(L)
(L)
Cautions 1. (L)
2. VSS
(L)
VDD
(L)
VPP
D3
(L)
D4
6
D5
60
D6
A15
5
D7
61
Open
A14
4
(L)
VSS
(L)
62
(L)
A13
3
Open
63
VSS
A12
2
VDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
: Individually connect to VSS via a pull-down resistor.
: Connect to ground.
3. RESET : Set to low level.
4. Open : No connection.
8
A0 to A16 : Address Bus
RESET: Reset
D0 to D7 : Data Bus
CE
: Chip Enable
VDD
VPP
: Power Supply
: Programming Power Supply
OE
PGM
VSS
: Ground
: Output Enable
: Program
µPD78P048A
BLOCK DIAGRAM
TO0/P30
TI0/INTP0/P00
16-bit TIMER/
EVENT COUNTER
TO1/P31
TI1/P33
8-bit TIMER/
EVENT COUNTER1
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER2
PORT0
P00
P01-P03
P04
PORT1
P10-P17
PORT2
P20-P27
PORT3
P30-P37
PORT7
P70-P74
PORT8
P80, P81
PORT9
P90-P97
PORT10
P100-P107
PORT11
P110-P117
PORT12
P120-P127
FIP
CONTROLLER/
DRIVER
FIP0-FIP33
WATCHDOG TIMER
WATCH TIMER
CI0/INTP3/P03
SERIAL
INTERFACE0
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE1
INTP0/TI0/P00INTP3/CI0/P03
BUZ/P36
PROM
6-bit UP/DOWN
COUNTER
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
ANI0/P10ANI7/P17
AVDD
AVSS
AVREF
78K/0
CPU CORE
RAM
A/D CONVERTER
INTERRUPT
CONTROL
VLOAD
RESET
BUZZER OUTPUT
X1
PCL/P35
SYSTEM
CONTROL
CLOCK OUTPUT
CONTROL
VDD
VSS
VPP
X2
XT1/P04
XT2
9
µPD78P048A
CONTENTS
1. DIFFERENCES BETWEEN µPD78P048A AND MASK ROM PRODUCTS ................................... 11
2. PIN FUNCTION ................................................................................................................................ 12
2.1
2.2
Pins in Normal Operating Mode .........................................................................................................
Pins in PROM Programming Mode .....................................................................................................
12
15
2.3
Pin Input/Output Circuits and Recommended Connection of Unused Pins ..................................
16
3. MEMORY SIZE SWITCHING REGISTER (IMS) .............................................................................. 19
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................. 20
5. PROM PROGRAMMING .................................................................................................................. 21
5.1
Operating Modes ..................................................................................................................................
21
5.2
5.3
PROM Write Procedure .......................................................................................................................
PROM Read Procedure .......................................................................................................................
23
27
6. ERASURE METHOD (µPD78P048AKL-S ONLY) ........................................................................... 28
7. ERASURE WINDOW SEAL (µPD78P048AKL-S ONLY) ................................................................ 28
8. ONE-TIME PROM PRODUCTS SCREENING ................................................................................. 28
9. ELECTRICAL SPECIFICATIONS .................................................................................................... 29
10. CHARACTERISTIC CURVE (REFERENCE VALUE) ..................................................................... 56
11. PACKAGE DRAWINGS ................................................................................................................... 61
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 63
APPENDIX A. DEVELOPMENT TOOLS .............................................................................................. 64
APPENDIX B. RELATED DOCUMENTS .............................................................................................. 68
10
µPD78P048A
1. DIFFERENCES BETWEEN µPD78P048A AND MASK ROM PRODUCTS
The µPD78P048A is a single-chip microcontroller with an on-chip one-time writable PROM or with an on-chip
EPROM which has program write, erasure and rewrite capability.
It is possible to make all the functions except for PROM specification, and mask option, to the same as those of
mask ROM products by setting the memory size switching register (IMS) and the internal expansion RAM size
switching register (IXS).
Differences between the µPD78P048A and mask ROM products (µPD78042F, 78043F, 78044F, and 78045F) are
shown in Table 1-1.
Table 1-1. Differences between µPD78P048A and Mask ROM Products
µPD78P048A
Item
Mask ROM Products
Internal ROM structure
One-time PROM/EPROM
Mask ROM
Internal ROM capacity
60K bytes
µPD78042F:
µPD78043F:
µPD78044F:
µPD78045F:
16K bytes
24K bytes
32K bytes
40K bytes
Internal high-speed RAM capacity
1024K bytes
µPD78042F:
µPD78043F:
µPD78044F:
µPD78045F:
512 bytes
512 bytes
1024 bytes
1024 bytes
Changes of internal ROM and internal high-speed
AvailableNotes 1
Not available
Change of internal expansion RAM capacity by
internal expansion RAM size switching register
(IXS)
AvailableNotes 2
Not available
IC pin
No
Yes
VPP pin
Yes
No
RAM capacities by memory size switching register
(IMS)
Mask option with internal pull-down resistor for pins No
P30-P37, P106, P107, P110-P117, and P120-P127.
Yes
Mask option with internal pull-up resistor for pins
P70-P74.
No
Yes
Electrical characteristics
Refer to the Data Sheet for each product.
Notes 1. The internal PROM becomes to 60K bytes and the internal high-speed RAM becomes 1024 bytes by the
RESET input.
2. The internal expansion RAM becomes to 1024 bytes by the RESET input.
Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using
a mask ROM version instead of the PROM version for processes between prototype development
and full production, be sure to fully evaluate the CS of the mask ROM version (not ES).
11
µPD78P048A
2. PIN FUNCTION
2.1 Pins in Normal Operating Mode
(1) Port pins (1/2)
Pin Name
Input/Output
P00
Input
P01
Input/output
P02
On Reset
Dual-Function Pin
Port 0
Input only Input
Input
INTP0/TI0
5-bit input/
Input/Output is specifiable bit-wise.
When used as the input port, it is
possible to use an on-chip pull-up
resistor in software.
Input
Input only
Input
XT1
Input
ANI0 to ANI7
Input
SI1
output port
P03
P04Note 1
Input
P10 to P17
Input/output
P20
Function
Input/output
P21
P22
P23
Port 1
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to
use an on-chip pull-up resistor in software.Note 2
Port 2
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to
use an on-chip pull-up resistor in software.
INTP1
INTP2
INTP3/CI0
SO1
SCK1
STB
P24
BUSY
P25
SI0/SB0
P26
SO0/SB1
P27
SCK0
P30
P31
P32
P33
P34
Input/output
Port 3
8-bit input/output port
Input/output is specifiable bit-wise.
Direct LED drive capability.
When used as the input port, it is possible to
use an on-chip pull-up resistor in software.
Input
TO0
TO1
TO2
TI1
TI2
P35
PCL
P36
BUZ
P37
–
Notes 1. When the P04/XT1 pins are used as input ports, processor clock control register (PCC) bit 6 (FRC) should
be set to 1 (the subsystem clock oscillator incorporated feedback resistor should not be used).
2. When the P10/ANI0 to P17/ANI7 pins are used as A/D converter analog input, port 1 should be set to the
input mode. The on-chip pull-up resistor is not automatically used.
12
µPD78P048A
(1) Port pins (2/2)
Pin Name
Input/Output
P70 to P74
Input/output
P80, P81
Output
P90 to P97
Function
On Reset
Dual-Function Pin
Input
—
Port 8
P-ch open-drain 2-bit high-voltage output port.
Direct LED drive capability.
Pull-down resistor (connected to VLOAD) on chip.
Output
FIP0, FIP1
Output
Port 9
P-ch open-drain 8-bit high-voltage output port.
Direct LED drive capability.
Pull-down resistor (connected to VLOAD) on chip.
Output
FIP2 to FIP9
P100 to P107
Output
Port 10
P-ch open-drain 8-bit high-voltage output port.
Direct LED drive capability.
Pull-down resistor (connected to VLOAD) on chip in
P100 to P105.
Output
FIP10 to FIP17
P110 to P117
Input/output
Port 11
P-ch open-drain 8-bit high-voltage output port.
Input/output is specifiable bit-wise.
Input
FIP18 to FIP25
P120 to P127
Input/output
Port 12
P-ch open-drain 8-bit high-voltage output port.
Direct LED drive capability.
Input/output is specifiable bit-wise.
Input
FIP26 to FIP33
Port 7
N-ch open-drain 5-bit input/output port.
Direct LED drive capability.
Input/output is specifiable bit-wise.
13
µPD78P048A
(2) Non-port pins (1/2)
Pin Name
Input/Output
INTP0
Input
INTP1
Function
Specifiable valid edges (rising edge, falling edge,
and both rising and falling edges).
External interrupt request input
On Reset
Dual-Function Pin
Input
P00/TI0
P01
INTP2
P02
INTP3
SI0
Input
Falling edge detection external interrupt request input
Input
P03/CI0
Serial data input of the serial interface
Input
P25/SB0
SI1
SO0
P20
Output
Serial data output of the serial interface
Input
SO1
SB0
P21
Input/output
Serial data input/output of the serial interface
Input
SB1
SCK0
P26/SB1
P25/SI0
P26/SO0
Input/output
Serial clock input/output of the serial interface
Input
SCK1
P27
P22
STB
Output
Serial interface automatic transmit/receive strobe output
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input
Input
P24
TI0
Input
External count clock input to 16-bit timer (TM0)
Input
P00/INTP0
TI1
External count clock input to 8-bit timer (TM1)
P33
TI2
External count clock input to 8-bit timer (TM2)
P34
TO0
Output
16-bit timer (TM0) output (shared with 14-bit PWM output)
Iutput
P30
TO1
8-bit timer (TM1) output
P31
TO2
8-bit timer (TM2) output
P32
CI0
Input
Clock input of the 6-bit up/down counter
Input
P03/INTP3
PCL
Output
Clock output (for main system clock, subsystem
clock trimming)
Input
P35
BUZ
Output
Buzzer output
Input
P36
FIP0, FIP1
Output
FIP controller/driver digit output high-voltage highcurrent output
Output
P80, P81
FIP2 to FIP9
P90 to P97
FIP10 to FIP15
Output
FIP controller/driver digit/segment output highvoltage high-current output
Output
P100 to P105
FIP16, FIP17
Output
FIP controller/driver segment output high-voltage
output
Output
P106, P107
Input
P110 to P117
FIP18 to FIP25
FIP26 to FIP33
P120 to P127
VLOAD
—
ANI0 to ANI7
Input
A/D converter analog input
AVREF
Input
AVSS
AVDD
14
FIP controller/driver pull-down resistor connection
—
—
Input
P10 to P17
A/D converter reference voltage input
—
—
—
A/D converter ground potential. Connected to VSS
—
—
—
A/D converter analog power supply. Connected to VDD
—
—
µPD78P048A
(2) Non-port pins (2/2)
Pin Name
Input/Output
RESET
Input
X1
Input
X2
—
XT1
Input
XT2
—
VDD
—
VPP
VSS
Function
On Reset
Dual-Function Pin
System reset input
—
—
Main system clock oscillation crystal connection
—
—
—
—
Input
P04
—
—
Positive power supply
—
—
—
Directly connected to VSS
—
—
—
Ground potential
—
—
Subsystem clock oscillation crystal connection
2.2 Pins in PROM Programming Mode
Pin Name
Input/Output
Function
RESET
Input
PROM programming mode setting
When +5 V or +12.5 V is applied to the VPP pin and a low level signal is applied to the
RESET pin, this chip is set in the PROM programming mode.
VPP
Input
PROM programming mode setting and high-voltage applied during program write/
verification
A0 to A16
Input
Address bus
D0 to D7
Input/output
CE
Input
PROM enable input/program pulse input
OE
Input
Read strobe input to PROM
PGM
Input
Program/program inhibit input in PROM programing mode.
VDD
—
Positive power supply
VSS
—
Ground potential
Data bus
15
µPD78P048A
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1.
For the configuration of each type of input/output circuit, refer to Figure 2-1.
Table 2-1. Type of Input/Output Circuit of Each Pin
Pin Name
Input/Output
Circuit Type
Input/Output
2
Input
8-A
Input/output
P04/XT1
16
Input
P10A/ANI0 to P17/AN7
11
Input/output
P20/SI1
8-A
P21/SO1
5-A
P22/SCK1
8-A
P23/STB
5-A
P24/BUSY
8-A
P00/TI0/INTP0
P01/INTP1
Recommended Connecting
Method when Unused
Connect to VSS.
Individually connect to VSS via resistor
P02/INTP2
P03/INTP3/CI0
Connect to VDD or VSS.
Individually connect to VDD or VSS via resistor
P25/SI0/SB0
P26/SO0/SB1
10-A
P27/SCK0
P30/TO0
P31/TO1
5-A
P32/TO2
P33/TI1
8-A
P34/TI2
P35/PCL
5-A
P36/BUZ
P37
P70 to P74
P80/FIP0, P81/FIP1
13-D
14
Output
Leave open.
P90/FIP2 to P97/FIP9
P100/FIP10 to P105/FIP15
P106/FIP16, P107/FIP17
14-B
P110/FIP18 to P117/FIP25
15-B
Input/output
RESET
2
Input
XT2
16
–
AVREF
–
Individually connect to VDD or VSS via resistor
P120/FIP26 to P127/FIP33
—
Leave open
Connect to VSS
AVDD
Connect to VDD
AVSS
Connect to VSS
VLOAD
VPP
16
Directly connect to VSS
µPD78P048A
Figure 2-1. List of Pin Input/Output Circuits (1/2)
Type 2
Type 10-A
VDD
pull-up
enable
P-ch
VDD
IN
data
P-ch
IN/OUT
open drain
output disable
Schmitt-triggered input with hysteresis characteristics
Type 5-A
pull-up
enable
P-ch
data
P-ch
IN/OUT
P-ch
IN/OUT
output
disable
P-ch
VDD
VDD
data
VDD
Type 11
VDD
pull-up
enable
N-ch
output
disable
Comparator
N-ch
P-ch
+
N-ch
–
input
enable
N-ch
VREF (Threshold voltage)
input
enable
Type 8-A
Type 13-D
VDD
IN/OUT
pull-up
enable
data
output disable
P-ch
N-ch
VDD
data
VDD
P-ch
IN/OUT
output
disable
N-ch
RD
P-ch
Middle-high voltage input buffer
17
µPD78P048A
Figure 2-1. List of Pin Input/Output Circuits (2/2)
Type 14
Type 15-B
V DD
V DD
V DD
V DD
P-ch
P-ch
data
P-ch
IN/OUT
P-ch
N-ch
data
OUT
N-ch
V LOAD
Type 14-B
RD
N-ch
Type 16
feed back
cut-off
V DD
V DD
P-ch
P-ch
data
P-ch
OUT
N-ch
XT1
18
XT2
µPD78P048A
3. MEMORY SIZE SWITCHING REGISTER (IMS)
This is a register to disable use of part of internal memories by software. By setting this memory size switching
register (IMS), it is possible to get the same memory mapping as that of mask ROM product having different internal
memories.
The IMS is set up by the 8-bit memory manipulation instruction.
CFH will result by the RESET input.
Figure 3-1. Memory Size Switching Register Format
Symbol
IMS
7
6
5
RAM2 RAM1 RAM0
4
0
3
2
1
0
ROM3 ROM2 ROM1 ROM0
Address
R/W
On Reset
R/W
CFH
FFF0H
Selection of Internal
ROM3 ROM2 ROM1 ROM0
ROM Capacity
0
1
0
0
16K bytes
0
1
1
0
24K bytes
1
0
0
0
32K bytes
1
0
1
0
40K bytes
1
1
1
1
60K bytes
Other than above
Setting prohibited
Selection of Internal
RAM2 RAM1 RAM0
High-Speed RAM Capacity
0
1
0
512 bytes
1
1
0
1024 bytes
Other than above
Setting prohibited
Table 3-1 shows the setting values of IMS which makes the memory mapping the same as that of the various mask
ROM model.
Table 3-1. Memory Size Switching Register Setting Values
Target Mask ROM Product
IMS Setting Value
µPD78042F
44H
µPD78043F
46H
µPD78044F
C8H
µPD78045F
CAH
19
µPD78P048A
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
By using this register, the internal expansion RAM of the µPD78P048A can be mapped in the same manner as
a mask ROM model.
IXS is set by an 8-bit memory manipulation instruction.
The contents of this register are set to 0AH at RESET.
Figure 4-1. Format of Internal Expansion RAM Size Switching Register
Symbol
7
6
5
4
IXS
0
0
0
0
3
2
1
0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Address
On reset
R/W
FFF4H
0AH
W
Selects internal expansion
IXRAM3 IXRAM2 IXRAM1 IXRAM0 RAM capacity
1
0
1
0
1024 bytes
1
1
0
0
No internal expansion RAM
Other than above
Setting prohibited
Table 4-1 shows the value settings of IXS to map the internal expansion RAM of the µPD78P048A in the same
manner as the respective mask ROM models.
Table 4-1. Memory Size Switching Register Setting Values
Mask ROM Model
µPD78042F
µPD78043F
µPD78044F
µPD78045F
20
IXS Value Setting
0CH
µPD78P048A
5. PROM PROGRAMMING
The µPD78P048A has an on-chip 60K-byte PROM as a program memory. For programming, set the PROM
programming mode by the VPP and RESET pins. For connecting unused pins, refer to PIN CONFIGURATION (2)
PROM programming mode.
Caution Program writing should be performed in the address range 0000H to EFFFH (the last address,
EFFFH, should be specified). Writing cannot be performed with a PROM programmer that cannot
specify the write addresses.
5.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and a low level signal is applied to the RESET pin, the PROM
programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE and
PGM pins are set as shown.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 5-1. Operating Modes of PROM Programming
Pin
RESET
VPP
VDD
CE
OE
PGM
D0 to D7
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High-impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High-impedance
×
L
L
L
L
H
Data output
Output disable
L
H
×
High-impedance
Standby
H
×
×
High-impedance
Operating Mode
Page data latch
Read
+5 V
+5 V
× : L or H
21
µPD78P048A
(1) Read mode
Read mode is set if CE = L, OE = L is set.
(2) Output disable mode
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P048As are
connected to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode.
In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed
by applying a 0.1 ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification
can be performed, if CE = L, OE = L are set.
If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations
should be executed repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1 ms program pulse (active low) is applied to the PGM pin with CE = L, OE
= H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations
should be executed repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, OE = L are set.
In this mode, check if a write operation is performed correctly, after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, VPP pin and D0 to D7 pins of multiple µPD78P048As are
connected in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At
this time, a write is not performed to a device which has the PGM pin driven high.
22
µPD78P048A
5.2 PROM Write Procedure
Figure 5-1. Page Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
Latch
Address = address + 1
Latch
Address = address + 1
Latch
Address = address + 1
Address = address + 1
Latch
No
X=X+1
X = 10 ?
0.1 ms program pulse
Verify 4 bytes
Yes
Fail
Pass
No
Address = N ?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All Pass
Write end
Faulty product
G = Start address
N = Program last address
23
µPD78P048A
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
A2 – A16
A0, A1
D0 – D7
Data Input
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
24
Data Output
µPD78P048A
Figure 5-3. Byte Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1
No
X = 10 ?
0.1 ms program pulse
Yes
Address = address + 1
Fail
Verify
Pass
No
Address = N ?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All Pass
Write end
Faulty product
G = Start address
N = Program last address
25
µPD78P048A
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
A0 – A16
D0 – D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1. VDD should be applied before VPP and cut after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being
applied to VPP.
26
µPD78P048A
5.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown
below.
(1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in PIN
CONFIGURATION (2) PROM programming mode.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input address of read data into the A0 to A16 pins.
(4) Read mode
(5) Output data to D0 to D7 pins.
The timings of the above steps (2) to (5) are shown in Figure 5-5.
Figure 5-5. PROM Read Timings
Address Input
A0 – A16
CE (Input)
OE (Input)
D0 – D7
Hi-Z
Data Output
Hi-Z
27
µPD78P048A
6. ERASURE METHOD (µPD78P048AKL-S ONLY)
The µPD78P048AKL-S is capable of erasing (FFH) the contents of data written in a program memory and rewriting.
When erasing the contents of data, irradiate light having a wavelength of less than about 400 nm to the erasing
window. Normally, irradiate ultraviolet rays of 254 nm wavelength. Volume of irradiation required to completely erase
the contents of data is as follows:
• UV intensity × erasing time: 30 W•s/cm2 or more
• Erasing time: 40 minutes (MIN.) (When a UV lamp of 12,000 µW/cm2 is used. However, a longer time may
be needed because of deterioration in performance of the UV lamp, contamination of the erasing
window, etc.)
When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasing window. Further, if a filter
is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
7. ERASURE WINDOW SEAL (µPD78P048AKL-S ONLY)
To protect from miserasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal
circuit other than EPROM from misoperating by rays, stick a protection seal on the erasure window when EPROM
contents erasure is not performed.
8. ONE-TIME PROM PRODUCTS SCREENING
The one-time PROM product (µPD78P048AGF-3B9) can not be tested completely by NEC before it is shipped,
because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and
performing high-temperature storage under the condition below.
28
Storage Temperature
Storage Time
125 °C
24 hours
µPD78P048A
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Supply voltage
Symbol
Conditions
Rating
Unit
VDD
–0.3 to +7.0
V
VLOAD
VDD –40 to VDD +0.3
V
VPP
–0.3 to 13.5
V
AVDD
–0.3 to VDD +0.3
V
AVREF
–0.3 to VDD +0.3
V
AVSS
–0.3 to +0.3
V
–0.3 to VDD +0.3
V
VI1
P00 to P04, P10 to P17, P20 to P27, P30 to P37, X1, X2,
XT2, RESET
VI2
P70-P74
N-ch open drain
–0.3 to +16
V
VI3
P110 to P117, P120 to P127
P-ch open drain
VDD –40 to VDD +0.3
V
VO1
P01 to P03, P10 to P17, P20 to P27, P30 to P37
–0.3 to VDD +0.3
V
VO2
P70 to P74
–0.3 to +16
V
VOD
P80, P81, P90 to P97, P100 to P107, P110 to P117, P120 to P127
VDD –40 to VDD +0.3
V
Analog input voltage
VAN
ANI0 to ANI7
AVSS –0.3 to AVREF0 +0.3
V
High-level
IOH
1 pin of P01 to P03, P10 to P17, P20 to P27, P30 to P37
–10
mA
Total for P01 to P03, P10 to P17, P0 to P27, P30 to P37
–30
mA
1 pin of P80, P81, P90 to P97, P100 to P107, P110 to P117, P120 to P127
–30
mA
Total for P80, P81, P90 to P97, P100 to P107, P110 to P117, P120 to P127
–120
mA
Input voltage
Output voltage
output current
IOL Note 1
Low-level
output current
1 pin of P01 to P03, P10 to P17, P20 to
Peak value
30
mA
P27, P30 to P37, P70 to P74
rms
15
mA
Total for P01 to P03, P10 to P17,
Peak value
50
mA
P20 to P27, P30 to P37
rms
20
mA
Total for P56, P57, P60 to P63
Peak value
100
mA
rms
60
mA
Peak value
100
mA
rms
60
mA
TA = –40 to +60 °C
800
mW
TA = +85 °C
600
mW
Total for P70 to P74
Total power
PT Note 2
dissipation
Analog input pins
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,
or even momentarily. In other words, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics.
Notes 1. The rms should be calculated as follows: [rms value] = [Peak value] × √Duty
29
µPD78P048A
Total power dissipation PT [mW]
Notes 2. Total power dissipation differs depending on the temperature (refer to the following figure).
800
600
400
200
–40
0
+40
+80
Temperature [˚C]
How to calculate total power dissipation
The following three power dissipation are available for the µPD78P048A. The sum of the three power dissipation
should be less than the total power dissipation PT (80 % or less of ratings is recommended).
<1> CPU power dissipation: calculate VDD (MAX.) × IDD (MAX.).
<2> Output pin power dissipation: Power dissipation when maximum current flows into display output pin.
<3> Pull-down resistor power dissipation: Power dissipation by pull-down resistor incorporated in display output
pin by mask option.
The following is how to calculate total power dissipation for the example in Figure 9-1.
Example Assume the following conditions:
VDD = 5 V ± 10 %, 5.0 MHz oscillator
Supply current (IDD) = 21.6 mA
Display output: 11 grids × 10 segments (Cut width = 1/16)
Maximum current at the grid pin is 15 mA.
Maximum current at the segment pin is 3 mA.
At the key scan timing, display output pin is OFF.
Display output voltage: grid
VOD = VDD – 2 V (voltage drop of 2 V)
segments VOD = VDD – 0.4 V (voltage drop of 0.4 V)
Fluorescent display control voltage (VLOAD) = –30 V
Mask option pull-down resistor = 25 kΩ
By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out.
<1> CPU power dissipation: 5.5 V × 21.6 mA = 118.8 mW
30
µPD78P048A
<2> Output pin power dissipation:
(VDD – VOD) ×
Total current value of each grid
× Digit width (1 – Cut width)
The number of grids + 1
15 mA × 11 Grids
1
=2V×
× (1 –
) = 25.8 mW
11 Grids + 1
16
Total segment current value of illuminated dots
Segment (VDD – VOD) ×
The number of grids +1
3 mA × 31 Dots
= 0.4 V ×
= 3.1 mW
11 Grids + 1
Grid
<3> Pull-down resistor power dissipation:
The number of grids
(VOD – VLOAD)2
×
× Digit width
Pull-down resistor value
The number of grids + 1
Grid
=
Segment
=
11 Grids
1
(5.5 V – 2 V – (–30 V))2
×
× (1 –
) = 38.6 mW
25 kΩ
11 Grids + 1
16
(VOD – VLOAD)2
Pull-down resistor value
(5.5 V – 0.4 V – (–30 V))2
25 kΩ
×
The number of illuminated dots
The number of grids + 1
31 dots
×
= 127.3 mW
11 Grids + 1
Total power dissipation = <1> + <2> + <3> = 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mW
In this example, the total power dissipation do not exceed the rating of the total power dissipation shown
in the figure above, so there is no problem in power dissipation.
However, when the total power dissipation exceeds the rating of the total power dissipation, it is necessary
to lower the power dissipation. To reduce power dissipation, reduce the number of pull-down resistor.
31
32
Figure 9-1. Display Example of 10 Segments-11 Digits
Display Data Memory
FA7AH FA79H
FA6AH FA69H
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
a b
c
d
e
f
g
h
i
FA78H FA77H FA76H
FA68H FA67H FA66H
FA75H FA74H FA73H
FA65H FA64H FA63H
FA72H FA71H FA70H
FA62H FA61H FA60H
0
0
0
0
0
1
0
0
1
0
0
Bit 7
0
1
1
0
1
0
0
1
1
0
0
Bit 6
0
1
1
0
1
1
0
1
1
0
1
Bit 5
0
0
0
0
0
1
0
0
1
1
0
Bit 4
0
0
0
0
0
0
0
0
0
1
1
Bit 3
0
0
0
0
1
1
0
0
0
0
1
Bit 2
0
0
0
0
1
1
0
0
1
1
1
Bit 1
0
0
0
0
0
0
1
0
0
0
0
Bit 0
1
0
1
0
0
0
0
0
0
0
0
Bit 7
0
0
0
1
0
0
0
0
0
0
0
Bit 6
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
SUN
MON
TUE
WED
THU
FRI
SAT
4
5
6
7
FA7 × H
FA6 × H
j
i
AMi
PMj
0
a
f g b
j·
j·
1
2
3
e d c
8
9
10 h
µPD78P048A
µPD78P048A
Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Resonator
Ceramic resonator
Recommended Circuit
VSS X1 X2
R1
C1
Crystal resonator
VSS X1
C2
X2
C1
C2
Parameter
Conditions
Oscillator frequency
(fX)Note 1
MIN. TYP. MAX. Unit
1
Oscillator stabilization
timeNote 2
Oscillator frequency
(fX)Note 1
Oscillator stabilization
timeNote 2
1
VDD = 4.5 to 6.0 V
4.19
5
MHz
4
ms
5
MHz
10
ms
30
External clock
X1
X2
µ PD74HCU04
X1 input frequency
(fX)Note 1
1
5
MHz
X1 input high-/low-level
width (tXH/tXL)
85
500
ns
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times.
2. This is the time required for oscillation to stabilize after addition of VDD, or STOP mode release.
Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring
in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance,
etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS.
• Do not connect to a ground pattern carrying a high current.
• A signal should not be taken from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
33
µPD78P048A
Subsystem Clock Osillator Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Resonator
Recommended Circuit
Crystal resonator
XT1
XT2 VSS
Parameter
Conditions
MIN. TYP. MAX. Unit
Oscillator frequency
(fXT)Note1
32
32.768
35
kHz
1.2
2
s
R2
C3
C4
Oscillator stabilization
timeNote2
VDD = 4.5 to 6.0 V
10
External clock
XT1
XT2
XT1 input frequency
(fXT)Note1
32
100
kHz
XT1 input high-/low-level
width (tXTH/tXTL)
5
15
µs
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times.
2. This is the time required for oscillation to stabilize after power (VDD) is turned on.
Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring
in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance,
etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS.
• Do not connect to a ground pattern carrying a high current.
• A signal should not be taken from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption
current, and is more prone to misoperation due to noise than the main system clock oscillator.
Particular care is therefore required with the wiring method when the subsystem clock is used.
34
µPD78P048A
Recommended Oscillator Constant
Main system clock: ceramic resonator (TA = –40 to +85 °C)
Manufacturer
Product Name
Frequency
(MHz)
Murata Mfg. Co., Ltd.
Circuit Constant
Oscillator Voltage Range
Remark
C1 (pF) C2 (pF) R1 (kΩ) MIN. (V) MAX. (V)
CSB1000J
1.00
CSA2.00MG
2.00
CST2.00MG
2.00
—
—
CSA×.××MG
3.00 to 5.00
30
30
CST×.××MGW
3.00 to 5.00
—
—
Matsushita Electronics
EFOGC2004A4
2.00
Components Co., Lltd.
EFOEC3004A4
3.00
Built-in capacitor
EFOEC4004A4
4.00
Built-in capacitor
EFOEC4194A4
4.19
Built-in capacitor
EFOGC5004A4
5.00
Built-in capacitor
FCR2.0MC3
2.00
Built-in capacitor
FCR4.0MC5
4.00
Built-in capacitor
OCR4.0MC3Note
4.00
Built-in capacitor
CCR5.0MC5Note
5.00
Built-in capacitor
TDK Corp.
100
100
5.6
2.8
—
2.9
6.0
Built-in capacitor
2.8
Built-in capacitor
2.7
Built-in capacitor
Note Surface-mount type
Remark ×.×× indicates frequencies.
Subsystem clock: crystal resonator (TA = –40 to +85 °C)
Manufacturer
Product Name
Frequency
(kHz)
Kyocera Corp.
KF-38GNote
32.768
Circuit Constant
Oscillator Voltage Range
C3 (pF) C4 (pF) R2 (kΩ) MIN. (V) MAX. (V)
15
22
220
2.7
6.0
(Load capacitance 12 pF)
Note Maintained product.
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application
circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency
in the application circuit. For this, it is necessary to directly contact the manufacturer of the
resonator that being used.
35
µPD78P048A
Capacitance (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz Unmeasured pins returned to 0 V
15
pF
Output
capacitance
COUT
f = 1 MHz Unmeasured pins returned to 0 V
35
pF
Input/output
capacitance
CIO
f = 1 MHz
Unmeasured pins returned to 0 V
P01 to P03, P10 to P17,
P20 to P27, P30 to P37
15
pF
P70 to P74
20
pF
P110 to P117,
P120 to P127
35
pF
Remark Unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of the
port pin.
Operating power supply voltage (TA = –40 to +85 °C)
Parameter
MAX.
Unit
2.7Note 2
6.0
V
Display controller
4.5
6.0
V
PWM mode of 16-bit
time/event counter (TM0)
4.5
6.0
V
A/D converter
4.0
6.0
V
Other hardware
2.7
6.0
V
CPUNote 1
Conditions
MIN.
TYP.
Notes 1. Except for system clock oscillator, display controller/driver, and PWM.
2. Operating power supply voltage differs depending on the cycle time. Refer to AC Characteristics.
36
µPD78P048A
DC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
High-level
input voltage
Symbol
Conditions
MAX.
Unit
0.7 VDD
VDD
V
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0.8 VDD
VDD
V
P70 to P74
0.7 VDD
15
V
VDD – 0.5
VDD
V
VDD – 0.5
VDD
V
VDD – 0.3
VDD
V
0.65 VDD
VDD
V
0.7 VDD
VDD
V
VIH1
P21, P23
VIH2
VIH3
VIH4
X1, X2
VIH5
XT1/P04, XT2
VDD = 4.5 to 6.0 V
VIH6
P10 to P17, P30 to P32,
VDD = 4.5 to 6.0 V
N-ch open-drain
P35 to P37
VIH7
Low-level
input voltage
High-level
output voltage
Low-level
output voltage
High-level
input leakage
current
P110 to P117, P120 to P127
VDD = 4.5 to 6.0 V
MIN.
TYP.
0.7 VDD
VDD
V
VDD – 0.5
VDD
V
VIL1
P21, P23
0
0.3 VDD
V
VIL2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0
0.2 VDD
V
VIL3
P70 to P74
VDD = 4.5 to 6.0 V
VIL4
X1, X2
VIL5
XT1/P04, XT2
VIL6
P10 to P17, P30 to P32, P35 to P37 VDD = 4.5 to 6.0 V
VIL7
VOH
VOL1
VDD = 4.5 to 6.0 V
V
V
0
0.4
V
0
0.4
V
0.3
V
0
0.3 VDD
V
P110 to P117, P120 to P127
VDD – 3.5
0.3 VDD
V
P01 to P03, P10 to P17, P20 to VDD = 4.5 to 6.0 V,
P27, P30 to P37, P80, P81, P90 IOH = –1 mA
to P97, P100 to P107, P110 to IOH = –100 µA
P117, P120 to P127
VDD – 1.0
V
VDD – 0.5
V
VDD = 4.5 to 6.0 V
IOL = 15 mA
P01 to P03, P10 to P17,
P20 to P27
VDD = 4.5 to 6.0 V
IOL = 1.6 mA
VOL2
SB0, SB1, SCK0
VDD = 4.5 to 6.0 V
With open-drain and
pull-up (R = 1 kΩ)
VOL3
P01 to P03, P10 to P17, P20 to IOL = 400 µA
P27, P30 to P37, P70 to P74
ILIH1
VIN = VDD
ILIH2
ILIH4
0.3 VDD
0.2 VDD
0
P30 to P37, P70 to P74
ILIH3
0
0
VIN = 15 V
P110 to P117, P120 to P127
VIN = VDD
2.0
V
0.4
V
0.2 VDD
V
0.5
V
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
RESET
3
µA
X1, X2, XT1/P04, XT2
20
µA
P70 to P74
20
µA
3Note 1
µA
3Note 2
µA
VDD = 4.5 to 6.0 V
0.4
Notes 1. For P110 to P117 and P120 to P127, a high-level input leak current of 150 µA (MAX.) flows only during
the 1.5 clocks after an instruction has been executed to read out ports 11, 12 (P11, 12) or port mode
registers 11, 12 (PM11, 12). Outside the period of 1.5 clocks following executing a read-out instruction,
the current is 3 µA (MAX.).
2. For P110 to P117 and P120 to P127, a high-level input leak current of 90 µA (MAX.) flows only during the
1.5 clocks after an instruction has been executed to read out P11, P12, PM11, and PM12. Outside the
period of 1.5 clocks following executing a read-out instruction, the current is 3 µA (MAX.).
Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
37
µPD78P048A
DC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Low-level input
leakage current
Symbol
ILIL1
Conditions
VIN = 0 V
ILIL2
High-level output
leakage current
MAX.
Unit
P00 to P03, P10 to P17, P20
to P27, P30 to P37, RESET
MIN.
TYP.
–3
µA
X1, X2, XT1/P04 XT2
–20
µA
–3Note 4
µA
ILIL3
P70 to P74
ILIL4
P110 to P117, P120 to P127
–10
µA
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P80, P81, P90 to P97,
P100 to P107, P110 to P117,
P120 to P127
3
µA
ILOH1
VOUT = VDD
ILOH2
VOUT = 15 V
P70 to P74
20
µA
ILOL1
VOUT = 0 V
P01 to P03, P10 to P17,
P10 to P27, P30 to P37,
P70 to P74
–3
µA
ILOL2
VOUT = VLOAD = VDD – 35 V
P80, P81, P90 to P97,
P100 to 107, P110 to P117,
P120 to P127
–10
µA
Display output
current
IOD
VDD = 4.5 to 6.0 V, VOD = VDD – 2 V
–15
–25
Software
R1
VIN = 0 V,
15
40
Low-level output
leakage current
90
kΩ
500
kΩ
70
135
kΩ
9.5
28.5
mA
9.75Note 5
29Note 5
mA
VDD = 3.0 V ± 10 %Note 3
0.9
2.7
mA
VDD = 5.0 V ± 10 %
2.5
7.5
mA
VDD = 3.0 V ± 10 %
1.0
3.0
mA
32.768 kHz crystal oscillation VDD = 5.0 V ± 10 %
operation mode
VDD = 3.0 V ± 10 %
90
180
µA
55
110
µA
IDD4
32.768 kHz crystal oscillation VDD = 5.0 V ± 10 %
HALT mode
VDD = 3.0 V ± 10 %
25
50
µA
5
10
µA
IDD5
XT1 = 0 V STOP mode when VDD = 5.0 V ± 10 %
connecting to feedback resistor VDD = 3.0 V ± 10 %
1
20
µA
0.5
10
µA
XT1 = 0 V STOP mode when not VDD = 5.0 V ± 10 %
connecting to feedback resistor VDD = 3.0 V ± 10 %
0.1
20
µA
0.05
10
µA
pull-up resistor
VDD = 4.5 to 6.0 V
mA
P01 to P03, P10 to P17,
20
P20 to P27, P30 to P37
On-chip
pull-down resistor
R2
P80, P81, P90 to P97,
P100 to P105
VOD – VLOAD = 35 V
Power supply
currentNote 1
IDD1
5.0 MHz crystal oscillation
operation mode
VDD = 5.0 V ± 10 %Note 2
IDD2
IDD3
IDD6
5.0 MHz crystal oscillation
HALT mode
25
Notes 1. This current excludes the AVREF current, port current, and current which flows in the built-in pull-down
resistor.
2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)
3. When operating at low-speed mode (when the PCC is set to 04H)
4. For P70 to P74, a low-level input leak current of –150 µA (MAX.) flows only during the 1.5 clocks after an
instruction has been executed to read out port 7 (P7) or port mode register 7 (PM7). Outside the period
of 1.5 clocks following executing a read-out instruction, the current is –3 µA (MAX.).
5. This current includes the AVDD current by the A/D converter operation.
Remark Unless otherwise specified, the characteritics of a shared pin are the same as those of a port pin.
38
µPD78P048A
AC Characteristics
(1) Basic operation (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Cycle time (minimum)
instruction execution
time)
Symbol
TCY
Conditions
Operated with main system
MIN.
VDD = 4.5 to 6.0 V
clock
TI1, 2 input
frequency
fTI
TI1, 2 input high,
low-level width
fTIH
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
fINTH
INTP0
fINTL
INTP1 to INTP3
RESET low-level width
tRSL
Unit
0.4
32
µs
0.8
32
µs
125
µs
0
2
MHz
0
138
kHz
122
250
ns
3.6
µs
8/fsamNote 2
µs
10
µs
10
µs
fTIL
Interrupt input high,
low-level width
MAX.
40Note 1
Operated with subsystem clock
TYP.
Notes 1. Value when external clock input is used as subsystem clock. When crystal is used, the value becomes
114 µs.
2. Selection of fsam = fx/2N+1, fx/64, fx/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of sampling
clock select register (SCS).
TCY vs VDD (with main system clock operated)
60
30
Operation guarantee
range
Cycle time TCY [µs]
10
2.0
1.0
0.5
0.4
0
1
2
3
4
5
6
Power supply voltage VDD [V]
39
µPD78P048A
(2) Serial interface (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(a) Serial interface channel 0
(i)
3-wire serial I/O mode (SCK0: Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY1
tKH1
Conditions
MIN.
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY1/2 – 50
ns
SCK0 high, low-level
width
tKL1
tKCY1/2 – 150
ns
SI0 setup time to SCK0↑
tSIK1
100
ns
400
ns
SI0 hold time from SCK0↑ tKSI1
SCK0↓→ SO0
output delay time
tKSO1
C = 100
pFNote
VDD = 4.5 to 6.0 V
300
ns
1000
ns
MAX.
Unit
Note C is a load capacitance of the SCK0 or SO0 output line.
(ii) 3-wire serial I/O mode (SCK0: External clock input)
Parameter
SCK0 cycle time
Symbol
MIN.
ns
3200
ns
400
ns
tKL2
1600
ns
tSIK2
100
ns
SI0 hold time from SCK0↑ tKSI2
400
ns
SI0 setup time to SCK0↑
tKH2
SCK0↓→ SO0
output delay time
tKSO2
SCK0 rise, fall time
tR2
tF2
VDD = 4.5 to 6.0 V
TYP.
800
SCK0 high, low-level
width
tKCY2
Conditions
VDD = 4.5 to 6.0 V
C = 100 pFNote
Note C is a load capacitance of the SO0 output line.
40
VDD = 4.5 to 6.0 V
300
ns
1000
ns
160
ns
µPD78P048A
(iii) SBI mode (SCK0: Internal clock output)
Parameter
SCK0 cycle time
SCK0 high, low-level
width
Symbol
tKCY3
tKH3
Conditions
MIN.
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKL3
VDD = 4.5 to 6.0 V
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY3/2 – 50
ns
tKCY3/2 – 150
ns
100
ns
300
ns
tKCY3/2
ns
SB0, SB1 setup time
to SCK↑
tSIK3
SB0, SB1 hold time
from SCK0↑
tKSI3
SCK0↓→ SB0, SB1
output delay time
tKSO3
SCK0↑→SB0, SB1↓
tKSB
tKCY3
ns
SB0, SB1↓→SCK0↓
tSBK
tKCY3
ns
SB0, SB1 high-level
width
tSBH
tKCY3
ns
SB0, SB1 low-level
tSBL
tKCY3
ns
R = 1 kΩ, C = 100 pFNote
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
width
Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance.
(iv) SBI mode (SCK0: External clock input)
Parameter
SCK0 cycle time
SCK0 high, low-level
width
Symbol
tKCY4
tKH4
Conditions
MIN.
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKL4
VDD = 4.5 to 6.0 V
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
tKCY4/2
ns
SB0, SB1 setup time
to SCK0↑
tSIK4
SB0, SB1 hold time
from SCK0↑
tKSI4
SCK0↓→ SB0, SB1
output delay time
tKSO4
SCK0↑→SB0, SB1↓
tKSB
tKCY4
ns
SB0, SB1↓→SCK0↓
tSBK
tKCY4
ns
SB0, SB1 high-level
width
tSBH
tKCY4
ns
SB0, SB1 low-level
width
tSBL
tKCY4
ns
SCK0 rise, fall time
tR4
tF4
R = 1 kΩ, C = 100 pFNote
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
160
ns
Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance.
41
µPD78P048A
(v) 2-wire serial I/O mode (SCK0: Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
Conditions
R = 1 kΩ, C = 100
pFNote
MIN.
VDD = 4.5 to 6.0 V
TYP.
MAX.
Unit
1600
ns
3800
ns
SCK0 high-level width
tKH5
tCKY5/2 – 160
ns
SCK0 low-level width
tKL5
tCKY5/2 – 50
ns
SB0, SB1 setup time
to SCK0↑
tSIK5
300
ns
SB0, SB1 hold time
from SCK0↑
tKSI5
600
ns
SCK0↓→SB0, SB1
output delay time
tKSO5
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
MAX.
Unit
Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance.
(vi) 2-wire serial I/O mode (SCK0: External clock input)
Parameter
SCK0 cycle time
Symbol
tKCY6
Conditions
R = 1 kΩ, C = 100 pFNote
MIN.
VDD = 4.5 to 6.0 V
TYP.
1600
ns
3800
ns
SCK0 high-level width
tKH6
650
ns
SCK0 low-level width
tKL6
800
ns
SB0, SB1 setup time
to SCK0↑
tSIK6
100
ns
SB0, SB1 hold time
from SCK0↑
tKSI6
tKCY6/2
ns
SCK0↓→SB0, SB1
output delay time
tKSO6
SCK0 rise,
fall time
tR6
tF6
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
160
ns
Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance.
42
µPD78P048A
(b) Serial interface channel 1
(i)
3-wire serial I/O mode (SCK1: Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY7
MIN.
VDD = 4.5 to 6.0 V
MAX.
Unit
800
ns
3200
ns
tKCY7/2 – 50
ns
tKL7
tKCY7/2 – 100
ns
SI1 setup time to SCK1↑
tSIK7
100
ns
SI1 hold time from SCK1↑
tKSI7
400
ns
tKSO7
VDD = 4.5 to 6.0 V
TYP.
SCK1 high, low-level
width
SCK1↓→ SO1
output delay time
tKH7
Conditions
C = 100
pFNote
VDD = 4.5 to 6.0 V
300
ns
1000
ns
MAX.
Unit
Note C is a load capacitance of the SCK1 or SO1 output line.
(ii) 3-wire serial I/O mode (SCK1: External clock input)
Parameter
SCK1 cycle time
SCK1 high, low-level
width
SI1 setup time to SCK1↑
Symbol
tKCY8
Conditions
MIN.
800
ns
3200
ns
400
ns
tKL8
1600
ns
tSIK8
100
ns
400
ns
tKH8
VDD = 4.5 to 6.0 V
TYP.
VDD = 4.5 to 6.0 V
SI1 hold time from SCK1↑ tKSI8
SCK1↓→ SO1
output delay time
tKSO8
SCK1 rise, fall time
tR8
tF8
C = 100
pFNote
VDD = 4.5 to 6.0 V
300
ns
1000
ns
160
ns
Note C is a load capacitance of the SO1 output line.
43
µPD78P048A
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1: Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY9
tKH9
Conditions
MIN.
VDD = 4.5 to 6.0 V
MAX.
Unit
800
ns
3200
ns
tKCY9/2 – 50
ns
SCK1 high, low-level
width
tKL9
tKCY9/2 – 150
ns
SI1 setup time (to SCK1↑)
tSIK9
100
ns
SI1 hold time (from SCK1↑)
tKSI9
400
ns
SO1 output delay time
from SCK1↓
tKSO9
STB↑ from SCK1↓
tSBD
Strobe signal
high-level width
VDD = 4.5 to 6.0 V
TYP.
R = 1 kΩ, C = 100
pFNote
VDD = 4.5 to 6.0 V
300
ns
1000
ns
tKCY9/2 – 100
tKCY9/2 + 100
ns
tSBW
tKCY9 – 30
tKCY9 + 30
ns
B signal setup time
(to busy signal
detection timing)
tBYS
100
ns
Busy signal hold time
(from busy signal
detection timing
tBYH
100
ns
SCK1↓ from busy
tSPS
2tKCY9
ns
inactibe
Note R is a load resistance of the SCK1 or SO1 output line, and C is its load capacitance.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1: External clock input)
Parameter
SCK1 cycle time
Symbol
tKCY10
tKH10
Conditions
MIN.
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
SCK1 high, low-level
width
tKL10
1600
ns
SI1 setup time (to SCK1↑)
tSIK10
100
ns
SI1 hold time (from SCK1↑)
tKSI10
400
ns
SO1 output delay time
from SCK1↓
tKSO10
SCK1 rise, fall time
tR10
tF10
C = 100 pFNote
Note C is a load capacitance of the SO1 output line.
44
VDD = 4.5 to 6.0 V
300
ns
1000
ns
160
ns
µPD78P048A
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 Input
TI timing
1/fTI
tTIL
tTIH
TI1, TI2
45
µPD78P048A
Serial Transfer Timing
3-wire serial I/O mode:
IDD vs VDD (fx = 5.0 MHz, fxx = MHz
tKCY1, 2, 7, 8
tKL1, 2, 7, 8
tKH1, 2, 7, 8
tR2, 8
tF2, 8
SCK0, SCK1
tSIK1, 2, 7, 8 tKSI1, 2, 7, 8
SI0, SI1
Input Data
tKSO1, 2,
7, 8
SO0, SO1
Output Data
SBI mode (bus release signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tR4
tF4
SCK0
tKSB
tSBL
tSBH
tSBK
tSIK3, 4
SB0, SB1
tKSO3, 4
SBI mode (command signal transfer):
tKL3, 4
tKCY3, 4
tKH3, 4
SCK0
tKSB
tSBK
tSIK3, 4
SB0, SB1
tKSO3, 4
46
tKSI3, 4
tKSI3, 4
µPD78P048A
2-wire serail I/O mode:
tKCY5, 6
tKL5, 6
tR6
tKH5, 6
tF6
SCK0
tSIK5, 6
tKSO5, 6
tKSI5, 6
SB0, SB1
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D2
D1
D2
D0
D1
D7
D0
D7
tKSI9, 10
tSIK9, 10
tKH9, 10
tKSO9, 10
tF10
SCK1
tR10
tKL9, 10
tKCY9, 10
tSBD
tSBW
STB
3-wire serial I/O mode with automatic transmit/receive function (Busy processing):
SCK1
7
8
Note
9
Note
Note
10
tBYS
10+n
tBYH
1
tSPS
BUSY
(Active high)
Note Though it does not become low level actually, heve described as it does due to the timing rule.
47
µPD78P048A
A/D Converter Characteristics (TA = –40 to +85 °C, AVDD = VDD = 4.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
0.8
%
19.1
200
µs
tSAMP
2.86
30
µs
Analog signal input voltage
VIAN
AVSS
AVREF
V
Reference voltage
AVREF
4.0
AVDD
V
AVREF resistor
RAIREF
4
Resolution
Total
errorNote 1
Conversion
Sampling
timeNote 2
timeNote 3
tCONV
1 MHz ≤ fx ≤ 5.0 MHz
14
kΩ
Notes 1. Quantization error (+1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value.
2. Set the A/D conversion time to 19.1 µs or more.
3. Sampling time depends on the conversion time.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Data retention supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
wait time
tWAIT
Conditions
MIN.
TYP.
2.0
VDDDR = 2.0 V
Subsystem clock stopped,
Feedback resistor non-connected
0.1
MAX.
Unit
6.0
V
10
µA
µs
0
Release by RESET
217/fx
ms
Release by interrupt
Note
ms
Note Selection of 212/fx, 214/fx to 217/fx is available by bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time
select register (OSTS).
Data retention timing (STOP mode release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
48
µPD78P048A
Data retention timing (standby release signal: STOP mode release by interrupt signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
tSREL
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
Interrupt input timing
tINTL
tINTH
INTP0 - INTP2
tINTL
INTP3
RESET input timing
tRSL
RESET
49
µPD78P048A
PROM Programming Characteristics
DC characteristics
(1) PROM write mode (TA = 25 ±5 °C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX.
Unit
Input voltage high
VIH
VIH
0.7 VDD
VDD
V
Input voltage low
VIL
VIL
0
0.3 VDD
V
Output voltage high
VOH
VOH
IOH = –1 mA
Output voltage low
VOL
VOL
IOL = 1.6 mA
Input leakage current
ILI
ILI
0 ≤ VIN ≤ VDD
VPP supply voltage
VPP
VPP
12.2
VDD supply voltage
VDD
VCC
6.25
VPP supply current
IPP
IPP
VDD supply current
IDD
ICC
VDD –1.0
V
0.4
V
+10
µA
12.5
12.8
V
6.5
6.75
V
50
mA
50
mA
MAX.
Unit
–10
PGM = VIL
(2) PROM read mode (TA = 25 ±5 °C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
Input voltage high
VIH
VIH
0.7 VDD
VDD
V
Input voltage low
VIL
VIL
0
0.3 VDD
V
Output voltage high
VOH1
VOH1
IOH = –1 mA
VDD –1.0
V
VOH2
VOH2
IOH = –100 µA
VDD –0.5
V
Output voltage low
VOL
VOL
IOL = 1.6 mA
Input leakage current
ILI
ILI
0 ≤ VIN ≤ VDD
Output leakage current
ILO
ILO
0 ≤ VOUT ≤ VDD, OE = VIH
VPP supply voltage
VPP
VPP
VDD –0.6
VDD supply voltage
VDD
VCC
4.5
VPP supply current
IPP
IPP
VDD supply current
IDD
ICCA1
Note Corresponding µPD27C1001A symbol.
50
0.4
V
–10
+10
µA
–10
+10
µA
VDD
VDD +0.6
V
5.0
5.5
V
VPP = VDD
100
µA
CE = VIL, VIN = VIH
50
mA
µPD78P048A
AC characteristics
(1) PROM write mode
(a) Page program mode (TA = 25 ±5 °C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time (to OE↓)
tAS
tAS
2
µs
OE setup time
tOES
tOES
2
µs
CE setup time (to OE↓)
tCES
tCES
2
µs
Input data setup time (to OE↓)
tDS
tDS
2
µs
Address hold time (from OE↑)
tAH
tAH
2
µs
tAHL
tAHL
2
µs
tAHV
tAHV
0
µs
Input data hold time (from OE↑)
tDH
tDH
2
µs
Data output float delay time from OE↑
tDF
tDF
0
VPP setup time (to OE↓)
tVPS
tVPS
1.0
ms
VDD setup time (to OE↓)
tVDS
tVCS
1.0
ms
Program pulse width
tPW
tPW
0.095
Valid data delay time from OE↓
tOE
tOE
OE pulse width during data latching
tLW
tLW
1
µs
PGM setup time
tPGMS
tPGMS
2
µs
CE hold time
tCEH
tCEH
2
µs
OE hold time
tOEH
tOEH
2
µs
250
0.1
ns
0.105
ms
1
µs
(b) Byte program mode (TA = 25 ±5 °C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time (to PGM↓)
tAS
tAS
2
µs
OE setup time
tOES
tOES
2
µs
CE setup time (to PGM↓)
tCES
tCES
2
µs
Input data setup time (to PGM↓)
tDS
tDS
2
µs
Address hold time (from OE↑)
tAHL
tAHL
2
µs
Input data hold time (from PGM↑)
tDH
tDH
2
µs
Data output float delay time from OE↑
tDF
tDF
0
VPP setup time (to PGM↓)
tVPS
tVPS
1.0
ms
VDD setup time (to PGM↓)
tVDS
tVCS
1.0
ms
Program pulse width
tPW
tPW
0.095
Valid data delay time from OE↓
tOE
tOE
OE hold time
tOEH
—
2
250
0.1
ns
0.105
ms
1
µs
µs
Note Corresponding µPD27C1001A symbol
51
µPD78P048A
(2) PROM read mode (TA = 25 ±5 °C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX.
Unit
Data output delay time from address
tACC
tACC
CE = OE = VIL
800
ns
Data output delay time from CE↓
tCE
tCE
OE = VIL
800
ns
Data output delay time from OE↓
tOE
tOE
CE = VIL
200
ns
Data output float delay time from OE↑
tDF
tDF
CE = VIL
0
60
ns
Data hold time from address
tOH
tOH
CE = OE = VIL
0
ns
Note Corresponding µPD27C1001A symbol
(3) PROM programming mode setting (TA = 25 °C, VSS = 0 V)
Parameter
PROM programming mode setup time
52
Symbol
tSMA
Conditions
MIN.
10
TYP.
MAX.
Unit
µs
µPD78P048A
PROM write mode timing (page program mode)
Page Data Latch
Program Verify
Page Program
A2 – A16
tAS
tAHL
tAHV
tDS
tDH
tDF
A0, A1
D0 – D7
Hi-Z
Hi-Z
Data Input
tVPS
Hi-Z
tPGMS
Data
tOE Output
VPP
tAH
VPP
VDD
tVDS
VDD + 1.5
VDD
VDD
tCES
tOEH
VIH
CE
VIL
tCEH
tPW
VIH
PGM
VIL
tLW
tOES
VIH
OE
VIL
53
µPD78P048A
PROM write mode timing (byte program mode)
Program
Program Verify
A0 – A16
tAS
D0 – D7
tDF
Hi-Z
Hi-Z
Data Input
tDS
Hi-Z
Data Output
tDH
tAH
VPP
VPP
VDD
tVPS
VDD + 1.5
VDD
VDD
tVDS
tOEH
VIH
CE
VIL
tCES
tPW
VIH
PGM
VIL
tOES
tOE
VIH
CE
VIL
Cautions 1. VDD shonld be applied before VPP, and cut after VPP.
2. VPP shonld not exceed +13.5 V including overshoot.
3. Disconnection during application of ±12.5 V to VPP may have an adverse effect on reliability.
PROM read mode timing
A0 – A16
Effective Address
VIH
CE
VIL
tCE
VIH
CE
tDF Note 2
VIL
tACC
D0 – D7
Note 1
Hi-Z
tOE
Note 1
tOH
Data Output
Hi-Z
Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE a maximum of
tACC – tOE.
2. tDF is the time from when either OE or CE first reaches VIH.
54
µPD78P048A
PROM programming mode setting timing
VDD
VDD
0
RESET
VDD
VPP
0
tSMA
A0 - A16
Effective Address
55
µPD78P048A
10. CHARACTERISTIC CURVE (REFERENCE VALUE)
IDD vs. VDD (Main system clock : 5.0 MHz)
(TA = 25 °C)
100.0
50.0
PCC = 00H
10.0
PCC = 01H
5.0
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillates,
XT1 oscillates)
Supply Current IDD [mA]
1.0
0.5
PCC = B0H
0.1
0.05
HALT (X1 stops, XT1 oscillates)
STOP (X1 stops, XT1 oscillates)
0.01
0.005
0.001
0
2
3
4
5
Supply voltage VDD [V]
56
6
7
8
µPD78P048A
IDD vs. fx
(VDD = 3 V, TA = 25 °C)
6
PCC = 00H
Supply Current IDD [mA]
5
4
3
PCC = 01H
2
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT
(X1 oscillates)
1
0
0
1
2
3
4
5
6
Clock oscillation frequency fX [MHz]
IDD vs. fX
(VDD = 5 V, TA = 25 °C)
9
PCC = 00H
8
7
Supply current IDD [mA]
6
PCC = 01H
5
4
PCC = 02H
3
PCC = 03H
2
PCC = 04H
PCC = 30H
HALT
(X1 oscillates)
1
0
0
1
2
3
4
5
6
Clock oscillation frequency fX[MHz]
57
µPD78P048A
IOL vs. VOL (Port 1)
(TA = 25 °C)
VDD = 5 V
VDD = 4 V
30
Low-level output current IOL [mA]
VDD = 6 V
VDD = 3 V
20
10
0
0
0.5
1.0
1.5
Low-level output voltage VOL [V]
IOL vs. VOL (Ports 0, 2, 3)
(TA = 25 °C)
VDD = 5 V
30
VDD = 4 V
Low-level output current IOL [mA]
VDD = 6 V
VDD = 3 V
20
10
0
0
0.5
1.0
Low-level output voltage VOL [V]
58
1.5
µPD78P048A
IOL vs. VOL (Port 7)
(TA = 25 °C)
VDD = 5 V
30
Low-level output current IOL [mA]
VDD = 6 V
VDD = 4 V
20
VDD = 3 V
10
0
0
0.5
1.0
1.5
Low-level output voltage VOL [V]
IOH vs. VDD–VOH (Port 0-Port 3)
(TA = 25 °C)
VDD = 5 V
High-level output current IOH [mA]
–10
VDD = 4 V
VDD = 6 V
VDD = 3 V
–5
0
0
0.5
1.0
1.5
High-level output voltage VDD–VOH [V]
59
µPD78P048A
IOH vs. VDD–VOH (Port 8-Port 12)
(TA = 25 °C)
VDD = 5 V VDD = 4 V
–30
VDD = 6 V
High-level output current IOH [mA]
VDD = 3 V
–20
–10
0
0
1.0
2.0
High-level output voltage VDD–VOH [V]
60
3.0
µPD78P048A
11. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14 20)
A
B
41
40
64
65
detail of lead end
S
C D
Q
R
25
24
80
1
F
G
J
H
I
M
K
P
M
N
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
L
ITEM
MILLIMETERS
INCHES
A
23.6±0.4
0.929±0.016
B
20.0±0.2
0.795 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
1.0
0.039
G
0.8
0.031
H
0.35±0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
S
5°±5°
5°±5°
3.0 MAX.
0.119 MAX.
P80GF-80-3B9-3
Remark Dimensions and materials of ES products are the same as those of mass-production products.
61
µPD78P048A
80 PIN CERAMIC WQFN
A
Q
K
C
D
B
T
W
S
80
H
U
I
1
M
E
F
G
J
X80KW-80A-1
NOTE
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
20.0 ± 0.4
0.787+0.017
–0.016
B
19.0
0.748
C
13.2
0.520
D
14.2 ± 0.4
0.559 ± 0.016
E
1.64
0.065
F
2.14
0.084
G
4.064 MAX.
0.160 MAX.
H
0.51 ± 0.10
0.020 ± 0.004
I
0.08
0.003
J
0.8 (T.P.)
0.031 (T.P.)
K
1.0 ± 0.2
0.039 –0.008
Q
C 0.5
C 0.020
R
0.8
0.031
S
1.1
0.043
T
R 3.0
R 0.118
U
12.0
0.472
W
0.75 ± 0.2
0.030 –0.009
+0.009
+0.008
Remark Dimensions and materials of ES products are the same as those of mass-production products.
62
R
µPD78P048A
12. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the µPD78P048A.
For details of the recommended soldering conditions, refer to our information document Semiconductor Device
Mounting Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 12-1. Soldering Conditions for Surface-Mount Type
µPD78P048AGF-3B9: 80-pin plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), IR35-00-3
Number of times: Thrice max.
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), VP15-00-3
Number of times: Thrice max.
Wave soldering
Solder bath temperature: 260 °C max. Duration: 10 sec. max.
Number of times: Once
Preliminary heat temperature: 120 °C max. (Package surface temperature)
Partial heating
Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side)
WS60-00-1
—
Caution Using more than one soldering method should be avoided (except in the case of partial heating).
63
µPD78P048A
APPENDIX A. DEVELOPMENT TOOLS
The following tools are available for development of systems using the µPD78P048A:
Language Processing Software
RA78K/0Note 1, 2, 3, 4
Assembler package common to 78K/0 series
CC78K/0Note 1, 2, 3, 4
C compiler package common to 78K/0 series
DF78044Note 1, 2, 3, 4
Device file for µPD78044F subseries
CC78K/0-LNote 1, 2, 3, 4
C compiler library source file common to 78K/0 series
PROM Writing Tools
PG-1500
PROM programmer
PA-78P048GF
PA-78P048KL-S
Programmer adapter connected to PG-1500
PG-1500 ControllerNote 1, 2
Control program for PG-1500
Debugging Tools
IE-78000-R
In-circuit emulator common to 78K/0 series
IE-78000-R-A
In-circuit emulator common to 78K/0 series (for integrated debugger)
IE-78000-R-BK
Break board common to 78K/0 series
IE-78044-R-EM
Emulation board for evaluating µPD78044F subseries
EP-78130GF-R
Emulation probe common to µPD78134
EV-9200G-80
Socket mounted to target system created for 80-pin plastic QFP (GF-3B9 type)
SM78K0Note 5, 6, 7
System simulator common to 78K/0 series
ID78K0Note 4, 5, 6, 7
Integrated debugger for IE-78000-R-A
SD78K/0Note 1, 2
Screen debugger for IE-78000-R
DF78044Note 1, 2, 4, 5, 6, 7
Device file for µPD78044F subseries
Real-time OS
RX78K/0Note 1, 2, 3, 4
Real-time OS for 78K/0 series
MX78K0Note 1, 2, 3, 4
OS for 78K/0 series
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/ATTM and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 series 300TM (HP-UXTM) based
4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (Sun OSTM) based, EWS4800 series (EWS-UX/
V) based
5. PC-9800 series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
64
µPD78P048A
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note 3
Fuzzy knowledge data creation tool
FT9080Note 1/FT9085Note 2
Translator
FI78K0Note 1, 2
Fuzzy inference module
FD78K0Note 1, 2
Fuzzy inference debugger
Notes 1. PC-9800 series (MS-DOS) based
2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based
3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development
tools.
2. RA78K/0, CC78K/0, SM78K0, ID78K0, RX78K/0, and SD78K/0 are used in combination with DF78044.
65
µPD78P048A
DIMENSIONS AND RECOMMENDED MOUNTING PATTERN OF CONVERSION SOCKET
Figure A-1. Dimensions of EV-9200G-80 (Reference)
A
N
O
G
P
R
B
M
L
U
K
D
C
E
T
S
F
EV-9200G-80
1
Q
No.1 pin index
H
I
J
EV-9200G-80-G0E
ITEM
66
MILLIMETERS
INCHES
A
25.0
0.984
B
20.30
0.799
C
4.0
0.157
D
14.45
0.569
E
19.0
0.748
F
4-C 2.8
4-C 0.11
G
0.8
0.031
H
11.0
0.433
I
22.0
0.866
J
24.7
0.972
K
5.0
0.197
L
16.2
0.638
M
18.9
0.744
N
8.0
0.315
O
7.8
0.307
P
2.5
0.098
Q
2.0
0.079
R
1.35
0.053
S
0.35 ± 0.1
0.014+0.004
–0.005
T
φ 2.3
φ 0.091
U
φ 1.5
φ 0.059
µPD78P048A
Figure A-2. Recommended Mounting Pattern of V-9200G-80
G
J
H
I
D
E
F
L
K
M
C
B
A
EV-9200G-80-P1E
ITEM
MILLIMETERS
INCHES
A
25.7
1.012
B
21.0
0.827
C
+0.003
0.8±0.02 × 23=18.4±0.05 0.031+0.002
–0.001 × 0.906=0.724 –0.002
D
+0.003
0.8±0.02 × 15=12.0±0.05 0.031+0.002
–0.001 × 0.591=0.472 –0.002
E
15.2
0.598
F
19.9
0.783
G
11.00 ± 0.08
0.433+0.004
–0.003
H
5.50 ± 0.03
0.217+0.001
–0.002
I
5.00 ± 0.08
0.197+0.003
–0.004
J
2.50 ± 0.03
0.098 +0.002
–0.001
K
0.5 ± 0.02
0.02+0.001
–0.002
L
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
M
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).
67
µPD78P048A
APPENDIX B. RELATED DOCUMENTS
• Device Related Documents
Document Name
Document No.
Japanese
English
µPD78044F Subseries User’s Manual
U10908J
U10908E
µPD78042F, 78043F, 78044F, 78045F Data Sheet
U10700J
U10700E
µPD78P048A Data Sheet
U10611J
This document
µPD78044A, 78044F Subseries Special Function Register Table
U10701J
—
78K/0 Series User’s Manual-Instruction
U12326J
U12326E
78K/0 Series Instruction Set
U10904J
—
78K/0 Series Instruction Table
U10903J
—
78K/0 Series Application Note-Basics (II)
U10121J
U10121E
• Development Tool Related Documents (User’s Manual) (1/2)
Document Name
Document No.
Japanese
RA78K Series Assembler Package
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
EEU-817
EEU-1402
Structured assembly language
U11789J
U11789E
Assembly language
U11801J
U11801E
Operation
U11802J
U11802E
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
Operation
U11517J
U11517E
Language
U11518J
U11518E
U12322J
—
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
CC78K Series C Compiler
CC78K/0 C Compiler
CC78K Series Library Source File
CC78K/0 C Compiler Application Note
English
Programming know-how
EEA-618
EEA-1208
PG-1500 PROM Programmer
U11940J
EEU-1335
PG-1500 Controller PC-9800 Series (MS-DOS) Based
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC DOS) Based
EEU-5008
U10540E
IE-78000-R
U11376J
U11376E
IE-78000-R-A
U10057J
U10057E
IE-78000-R-BK
EEU-867
EEU-1427
IE-78044-R-EM
EEU-833
EEU-1424
EP-78130GF-R
EEU-943
EEU-1470
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External part user open
interface specifications
U10092J
U10092E
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
—
ID78K0 Integrated Debugger PC Based
Reference
U11539J
U11539E
68
µPD78P048A
• Development Tool Related Documents (User’s Manual) (2/2)
Document Name
Document No.
Japanese
English
ID78K0 Integrated Debugger Windows Based
Guide
U11649J
U11649E
SD78K/0 Screen Debugger
Introduction
EEU-852
U10539E
PC-9800 Series (MS-DOS) Based
Reference
U10952J
—
SD78K/0 Screen Debugger
Introduction
EEU-5024
EEU-1414
IBM PC/AT (PC DOS) Based
Reference
U11279J
U11279E
• Embedded Software Related Documents (User’s Manual)
Document Name
Document No.
Japanese
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
English
Fundamental
U11537J
—
Installation
U11536J
—
Fundamental
U12257J
—
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-1438
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System
EEU-862
EEU-1444
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference
Module
EEU-858
EEU-1441
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference
Debugger
EEU-921
EEU-1458
Translator
• Other Related Documents
Document Name
Document No.
Japanese
English
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability and Quality Control
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
Semiconductor Devices Quality Guarantee Guide
C11893J
MEI-1202
Microcomputer-Related Product Guide (Products by Other Manufacturers)
U11416J
—
—
Caution The above related documents are subject to change without notice. For design purpose, etc., be
sure to use the latest documents.
69
µPD78P048A
[MEMO]
70
µPD78P048A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
71
µPD78P048A
The documents referred to in this publication may include preliminary versions. However preliminary versions are not marked as
such.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µPD78P048AKL-S
The customer must judge the need for license: µPD78P048AGF-3B9
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
FIP is a registered trademark of NEC Corporation.
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 series 300, HP9000 series 700 and HP-UX are trademarks of Hewlett Packard Inc.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun MicroSystems Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
72