REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to reflect MIL-H-38534 processing. Correction to table I. Editorial changes throughout. 92-03-05 Alan Barone B Changes in accordance with NOR 5962-R015-96. 95-12-08 Kendall A. Cottongim C Added device types 02 and 03 with cage code 88379. Made changes to table I, figure 1, and figure 20. Renumbered figures 5 through 21 to figures 4 through 20. Changes to reflect MIL-PRF-38534 processing. -sld 02-03-01 Raymond Monnin REV SHEET REV C C C C C C C C C C C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Robert M. Heber STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 CHECKED BY Ray Monnin APPROVED BY Michael Frye http://www.dscc.dla.mil MICROCIRCUIT, HYBRID, LINEAR, MIL-STD1553, BUS TO MICROPROCESSOR INTERFACE UNIT DRAWING APPROVAL DATE 88-12-20 REVISION LEVEL C SIZE A SHEET CAGE CODE 5962-88586 67268 1 OF DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 33 5962-E240-02 1. SCOPE 1.1 Scope. This drawing describes device requirements for class H hybrid microcircuits to processed in accordance with MIL-PRF-38534. 1.2 PIN. The PIN shall be as shown in the following example: 01 Device type (see 1.2.1) 5962-88586 Drawing number X Case outline (see 1.2.2) X Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 02 03 Circuit function BUS-66300II CT2566-001 CT2566-002 MIL-STD-1553, BUS to microprocessor interface unit MIL-STD-1553, BUS to microprocessor interface unit MIL-STD-1553, BUS to microprocessor interface unit 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Descriptive designator See figure 1 See figure 1 Terminals Package style 78 82 Dual-in-line Flat pack 1.2.3 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) ................................................. Input voltage range (VIN) ..................................................... Supply current (ICC) ............................................................. Power dissipation (PD) ........................................................ Storage temperature range................................................. Lead temperature (soldering, 10 seconds) ......................... Thermal resistance, junction-to-case (ΘJC) ......................... -0.5 V dc to +7.0 V dc -0.5 V dc to +7.0 V dc 150 mA 250 mW 2/ -65°C to +150°C +300°C 4.11°C/W 1.4 Recommended operating conditions. Supply voltage range (VCC) ................................................. Minimum logic high input voltage (VIH)................................ Maximum logic low input voltage (VIL)................................. Case operating temperature range (TC).............................. Operating frequency (FOP) .................................................. 1/ 2/ 4.5 V dc to 5.5 V dc 2.0 V dc 0.8 V dc -55°C to +125°C 12.0 MHz Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Applies up to TC = +125°C. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1553 - Aircraft Internal Time Division Command/Response Multiplex Data Bus. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbook are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tests herein or as designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class. Therefore, the tests and inspections herein may not be performed for the applicable device class (see MIL-PRF-38534). Furthermore, the manufacturer may take exceptions or use alternate methods to the tests and inspections herein and not perform them. However, the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 through 20. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 3 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Group A subgroups 1/ Conditions -55°C ≤ TC ≤+125°C unless otherwise specified Device types Limits Min Supply current ICC VCC = 5.5 V, IOH = -0.4 mA, IOL = 4.0 mA, fIN = 12 MHz, measured at pin 20 1,2,3 All High level output voltage 2/ VOH VCC = 4.5 V, IOH = -4.0 mA, VIH = 2.5 V, VIL = 0.4 V 1,2,3 All Low level output voltage 2/ VOL VCC = 4.5 V, IOL = 4.0 mA, VIH = 2.5 V, VIL = 0.4 V 1,2,3 All High level input current 3/ IIH1 VCC = 5.5 V, VIN = 2.5 V 1,2,3 All High level input current 4/ 5/ IIH2 VCC = 5.5 V, VIH = 2.5 V 1,2,3 Low level input current 3/ IIL1 VCC = 5.5 V, VIN = 0.0V Low level input current 4/ 5/ IIL2 VCC = 5.5 V, IIN = 0.0 V Functional tests 6/ Unit Max 150 3.7 mA V 0.4 V -10 +10 µA All -107 -630 µA 1,2,3 All -10 +10 µA 1,2,3 All -134 -700 µA VCC = 4.5 V, VIH = 2.5 V, VIL = 0.4 V, IOH = -4.0 mA, IOL = 4.0 mA, f = 12 MHz 7,8 All VCC = 4.5 V, VIH = 2.5 V, VIL = 0.4 V, IOH = -4.0 mA, IOL = 4.0 mA, fIN = 12 MHz, See figures 4 through 20 9,10,11 All 200 ns 9,10,11 All 20 ns Pass/Fail Delay timing: READY low delay (CPU handshake) tD1 IOEN high delay (CPU handshake) tD2 CPU MEMWR low delay tD3 9,10,11 All 120 ns CPU MEMOE low delay tD4 9,10,11 All 115 ns EXTLD low delay tD5 9,10,11 All 130 ns RESET low delay tD6 9,10,11 All 30 ns Internal Register delay (read) tD7 9,10,11 All 60 ns Internal Register delay (write) tD8 9,10,11 All 60 ns Register Data/Address setup time tD9 9,10,11 All 40 ns Register Data/Address hold time tD10 9,10,11 All 0 ns BC , SOM cycle DMA mode tD11 9,10,11 All 120 ns INT low delay tD12 9,10,11 All 50 ns 7/ 8/ See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Group A subgroups 1/ Conditions -55°C ≤ TC ≤+125°C unless otherwise specified Device types Limits Min Unit Max Delay Timing - Continued: RTU, SOM cycle DMA delay tD13 VCC = 4.5 V, VIH = 2.5 V, VIL = 0.4 V, IOH = -4.0 mA, IOL = 4.0 mA, fIN = 12 MHz, See figures 4 through 20 9,10,11 All 200 ns 7/ 8/ 1553 Command Word setup time tD14 9,10,11 All 60 ns 1553 Command Word hold time tD15 9,10,11 All 60 ns MT , SOM cycle DMA delay tD16 9/ 9,10,11 All 200 ns CS low to MEMCS low delay tD17 9,10,11 All 30 ns OE low to MEMOE low delay tD18 9,10,11 All 30 ns WR low to MEMWR low delay tD19 9,10,11 All 30 ns BUSGRNT high delay tD20 9,10,11 All 25 ns BUSACK low address delay tD21 9,10,11 All 45 ns BUSACK high address delay tD22 9,10,11 All 25 ns Address increment delay tD23 9,10,11 All 200 ns 9,10,11 All 70 ns Pulse Width Timing: READYD pulse width (CPU handshake) tPW1 VCC = 4.5 V, VIH = 2.5 V, VIL = 0.4 V, IOH = -4.0 mA, IOL = 4.0 mA, fIN = 12 MHz, See figures 4 through 20 8/ CPU MEMWR low pulse width tPW2 9,10,11 All 70 ns CPU MEMCS low pulse width tPW3 9,10,11 All 70 ns EXTLD low pulse width tPW4 9,10,11 All 70 ns RESET low pulse width tPW5 9,10,11 All 70 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Group A subgroups 1/ Conditions -55°C ≤ TC ≤+125°C unless otherwise specified Device types Limits Min Unit Max Pulse Width Timing - Continued: DMA MEMWR low pulse width tPW6 VCC = 4.5 V, VIH = 2.5 V, VIL = 0.4 V, IOH = -4.0 mA, IOL = 4.0 mA, fIN = 12 MHz, See figures 4 through 20 9,10,11 All 70 ns 8/ DMA MEMCS low pulse width tPW7 9,10,11 All 70 ns BCSTART low pulse width tPW8 9,10,11 All 70 ns EOM low pulse width tPW9 9,10,11 All 50 200 ns INT low pulse width tPW10 9,10,11 All 20 200 ns INT low ( BC EOM ) pulse width tPW11 9,10,11 All 60 SOM low pulse width tPW12 9,10,11 All 50 200 ns NBGRNT low pulse width tPW13 9,10,11 All 50 200 ns ADRINC low pulse width tPW14 9,10,11 All 50 200 ns MSTRCLR low pulse width tPW15 9,10,11 All 150 ns 9,10,11 All 40 ns 83 ns ns DMA Cycle Data/Address set-up and hold timing: DMA address setup time tAS1 VCC = 4.5 V, VIH = 2.5 V, VIL = 0.4 V, IOH = -4.0 mA, IOL = 4.0 mA, fIN = 12 MHz, See figures 4 through 20 7/ 8/ DMA data setup time tDS1 9,10,11 All DMA address setup time tAS2 9,10,11 All 45 ns DMA data setup time tDS2 9,10,11 All 83 ns DMA address hold time tAH1 9,10,11 All 60 ns DMA data hold time tDH1 9,10,11 All 30 ns DMA address hold time tAH2 9,10,11 All 0 ns DMA data hold time tDH2 9,10,11 All 0 ns Maximum clock frequency fMAX 9,10,11 All 50 percent duty cycle 7/ 16.0 MHz See footnotes on next page. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 7 TABLE I. Electrical performance characteristics -Continued. 1/ All group A subgroup testing may be performed concurrently. 2/ Measured at the following pins: Case X: Pins 3 through 5, 14, 16, 21 through 39, 42, 43, 45 through 47, 50, 56, 57, and 59 through 77. Case Y: Pins 5 through 8, 10, 11, 13, 15, 21, 28, 32, 33, 35, 39, and 45 through 81. 3/ Measured at the following pins: Case X: Pins 7 through 9, 11 through 13, 17, 19, 21 through 28, 38, 39, 44, 48, 49, 51, 53 through 55, 60 through 67 and 77. Case Y: Pins 9, 14, 16 through 19, 22 through 24, 26, 27,29, 31,34, 38, 45 through 47, and 66 through 81. 4/ Measured at the following pins: Case X: Pins 1, 2, 6, 10, 41, and 52. Case Y: Pins 2 through 4, 12, 20, and 25. 5/ For device type 03, case X, pin 52 and case Y, pin 25 have a 0.001 µf capacitor to ground. 6/ Functional tests performed to verify functionality of device as a handshake intermediary between MIL- STD-1750 Central Processing Units (CPU) and MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU) and Bus Monitor (MT). 7/ Parameter shall be tested as part of device intial characterization and after design and process changes. Parameter shall be guaranteed to the limits specified in table I for all lots not specifically tested. 8/ All timing characterisitics measured at 50 percent of waveform, unless otherwise specified. 9/ For device types 02 and 03, tD16 is referenced from the rising edge of READYD as shown in figure 19. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 8 Case outline X Symbol A Φb D D1 D2 E E1 E2 e e1 e2 L S S1 Millimeters Min Max 6.35 0.33 0.58 47.50 41.78 42.04 37.97 38.23 53.34 48.13 48.39 45.59 45.85 2.54 TYP 2.41 2.67 1.14 1.40 0.61 0.66 1.78 2.03 1.91 TYP Inches Min Max .250 .013 .023 1.870 1.645 1.655 1.495 1.505 2.100 1.895 1.905 1.795 1.805 .100 TYP .095 .105 .045 .055 .240 .260 .070 .080 .075 TYP NOTES: 1. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. FIGURE 1. Case outline(s). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 9 Case outline Y Symbol Millimeters Min A Inches Max Min 4.72 A1 .186 2.03 REF Φb 0.30 Max .080 REF 0.46 .012 .018 Φc 0.20 0.30 D 40.51 40.77 1.595 1.605 E 55.50 55.75 2.185 2.195 e L .008 1.27 TYP .050 TYP 10.16 S1 .012 .400 2.41 REF .095 REF NOTES: 1. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. FIGURE 1. Case outline(s) - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 10 Device types All Case outline X Device types All Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 SELECT 27 D03 53 BUSACK 2 RD/ WR 28 D01 54 WR 3 READYD 29 SSFLAG 55 CS 4 EXTEN 30 SSBUSY 56 MEMOE 5 TAGEN 31 RTU/ BC 57 MEMWR 6 EOM 32 A14 58 No connection 7 SOM 33 A12 59 MT 8 STATERR 34 A10 60 D14 9 ADR INC 35 A08 61 D12 10 MEM/ REG 36 A06 62 D10 11 CLOCKIN 37 A04 63 D08 12 LOOPERR 38 A02 64 D06 13 BUSREQ 39 A00 (LSB) 65 D04 14 BUSGRNT 40 Ground 66 D02 15 No connection 41 STRBD 67 D00 (LSB) 16 MEMCS 42 IOEN 68 SVCREQ 17 OE 43 EXTLD 69 DBAC 18 No connection 44 CHB/ CHA 70 A15 (MSB) 19 NBGRNT 45 INT 71 A13 20 VCC 46 BCSTART 72 A11 21 D15 (MSB) 47 RESET 73 A09 22 D13 48 MSGERR 74 A07 23 D11 49 CTLIN B/ A 75 A05 24 D09 50 CTLOUT B/ A 76 A03 25 D07 51 TIMEOUT 77 A01 26 D05 52 MSTRCLR 78 Chassis ground FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 11 Device types All Case outline Y Device types All Case outline Y Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 No connection 29 WR 57 A12 2 SELECT 30 No connection 58 A13 3 STRBD 31 CS 59 A14 4 RD/ WR 32 MEMCS 60 A15 (MSB) 5 IOEN 33 MEMOE 61 RTU/ BC 6 READYD 34 OE 62 DBAC 7 EXTLD 35 MEMWR 63 SSBUSY 8 EXTEN 36 No connection 64 SVCREQ 9 CHB/ CHA 37 No connection 65 SSFLAG 10 TAGEN 38 NBGRNT 66 D00 (LSB) 11 INT 39 MT 67 D01 12 EOM 40 VCC 68 D02 13 BCSTART 41 No connection 69 D03 14 SOM 42 No connection 70 D04 15 RESET 43 Ground 71 D05 16 STATERR 44 Chassis ground 72 D06 17 MSGERR 45 A00 (LSB) 73 D07 18 ADR INC 46 A01 74 D08 19 CTLIN B/ A 47 A02 75 D09 20 MEM/ REG 48 A03 76 D10 21 CTLOUT B/ A 49 A04 77 D11 22 CLOCKIN 50 A05 78 D12 23 TIMEOUT 51 A06 79 D13 24 LOOPERR 52 A07 80 D14 25 MSTRCLR 53 A08 81 D15 (MSB) 26 BUSREQ 54 A09 82 No connection 27 BUSACK 55 A10 28 BUSGRNT 56 A11 FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 12 FIGURE 3. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 13 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 4. Timing diagram - CPU reads from internal register. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 14 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 5. Timing diagram - CPU writes to internal register. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 15 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 6. Timing diagram - CPU reads from external register. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 16 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 7. Timing diagram - CPU writes to external register. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 17 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 8. Timing diagram - CPU read from RAM. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 18 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 9. Timing diagram - CPU writes to RAM. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 19 FIGURE 10. Timing diagram - 1553 terminal to interface unit handshaking. FIGURE 11. Timing diagram - 1553 terminal I/O delay. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 20 FIGURE 12. Timing diagram - interface unit address increment. NOTE: RESET (low) pulse width will be approximately equal to that of MSTRCLR (low). FIGURE 13. Timing diagram - interface unit direct reset. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 21 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus. FIGURE 14. Timing diagram - programmed interface unit reset. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 22 FIGURE 15. Timing diagram - RTU SOM (no connection). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 23 FIGURE 16. Timing diagram - RTU EOM (no connection). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 24 FIGURE 17. Timing diagram - BC SOM (no connection). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 25 FIGURE 18. Timing diagram - BC EOM (no connection). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 26 NOTE: For device types 02 and 03, tD16 is referenced from the rising edge of READYD. FIGURE 19. Timing diagram - MT SOM (no connection). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 27 FIGURE 20. Timing diagram - DMA read/write (SOM/EOM cycles). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 28 TABLE II. Electrical test requirements. MIL-PRF-38534 test requirements Subgroups (in accordance with MIL-PRF-38534, group A test table) Interim electrical parameters 1, 7, 9 Final electrical parameters 1*, 2, 3, 7*, 8, 9*, 10, 11 Group A test requirements 1, 2, 3, 7, 8, 9, 10, 11 Group C end-point electrical parameters 1, 2, 3, 7, 8, 9, 10, 11 Not applicable End-point electrical parameters for Radiation Hardness Assurance (RHA) devices * PDA applies to subgroup 1, 7, and 9. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply: a. b. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TA as specified in accordance with table I of method 1015 of MIL-STD-883. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Conformance and periodic inspections. Conformance inspection (CI) and periodic inspection (PI) shall be in accordance with MIL-PRF-38534 and as specified herein. 4.3.1 Group A inspection (CI). Group A inspection shall be in accordance with MIL-PRF-38534 and as follows: a. Tests shall be as specified in table II herein. b. Subgroups 4, 5, and 6 shall be omitted. 4.3.2 Group B inspection (PI). Group B inspection shall be in accordance with MIL-PRF-38534. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 29 4.3.3 Group C inspection (PI). Group C inspection shall be in accordance with MIL-PRF-38534 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA as specified in accordance with table I of method 1005 of MIL-STD-883. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.3.4 Group D inspection (PI). Group D inspection shall be in accordance with MIL-PRF-38534. 4.3.5 Radiation Hardness Assurance (RHA) inspection. RHA inspection is not currently applicable to this drawing. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated as specified in MIL-PRF38534. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0514. 6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK-103 and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DSCC-VA and have agreed to this drawing. 6.7 Pin functions. Microcircuits conforming to this drawing shall have the pin functions as specified in table III herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 30 TABLE III. Pin functions. Pin name I/O Description SELECT I Select. When active, selects interface unit for operation. RD/ WR I Read/Write. Controls CPU bus data direction. READYD O Ready Data. When active indicates data has been received from, or is available to the CPU. EXTEN O External Enable. Output from interface unit to enable output from external devices. Same timing as MEMEO . TAGEN O Tag Enable. Enables an external time tag counter for transfering the time tag word into memory. EOM I End of Message. Input from 1553 device indicating end of message. SOM I Start of message. Input from 1553 device indicating start of message. STATERR I Status Error. Input from 1553 device when status word has either a bit set or unexpected RTU address (in BC mode only). ADRINC I Address Increment. Send from 1553 device to increment address counter following word transfer. MEM/ REG I Memory/Register. Input from CPU to select memory or register data transfer. CLOCKIN I Clock input; 50 percent duty cycle, 16 MHz, maximum. LOOPERR I Loop Error. Input from 1553 device if short loop BIT fails. BUSREQ I Bus Request. When active, indicates 1553 device requires use of the address/data bus. BUSGRNT O Bus Grant. Handshake output to 1553 device in response to Bus Request indicating address/data bus available to 1553 device. MEMCS O Memory Chip Select. Low from interface unit enable external RAM. Used with 4K x 4 RAM type device to read RAM or used in conjunction with MEMWR to write data into RAM. OE I Output Enable. Input from 1553 device used to enable memory on the parallel bus. NBGRNT I Low pulse from 1553 device preceding start of receiving new protocol sequence. Used with superseding command to reset DMA in progress. VCC I Logic power supply (+5.0 V). D15 I/O Data Bus Bit 15 (MSB). D13 I/O Data Bus Bit 13. D11 I/O Data Bus Bit 11. D09 I/O Data Bus Bit 9. D07 I/O Data Bus Bit 7. D05 I/O Data Bus Bit 5. D03 I/O Data Bus Bit 3. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 31 TABLE III. Pin functions - Continued. Pin name I/O Description D01 I/O Data Bus Bit 1. SSFLAG O Subsystem Flag. Output to 1553 device to set RTU subsystem flag status bit. SSBUSY O Subsystem Busy. Output to 1553 device to set RTU subsystem busy flag. RTU/ BC O Output to 1553 device used in conjunction with MT to set operating mode. A14 O Address Bit 14. A12 O Address Bit 12. A10 O Address Bit 10 A08 O Address Bit 8. A06 O Address Bit 6. A04 O Address Bit 4. A02 I/O Address Bit 2. A00 I/O Address Bit 0 (LSB). Ground - Signal return. STRBD I Strobe Data. Used in conjunction with SELECT to indicate a data transfer cycle to/from the CPU. IOEN O Input/Output Enable. Output from interface unit to enable external buffers/latches connecting the hybrid to the address/data bus. EXTLD O External load. Used to load data into external device via the interface unit data bus. Same timing as MEMWR . Input from 1553 in RTU mode used to indicate received 1553 message came in either channel A or B. CHB/ CHA INT O Interrupt. Interrupt pulse line to CPU BCSTART O Bus Controller Start. Output to 1553 to initiate BC cycle. RESET O Reset. Output to external device from interface unit consisting of the OR condition of CPU reset and CPU Master Clear. MSGERR I Message error. Input from 1553 device when an error occurs in message sequence. CTLIN B /A O Input to change memory map area (0 = area A). CTLOUT B/ A O Output from interface unit selecting which area is to be active (0 = area A). TIMEOUT I Input from 1553 device indicating no response time-out. MSTRCLR I Master Clear. Power-on reset from CPU. Resets DMA in progress and internal registers to logic "0". STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 32 TABLE III. Pin functions - Continued. Pin name I/O Description BUSACK I Bus Acknowledge. Input from 1553 device acknowledge receipt of BUSGRNT . WR I Write. Input from 1553 device for writing data into memory. CS I Chip Select. Input from 1553 device that is routed to MEMCS . MEMOE O Memory Output Enable. Output from interface unit to enable memory output data. MEMWR O Memory Write. Output pulse from interface unit to write data bus into memory. MT O Bus Monitor. Used in conjunction with RTU/ BC to set operating mode. D14 I/O Data Bus Bit 14. D12 I/O Data Bus Bit 12. D10 I/O Data Bus Bit 10. D08 I/O Data Bus Bit 8. D06 I/O Data Bus Bit 6. D04 I/O Data Bus Bit 4. D02 I/O Data Bus Bit 2. D00 I/O Data Bus Bit 0 (LSB). SVCREQ O Service Request. Used to set service request bit in RTU Block Status Word. DBAC O Dynamic Bus Acceptance. Used to set status bit in RTU Block Status Word. A15 O Data Bus Bit 15 (MSB). A13 O Data Bus Bit 13. A11 O Data Bus Bit 11. A09 O Data Bus Bit 9. A07 O Data Bus Bit 7. A05 O Data Bus Bit 5. A03 O Data Bus Bit 3. A01 I/O Data Bus Bit 1. -- Chassis Ground Chassis Ground STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88586 A REVISION LEVEL C SHEET 33 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-03-01 Approved sources of supply for SMD 5962-88586 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revisions of MIL-HDBK-103 and QML-38534. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-8858601XA 5962-8858601XC 19645 19645 BUS-66300II-140 BUS-66300II-883B 5962-8858601YA 5962-8858601YC 19645 19645 BUS-66301II-140 BUS-66301II-883B 5962-8858602XA 5962-8858602XC 5962-8858602YA 5962-8858602YC 88379 88379 88379 88379 CT2566-001-2 CT2566-001-1 CT2566-201-2 CT2566-201-1 5962-8858603XA 5962-8858603XC 5962-8858603YA 5962-8858603YC 88379 88379 88379 88379 CT2566-002-2 CT2566-002-1 CT2566-202-2 CT2566-202-1 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number Vendor name and address 19645 ILC Data Device Corporation 105 Wilbur Place Bohemia, NY 11716 88379 Aeroflex Circuit Technology Corporation 35 South Service Road Plainview, NY 11803-4101 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.