PRELIMINARY ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83908I-02 is a low skew, high performance ICS 1-to-8 Crystal Oscillator/3.3V LVCMOS-to-3.3V HiPerClockS™ LVCMOS fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS83908I-02 has selectable single ended clock or two crystal-oscillator inputs. There is an output enable to disable the outputs by placing them into a highimpedance state. • Eight LVCMOS/LVTTL outputs (19Ω typical output impedance) Guaranteed output and part-to-part skew characteristics make the ICS83908I-02 ideal for those applications demanding well defined performance and repeatability. • Part to Part Skew: TBD • Two Crystal oscillator input pairs One LVCMOS/LVTTL clock input • Crystal input frequencry range: 10MHz - 40MHz • Output frequency: 200MHz (typical) CLK0 • Output Skew: TBD • RMS phase jitter @ 25MHz (100Hz - 1MHz): 0.22ps (typical) VDD = VDDO = 3.3V Offset Noise Power 100Hz ............. -111.4 dBc/Hz 1kHz ............. -139.9 dBc/Hz 10kHz ............. -157.3 dBc/Hz 100kHz ............. -157.5 dBc/Hz • Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM OE CLK_SEL0 • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pullup Pulldown PIN ASSIGNMENT CLK_SEL1 Pulldown XTAL_IN0 OSC 0 0 XTAL_OUT0 Q0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GND XTAL_IN1 XTAL_OUT1 VDDO Q7 Q6 GND Q5 Q4 VDDO CLK_SEL1 OE ICS83908I-02 XTAL_IN1 OSC 8 LVCMOS Outputs 0 1 XTAL_OUT1 Q7 CLK0 VDD XTAL_IN0 XTAL_OUT0 VDDO Q0 Q1 GND Q2 Q3 VDDO CLK_SEL0 CLK0 Pulldown 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View 1 0 1 1 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 1 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD XTAL_IN0, XTAL_OUT0 VDDO Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 GND CLK_SEL0, CLK_SEL1 CLK0 2, 3 4, 10, 15, 21 5, 6, 8, 9, 16, 17, 19, 20 7, 18, 24 11, 14 12 Type Power Description Power Core supply pin. Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. Output supply pins. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. Input Power Power supply ground. Clock select inputs. See Table 3, Input Reference Function Table. Input Pulldown LVCMOS / LVTTL interface levels. Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. 13 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1, 22, 23 Input XTAL_OUT1 is the output. XTAL_IN1 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ VDDO = 3.465V 7 pF CPD Power Dissipation Capacitance (per output) VDDO = 2.625V 7 pF VDDO = 2V 6 pF VDDO = 3.3V ± 5% 19 Ω VDDO = 2.5V ± 5% 21 Ω VDDO = 1.8V ± 0.2V 32 Ω ROUT Output Impedance TABLE 3. INPUT REFERENCE FUNCTION TABLE Control Inputs CLK_SEL1 CLK_SEL0 0 0 Reference XTAL0 (default) 0 1 XTAL1 1 0 CLK0 1 1 CLK0 IDT ™ / ICS™ LVCMOS FANOUT BUFFER 2 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 84.6°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current IDDO Output Supply Current No Load & XTALx selected 25 mA No Load & CLK0 selected 0 mA No Load & CLK0 selected 0 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2. 5 2.625 I DD Power Supply Current IDDO Output Supply Current Test Conditions V No Load & XTALx selected 25 mA No Load & CLK0 selected 0 mA No Load & CLK0 selected 0 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter V DD Core Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current IDDO Output Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 2.0 V No Load & XTALx selected 25 mA No Load & CLK0 selected 0 mA No Load & CLK0 selected 0 mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units V DD Core Supply Voltage 2.375 2. 5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current IDDO Output Supply Current IDT ™ / ICS™ LVCMOS FANOUT BUFFER Test Conditions No Load & XTALx selected 15 mA No Load & CLK0 selected 0 mA No Load & CLK0 selected 0 mA 3 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current IDDO Output Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 1.6 1.8 2.0 V No Load & XTALx selected 15 mA No Load & CLK0 selected 0 mA No Load & CLK0 selected 0 mA TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL VOH VOL Input Low Current CLK0, CLK_SEL0:1 OE CLK0, CLK_SEL0:1 OE Output HighVoltage Output Low Voltage Test Conditions Minimum VDD = 3.3V ± 5% VDD = 2.5V ± 5% VDD = 3.3V ± 5% VDD = 2.5V ± 5% Typical Maximum Units 2.2 VDD + 0.3 V 1.6 VDD + 0.3 V -0.3 1.3 V -0.3 0.9 V VDD = 3.3V or 2.5V ± 5% 150 µA VDD = 3.3V or 2.5V ± 5% 5 µA VDD = 3.3V or 2.5V ± 5% -5 µA VDD = 3.3V or 2.5V ± 5% -150 µA VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 0.2V; NOTE 1 1.2 V VDDO = 3.3V ± 5%; NOTE 1 0.6 V VDDO = 2.5V ± 5%; NOTE 1 0.5 V VDDO = 1.8V ± 0.2V; NOTE 1 0. 4 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation / cut Typical Maximum Units Fundamental 40 MHz Equivalent Series Resistance (ESR) Frequency 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW IDT ™ / ICS™ LVCMOS FANOUT BUFFER 10 4 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t R / tF Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 5 t jit(Ø) Test Conditions w/External Output Frequency XTAL w/External CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Minimum Typical Maximum Units 40 MHz 10 200 MHz 2 ns TBD ps TBD ps 25MHz, (100Hz - 1MHz) 0.22 ps 20% to 80% 457 ps 50 % 10 ns 8 ns Maximum Units 40 MHz Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t R / tF Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 5 t jit(Ø) Test Conditions w/External Output Frequency XTAL w/External CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Minimum Typical 10 200 MHz 2.2 ns TBD ps TBD ps 25MHz, (100Hz - 1MHz) 0.21 ps 20% to 80% 463 ps 50 Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 5 % 10 ns 8 ns ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t R / tF Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 5 t jit(Ø) Test Conditions w/External Output Frequency XTAL w/External CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Minimum Typical Maximum Units 40 MHz 10 200 MHz 2.5 ns TBD ps TBD ps 25MHz, (100Hz - 1MHz) 0.22 ps 20% to 80% 487 ps 50 % 10 ns 8 ns Maximum Units 40 MHz Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t R / tF Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 5 t jit(Ø) Test Conditions w/External Output Frequency XTAL w/External CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Minimum Typical 10 200 MHz 2.3 ns TBD ps TBD ps 25MHz, (100Hz - 1MHz) 0.29 ps 20% to 80% 470 ps 50 Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 6 % 10 ns 8 ns ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t R / tF Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 5 t jit(Ø) Test Conditions w/External Output Frequency XTAL w/External CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Minimum Typical Maximum Units 40 MHz 10 200 MHz 2.6 ns TBD ps TBD ps 25MHz, (100Hz - 1MHz) 0.3 ps 20% to 80% 518 ps 50 % Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 7 10 ns 8 ns ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.22ps (typical) -90 -100 -110 -120 -130 -140 -150 -160 Raw Phase Noise Data ➤ NOISE POWER dBc Hz TYPICAL PHASE NOISE AT 25MHZ @ 3.3V 0 -10 -20 -30 -40 -50 -60 -70 -80 -170 -180 -190 100 1k 10k 100k 1M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVCMOS FANOUT BUFFER 8 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDO SCOPE VDD Qx VDDO Qx LVCMOS GND LVCMOS GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% 2.4V±0.065V 0.9V±0.1V SCOPE VDD, VDDO SCOPE VDD Qx VDDO LVCMOS Qx GND GND LVCMOS -1.25V±5% -0.9V±0.1V 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 1.6V±0.025V 0.9V±0.1V PART 1 Qx SCOPE VDD VDDO Qx PART 2 Qy GND LVCMOS V DDO 2 V DDO 2 tsk(pp) -0.9V±0.1V 2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT IDT ™ / ICS™ LVCMOS FANOUT BUFFER PART-TO-PART SKEW 9 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY 80% 80% CLK0 Clock Outputs VDD VDD 2 2 20% 20% tR VDDO Q0:Q7 tF 2 tpLH VDDO 2 tpHL PROPAGATION DELAY OUTPUT RISE/FALL TIME V DDO 2 Q0:Q7 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVCMOS FANOUT BUFFER 10 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY APPLICATION INFORMATION CRYSTAL INPUT INTERFACE quencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 1. Typical results using parallel 18pF crystals are shown in Table 5. A crystal can be characterized for either series or parallel mode operation. The ICS83908I-02 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel cr ystal without additional components and generate fre- XTAL_OUT C1 15p X1 18pF Parallel Crystal XTAL_IN C2 15p FIGURE 1. Crystal Input Interface LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE IDT ™ / ICS™ LVCMOS FANOUT BUFFER 11 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resister can be tied from XTAL_IN to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 12 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 84.6°C/W 1 2.5 80.3°C/W 78.1°C/W TRANSISTOR COUNT The transistor count for ICS83908I-02 is: 277 IDT ™ / ICS™ LVCMOS FANOUT BUFFER 13 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 IDT ™ / ICS™ LVCMOS FANOUT BUFFER 14 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83908AGI-02 TBD 24 Lead TSSOP tube -40°C to 85°C ICS83908AGI-02T TBD 24 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS83908AGI-02LF ICS83908AI02L 24 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS83908AGI-02LFT ICS83908AI02L 24 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 15 ICS83908AGI-02 REV. B JULY 24, 2007 ICS83908I-02 LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA