AD ADP3041ARUZ

TFT LCD Panel Power Module
ADP3041
FEATURES
600 kHz PWM Frequency
Fully Integrated 1.5 A Power Switch
3% Output Regulation Accuracy
Simple Compensation
Small Inductor and MLC Capacitors
300 ␮A Quiescent Supply Current
90% Efficiency
Undervoltage Lockout
5 Buffers
TSSOP 20-Lead Package
Pb-Free Part
APPLICATIONS
TFT LCD Bias Supplies
GENERAL DESCRIPTION
The ADP3041 is a fixed frequency, PWM step-up dc-to-dc
switching regulator with five buffers capable of 12 V boosted
output voltage in a TSSOP 20-lead package. It provides high
efficiency, low noise operation, and excellent dynamic response,
and is easy to use. The high switching frequency allows for small,
cost-saving, external inductive and capacitive components. The
ADP3041 operates in PWM current mode. The current limit
and the power switch are integrated completely on-chip.
Capable of operating from 2.5 V to 5.5 V input, the ADP3041
is ideal for thin-film transistor (TFT) liquid crystal display
(LCD) module applications, where local point-of-use power
regulation is required. Supporting output voltages down to 4.5 V,
the ADP3041 is ideal to generate today’s low voltage rails, providing the optimal solution in its class for delivering power
efficiently, responsively, and simply with minimal printed circuit
board area.
The ADP3041 integrates five buffers. Each buffer can deliver
35 mA output current and has rail-to-rail input and output
capability.
FUNCTIONAL BLOCK DIAGRAM
COMP
REF
FB
IN
ERROR
AMP
ADP3041
gm
BIAS
SW
F/F
R Q
RAMP
GEN
COMPARATOR
NC
S
DRIVER
OSC
SD
SS
CURRENT
SENSE
AMPLIFIER
SOFT START
PGND
AVCC
VCMO
VCMI
G1I
G1O
G2I
G2O
G3I
G3O
G4I
G4O
AGND
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADP3041–SPECIFICATIONS1 (V
Parameter
Symbol
SUPPLY
Input Voltage
Operating Current2
VIN
IQSW
Quiescent Current
Shutdown Current
ERROR AMPLIFIER
Feedback Voltage Accuracy
Line Regulation
FB Bias Current
Overall Regulation
OUTPUT SWITCH
On Resistance
Output Load Current
IQ
ISD
= 3.3 V, TA = –40ⴗC to +85ⴗC, unless otherwise noted.)
Conditions
RDS (ON)
ILOAD
fOSC
DMAX
DMIN
SOFT START
Charge Current
Typ
Max
Unit
2.5
3.3
1
5.5
5
V
mA
270
500
10
µA
µA
1.233
1.251
+0.15
100
+3
V
%/V
nA
%
300
mΩ
VIN = 2.5 V to 5.5 V
1.215
–0.15
Line, Temperature
–3
At 1.5 A, VIN = 3.3 V
Continuous Operation,
VIN = 3.3 V, VOUT = 10 V
VSWITCH = 12 V, SD = 0 V
ILOAD = 200 mA, VOUT = 10 V
ILOAD = 100 mA, VOUT = 10 V
300
5
90
90
0.4
COMP = Open, FB = 1 V
COMP = Open, FB = 1 V
VSS = 3.3 V, CSS = 1 nF
SHUTDOWN
Input Voltage Low
Input Voltage High
0.6
80
0.9
90
40
0.8
ICL
COMPENSATION
Transconductance
Gain
gm
AV
1.5
UNDERVOLTAGE LOCKOUT
UVLO Threshold
UVLO Hysteresis
2.2
VOUT
VIN = 2.5 V to 5.5 V
ILOAD = 10 mA to 150 mA,
VOUT = 10 V
–2–
mA
µA
%
%
MHz
%
%
µA
2.5
2.2
CURRENT LIMIT
Peak Switch Current
OUTPUT
Voltage Range
Load Regulation
Min
f = 600 kHz, No Load,
AVCC = Open
Not Switching, AVCC = Open
AVCC = Open
VFB
Leakage Current
Efficiency
OSCILLATOR
Oscillator Frequency
Maximum Duty Cycle
Minimum Duty Cycle
IN
V
V
1.8
A
100
1000
µA/V
V/V
2.4
130
4.5
0.05
2.5
V
mV
12
V
mV/mA
REV. D
ADP3041
Parameter
Symbol
Conditions
BUFFER INPUT
CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
VOS
⌬VOS/⌬T
IB
–40°C ≤ TA ≤ +85°C
Input Voltage Range
Input Impedance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Continuous Output Current
Peak Output Current
POWER SUPPLY
Supply Voltage
Power Supply Rejection Ratio
2
5
80
10
VOH
VOL
IOUT
IPK
NL
VS
PSRR
400
1
IL = 100 µA
VS = 12 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
VS = 4.5 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
IL = 100 µA
VS = 12 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
VS = 4.5 V, IL = 5 mA
11.85
11.75
4.2
4.1
4.38
95
0.995
0.995
0.9985
0.9985
SR
BW
␾m
RL = 10 kΩ, CL = 200 pF
–3 dB, RL = 10 kΩ, CL = 10 pF
RL = 10 kΩ, CL = 10 pF
en
en
in
f = 1 kHz
f = 10 kHz
f = 10 kHz
70
4.5
90
780
–3–
V
V
V
V
V
mV
mV
mV
mV
mV
mA
mA
V/V
V/V
%
12
V
1000
1.2
dB
µA
mA
8
8
65
V/µs
MHz
Degrees
27
25
0.8
nV/√Hz
nV/√Hz
pA/√Hz
NOTES
1
All limits at temperature extremes are guaranteed via correlation and characterization using standard Statistical Quality Control (SQC).
2
This is the average current while switching.
Specifications subject to change without notice.
1.005
1.005
0.01
4.5
VS = 4 V to 12 V,
–40°C ≤ TA ≤ +85°C
VO = VS/2, No Load
–40°C ≤ TA ≤ +85°C
DYNAMIC PERFORMANCE
Slew Rate
Bandwidth
Phase Margin
REV. D
150
250
300
400
35
250
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ,
VO = 0.5 to (VS – 0.5 V)
Unit
mV
µV/°C
600
nA
800
nA
VS + 0.5 V
kΩ
pF
VS – 0.005
11.94
5
42
VS = 12 V
ISY
Current Noise Density
Max
–0.5
Supply Current/Amplifier
NOISE PERFORMANCE
Voltage Noise Density
Typ
–40°C ≤ TA ≤ +85°C
ZIN
CIN
TRANSFER CHARACTERISTICS
Gain
AVCL
Gain Linearity
Min
ADP3041
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 6 V
Buffer Input Voltage . . . . . . . . . . . . . –0.5 V to AVCC + 0.5 V
SW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V
COMP Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +2.5 V
FB Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +1.3 V
SD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mV
Operating Ambient Temperature Range . . . . . –40°C to +85°C
Operating Junction Temperature Range . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
␪JA 2-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
␪JA 4-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
SW 1
20 PGND
IN 2
19 AGND
SD 3
18 FB
NC 4
AVCC 5
17 COMP
ADP3041
16 SS
TOP VIEW 15 VCMO
(Not to Scale)
14 G1O
G1I 7
VCMI 6
G2I 8
13 G2O
G3I 9
12 G3O
G4I 10
11 G4O
NC = NO CONNECT
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Model
ADP3041ARU
–40°C to +85°C
ADP3041ARUZ* –40°C to +85°C
PIN FUNCTION DESCRIPTIONS
Voltage
Output
Package
Option
4.5 V to 12 V TSSOP-20
4.5 V to 12 V TSSOP-20
*Z = Pb-free part.
D1
R1
L1
COUT
R2
SW
PGND
ADP3041
VIN
IN
CIN
RSD
SD
NC
AVCC
VCMI
G1I
AGND
Pin No.
Mnemonic
Function
1
SW
Switching Output
2
IN
Main Power Supply Input
3
SD
Shutdown Input
4
NC
No Connection
5
AVCC
Buffers Power Supply Input
6
VCMI
VCOM Buffer Input
7
G1I
Gamma 1 Buffer Input
8
G2I
Gamma 2 Buffer Input
9
G3I
Gamma 3 Buffer Input
10
G4I
Gamma 4 Buffer Input
RC CC
11
G4O
Gamma 4 Buffer Output
CSS
12
G3O
Gamma 3 Buffer Output
SS
13
G2O
Gamma 2 Buffer Output
VCMO
14
G1O
Gamma 1 Buffer Output
G1O
15
VCMO
VCOM Buffer Output
16
SS
Soft Start Capacitor Timer Set
FB
COMP
G2I
G2O
17
COMP
Compensation Input
G3I
G3O
18
FB
Feedback Voltage Sense Input
G4I
G4O
19
AGND
Analog Signal Ground
20
PGND
Ground Return for Power Transistor
Figure 1. Typical Application
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3041 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. D
Typical Performance Characteristics– ADP3041
0
100
90
TA = 25ⴗC
4.5V < VS < 16V
VCM = VS/2
–50
VS = 16V
INPUT BIAS CURRENT (nA)
QUANTITY (Amplifiers)
80
70
60
50
40
30
–100
–150
VS = 4.5V
–200
–250
20
–300
10
0
–12
–350
–9
–6
–3
0
3
6
INPUT OFFSET VOLTAGE (mV)
9
–40
12
TPC 1. Input Offset Voltage Distribution
85
TPC 4. Input Bias Current vs. Temperature
300
5
4.5V < VS < 16V
4
INPUT OFFSET CURRENT (nA)
250
QUANTITY (Amplifiers)
25
TEMPERATURE (ⴗC)
200
150
100
50
3
2
1
VS = 4.5V
0
VS = 16V
–1
–2
–3
–4
0
0
–5
10
20
30
40
50
60
TCVOS (␮V/ⴗC)
70
80
90
–40
100
TPC 2. Input Offset Voltage Drift Distribution
85
TPC 5. Input Offset Current vs. Temperature
15.96
0
4.46
ILOAD = 5mA
VCM = VS/2
4.45
15.95
VS = 16V
OUTPUT VOLTAGE SWING (V)
–0.25
INPUT OFFSET VOLTAGE (mV)
25
TEMPERATURE (ⴗC)
–0.50
VS = 16V
–0.75
–1.00
VS = 4.5V
15.94
4.44
15.93
4.43
15.92
4.42
15.91
4.41
4.40
15.90
15.89
4.39
VS = 4.5V
15.88
4.38
15.87
4.37
–1.25
–1.50
15.86
–40
25
TEMPERATURE (ⴗC)
85
TPC 3. Input Offset Voltage vs. Temperature
REV. D
4.36
–40
25
TEMPERATURE (ⴗC)
85
TPC 6. Output Voltage Swing vs. Temperature
–5–
ADP3041
0.85
150
ILOAD = 5mA
VCM = VS/2
SUPPLY CURRENT/AMPLIFIER (mA)
OUTPUT VOLTAGE SWING (mV)
135
120
105
90
VS = 4.5V
75
60
45
VS = 16V
30
0.80
VS = 16V
0.75
0.70
0.65
VS = 4.5V
0.60
15
0
ⴚ40
25
TEMPERATURE (ⴗC)
0.55
85
TPC 7. Output Voltage Swing vs. Temperature
(Small Signal)
25
TEMPERATURE (ⴗC)
85
TPC 10. Supply Current/Amplifier vs. Temperature
0.9999
8
RL = 10k⍀
CL = 200pF
4.5V < VS < 16V
VOUT = 0.5V TO 15V
7
SLEW RATE (V/␮s)
RL = 2k⍀
GAIN ERROR (V/V)
ⴚ40
0.9997
VS = 16V
6
VS = 4.5V
5
4
3
2
RL = 600⍀
0.9995
ⴚ40
25
TEMPERATURE (ⴗC)
1
85
–40
TPC 8. Voltage Gain vs. Temperature
85
TPC 11. Slew Rate vs. Temperature
1k
1.1
TA = 25ⴗC
100
VS = 4.5V
10
TA = 25 C
AV = 1
VO = VS /2
1.0
SUPPLY CURRENT/AMPLIFIER (mA)
OUTPUT VOLTAGE (mV)
25
TEMPERATURE (ⴗC)
VS = 16V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.001
0.1
0.01
0.1
1
LOAD CURRENT (mA)
10
100
0
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
14
16
18
TPC 12. Supply Current/Amplifier vs. Supply Voltage
TPC 9. Output Voltage to Supply Rail vs. Load Current
–6–
REV. D
ADP3041
18
10
5
16
1k⍀
10k⍀
GAIN (dB)
–5
–10
–15
–20
TA = 25ⴗC
VS = ⴞ8V
VIN = 50mV rms
CL = 40pF
AV = +1
560⍀
150⍀
–25
10
8
6
4
–35
2
0
1M
10
100M
10M
FREQUENCY (Hz)
10
GAIN (dB)
5
50pF
0
–5
–10
1040pF
100pF
–15
540pF
–20
–25
100k
100k
1M
10M
1M
100M
10M
FREQUENCY (Hz)
120
100
80
+PSRR
60
40
0
–20
140
POWER SUPPLY REJECTION RATIO (dB)
160
400
350
VS = 4.5V
250
200
150
100
0
100
VS = 16V
1k
10k
100k
FREQUENCY (Hz)
1M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
TPC 17. Power Supply Rejection Ratio vs. Frequency,
VS = 16 V
450
50
ⴚPSRR
20
500
300
TA = 25ⴗC
VS = 16V
140
–40
100
TPC 14. Capacitive Loading vs. Frequency Response
10M
TA = 25ⴗC
VS = 4.5V
120
100
+PSRR
80
60
ⴚPSRR
40
20
0
–20
–40
100
TPC 15. Closed-Loop Output Impedance vs. Frequency
REV. D
10k
160
TA = 25ⴗC
VS = ⴞ8V
VIN = 50mV rms
RL = 10k⍀
AV = +1
POWER SUPPLY REJECTION RATIO (dB)
15
1k
TPC 16. Closed-Loop Output Swing vs. Frequency
25
20
100
FREQUENCY (Hz)
TPC 13. Resistive Loading vs. Frequency Response
IMPEDANCE (⍀)
12
–30
–40
100k
TA = 25ⴗC
VS = 16V
AV = +1
RL = 10k⍀
DISTORTION < 1%
14
OUTPUT SWING (V p-p)
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
TPC 18. Power Supply Rejection Ratio vs. Frequency,
VS = 4.5 V
–7–
ADP3041
1k
100
VOLTAGE NOISE DENSITY (nV/√Hz)
TA = 25ⴗC
4.5V ≤ VS ≤ 16V
TA = 25ⴗC
VS = 4.5V
VCM = 2.25V
VIN = 100mV p-p
AV = +1
RL = 10k⍀
90
80
70
OVERSHOOT (%)
100
10
60
50
40
–OS
30
+OS
20
10
1
10
1k
100
FREQUENCY (Hz)
0
10
10k
20
15
TA = 25ⴗC
4.5V < VS < 16V
OUTPUT SWING FROM 0V TO ⴞV
CHANNEL SEPARATION (dB)
1k
TPC 22. Small Signal Overshoot vs. Load Capacitance,
VS = 4.5 V
TPC 19. Voltage Noise Density vs. Frequency
0
100
LOAD CAPACITANCE (pF)
–20
–40
–60
–80
–100
–120
–140
TA = 25ⴗC
VS = ⴞ8V
RL = 10k⍀
10
5
OVERSHOOT SETTLING TO 0.1%
0
–5
UNDERSHOOT SETTLING TO 0.1%
–10
–160
–180
100
–15
1k
10k
100k
1M
10M
100M
0
0.5
FREQUENCY (Hz)
TPC 20. Channel Separation vs. Frequency
OVERSHOOT (%)
70
0
TA = 25ⴗC
VS = 16V
VCM = 8V
VIN = 100mV p-p
AV = +1
RL = 10k⍀
TA = 25ⴗC
VS = 16V
AV = +1
RL = 10k⍀
CL = 300pF
0
0
VOLTAGE (2V/DIV)
80
2.0
1.5
TPC 23. Step Size vs. Settling Time
100
90
1.0
SETTLING TIME (␮s)
60
50
40
–OS
0
0
0
30
0
+OS
20
0
10
0
10
100
LOAD CAPACITANCE (pF)
0
0
1k
TPC 21. Small Signal Overshoot vs. Load Capacitance,
VS = 16 V
0
0
0
0
0
TIME (2␮s/DIV)
0
0
0
TPC 24. Large Signal Transient Response, VS = 16 V
–8–
REV. D
ADP3041
0
0
TA = 25ⴗC
VS = 4.5V
AV = +1
RL = 10k⍀
CL = 300pF
VOLTAGE (1V/DIV)
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME (2␮s/DIV)
0
0
0
0
0
0
0
0
0
TIME (1␮s/DIV)
0
0
0
0
TA = 25ⴗC
VS = 16V
AV = +1
RL = 10k⍀
CL = 100pF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME (1␮s/DIV)
0
0
TA = 25ⴗC
VS = 16V
AV = +1
RL = 10k⍀
0
VOLTAGE (3V/DIV)
0
0
0
0
TPC 27. Small Signal Transient Response, VS = 4.5 V
0
VOLTAGE (50mV/DIV)
0
0
TPC 25. Large Signal Transient Response, VS = 4.5 V
0
0
0
TPC 26. Small Signal Transient Response, VS = 16 V
REV. D
0
0
0
0
TA = 25ⴗC
VS = 4.5V
AV = +1
RL = 10k⍀
CL = 100pF
0
VOLTAGE (50mV/DIV)
0
0
0
0
0
0
TIME (40␮s/DIV)
0
TPC 28. No Phase Reversal
–9–
0
0
ADP3041
to be equal and opposite to maintain steady state, one can say
that t1 × VIN will equal t2 × (VOUT – VIN), if we neglect the effect
of resistance in the inductor and switch and the forward voltage
drop of the diode. From this equality one can derive t1/T = 1 –
VIN/V OUT, where T is the period of a cycle, t1 + t2. This result
gives us the switch duty ratio, t1/T, in terms of the input and
output voltages.
THEORY OF OPERATION
Switching Regulator
The ADP3041 is a boost converter driver that stores energy
from an input voltage in an inductor and delivers that energy,
augmented by the input, to a load at a higher output voltage. It
includes a voltage reference and an error amplifier to compare some fraction of the load voltage to the reference and to
amplify any difference between them. The amplified error
signal is compared to a dynamic signal produced by an internal ramp generator incorporating switch current feedback. The
comparator output timing sets the duty ratio of a switch driving the inductor to maintain the desired output voltage.
In practice, the duty ratio needs to be slightly higher than this
calculation. Because of series resistance in the inductor and the
switch, the voltage across the actual inductance is somewhat less
than the applied VIN, and the actual output voltage is less than
our approximation by the amount of the diode forward voltage
drop. However, the feedback control within the ADP3041 adjusts
the duty ratio to maintain the output voltage. Changes in
load current and input voltage are also accommodated by the
feedback control.
Referring to Figure 1, a typical application powers both the IC
and the inductor from the same input voltage. The on-chip
MOSFET is driven on, pulling the SW pin close to PGND. The
resulting voltage across the inductor causes its current to increase
approximately linearly, with respect to time.
When the MOSFET switch is turned off, the inductor current
cannot drop to zero, and so this current drives the SW node
capacitance rapidly positive until the diode becomes forward
biased. The inductor current now begins to charge the load
capacitor, causing a slight increase in output voltage. Generally,
the load capacitor is made large enough that this increase is very
small during the time the switch is off. During this time, inductor
current is also delivered to the load. In steady state operation,
the inductor current exceeds the load current, and the excess is
what charges the load capacitor. The inductor current falls
during this time, though not necessarily to zero.
During the next cycle, initiated by the on-chip oscillator, the
switch is again turned on so that the inductor current is ramped
up again. The charge on the load capacitor provides load current
during that interval. The remainder of the chip is arranged to
control the duty ratio of the switch to maintain a chosen output
voltage despite changes in input voltage or load current.
A comparator compares the current sense amplifier output to a
factory set limit that resets the flip-flop, turning off the switch.
This prevents runaway or overload conditions from damaging
the switch and reflecting fault overloads back to the input. Of
course, the load is directly connected to the input by way of the
diode and inductor, so protection against short circuited loads
must be done at the power input.
The output voltage is scaled down by a resistor voltage divider
and presented to the gm amplifier. This amplifier operates on
the difference between an on-chip reference and the voltage at
the FB pin so as to bring them to balance. This is when the
output voltage equals the reference voltage multiplied by the
resistor voltage divider ratio.
The gm amplifier drives an internal comparator, which has at its
other input a positive-going ramp produced by the oscillator
and modified by the current sense amplifier. The MOSFET
switch is turned on as the modified ramp voltage rises. When
this voltage exceeds the output of the gm amplifier, the comparator turns off the switch by resetting the flip-flop previously set
by the oscillator. The output of the flip-flop is buffered by a high
current driver, which turned on the MOSFET switch at the
beginning of the oscillator cycle.
In the steady state with constant load and input voltage, the
current in the inductor cycles around some average current
level. The increasing ramp of current depends on input voltage
and t1, the switch-on time, while the decreasing ramp depends
on the difference between the input and output voltage and t2,
the remainder of the cycle. For the peaks of these two ramps
Changes in load current alone require a change in duty ratio in
order to change the average inductor current. Once the inductor
current adapts to the new load current, the duty ratio should
return to nearly its original value, as one can see from the
duty cycle calculation, which depends on input and output
voltages but not on current. Increasing the switch duty ratio
initially reduces the output voltage until the average inductor
current increases enough to offset the reduction of the t2
interval. By limiting the duty ratio, one can prevent this effect
from regeneratively increasing the duty ratio to 100%, which
would cause the output to fall and the switch current to rise
without limit. The duty ratio is limited to about 80% by the
design of the oscillator and an additional flip-flop reset.
The gm amplifier has high voltage gain to ensure the output
voltage accuracy and invariance with load and input voltage.
However, because it is a gm amplifier with a specified current
response to input signal voltages, its high frequency response
can be controlled by the compensation impedance. This permits
the high frequency gain of the gm amplifier to be optimized for
the best compromise between speed of response and frequency
stability.
The stable closed-loop bandwidth of the system can be extended
by the current feedback shown. A signal representing the magnitude of the switch current is added to the ramp. This dynamically
reduces the duty ratio as the current in the inductor increases,
until the gm amplifier restores it, improving the closed-loop
frequency stability.
Soft Start
The soft start pin can load the COMP pin, forcing a low duty
cycle when its voltage is low. A capacitor on SS initially holds
the pin low; however, a small internal current charges the
capacitor, causing SS to rise after SD goes high. As it rises,
–10–
REV. D
ADP3041
COMP is allowed to rise slowly until the control loop limits the
voltage to that required for regulation. SS continues to rise and
no longer affects COMP once soft start is complete.
by 5 mA. This resistance should be placed in series with the
input exposed to an overvoltage.
Output Phase Reversal
When SD goes low, an internal switch discharges the SS
capacitor to return its voltage to zero for soft restart.
The buffer family is immune to phase reversal. Although the
device’s output does not change phase, large currents due to
input overvoltage could damage the device. In applications
where the possibility of an input voltage exceeding the supply
voltage exists, overvoltage protection should be used as described
in the previous section.
Because of the large current that flows into the main MOSFET
switch, it is provided with a separate PGND return to the negative supply terminal to avoid corrupting the small-signal return,
GND, that can be used as a sense line at the output load point.
Buffers
APPLICATION INFORMATION
Output Voltage
This family of buffers is designed to drive large capacitive loads
in LCD applications. Each has high output current drive and
rail-to-rail input/output operation and can be powered from a
single 12 V supply. They are also intended for other applications
where low distortion and high output current drive are needed.
The ADP3041 operates with an adjustable output from VIN to
12 V. The output voltage is fed back to the ADP3041 via resistor dividers R1 and R2 (Figure 1). The feedback voltage is
1.233 V, so the output voltage is set by the formula
Input Overvoltage Protection
R1 

VOUT = 1.233V ×  1 +


R2 
As with any semiconductor device, whenever the input exceeds
either supply voltage, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the
magnitude of the fault current. When the input voltage exceeds
either supply by more than 0.6 V, the internal pin junctions
allow current to flow from the input to the supplies.
(1)
Because the feedback bias current is 100 nA maximum, R2 may
have a value up to 100 kΩ with minimum error due to the bias
current.
Inductor Selection
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the buffers where the input exceeds the supply more than 0.6 V,
a series external resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided
For most applications, the inductor used with the ADP3041
should be in the range of 1 µH to 22 µH. Several inductor
manufacturers are listed in Table I. When selecting an inductor,
it is important to make sure that the inductor used with the
ADP3041 is able to handle a peak current without saturation, and
that the peak current is below the current limit of the ADP3041.
Table I. Inductor Manufacturers
REV. D
Part
L (µH)
Max DCR (mΩ)
Height (mm)
Vendor
CMD4D11-4R7M
CCDRH5D18-100
CR43-4R7
CR43-100
4.7
10
4.7
10
166
124
109
182
1.1
2.0
3.5
3.5
Sumida
847-545-6700
www.sumida.com
DS1608-472
DS1608-103
4.7
10
60
75
2.9
2.9
Coilcraft
847-639-6400
www.coilcraft.com
D52LC-4R7M
D52LC-100M
4.7
10
84
137
2.0
2.0
Toko
847-297-0070
www.tokoam.com
–11–
ADP3041
As a rule, powdered iron cores saturate softly, whereas ferrite cores
saturate abruptly. Open drum core inductors tend to saturate
gradually and are low cost and small in size, making these
types of inductors attractive in many applications. However,
care must be exercised in their placement because they have
high magnetic fields. In applications that are sensitive to magnetic fields, shielded geometrics are recommended.
When selecting an output capacitor, make sure that the ripple
current rating is sufficient to cover the rms switching current
of the ADP3041. The ripple current in the output capacitor is
given by
In addition, inductor losses must be considered. Both core and
copper losses contribute to loss in converter efficiency. To minimize core losses, look for inductors rated for operation at high
switching frequencies. To minimize copper losses, it is best to
use low dc resistance inductors. Typically, it is best to use an
inductor with a dc resistance lower than 20 mΩ per µH.
Multilayer ceramic capacitors are a good choice since they have
low ESR, high ripple current rating, and a very small package
size. Tantalum or OS-CON capacitors can be used; however,
they have a larger package size and higher ESR. Table II lists
some capacitor manufacturers. Consult the manufacturer for
more information.
IRMS (COUT ) = IOUT
VOUT – VIN
VIN
(7)
The inductor value can be estimated using
L = (VOUT – VIN ) × MSLOPE
where MSLOPE is the scaling factor for the proper slope compensation.
MSLOPE
1.456
=
fSW
(3)
Choose the closest standard inductor value as a starting point.
The corresponding peak inductor current can then be calculated.
It is recommended to try several different inductor values, sizes,
and types to find the best inductor for the application. In general, large inductor values lead to lower ripple current, less
output noise, and either larger size or higher dc resistance.
Conversely, low inductor values lead to higher ripple current,
more noise, and either smaller size or lower dc resistance. The
final inductor selection should be based on the best trade-off of
size, cost, and performance.
Capacitor Selection
The ADP3041 requires an input capacitor to reduce the switching
ripple and noise on the IN pin. The value of the input capacitor depends on the application. For most applications, a minimum
of 10 µF is required. For applications that are running close to
current limit or that have large transient loads, input capacitors
in the range of 22 µF to 47 µF are required.
The selection of the output capacitor also depends on the
application. Given the allowable output ripple voltage, ⌬VOUT,
the criteria for selecting the output capacitor can be calculated using
ESRCOUT ≤
∆VOUT
IL (PEAK )
Vendor
Phone No.
Web Address
AVX
Murata
Sanyo
Taiyo Yuden
843-448-9411
770-436-1300
408-749-9714
858-554-0755
www.avxcorp.com
www.murata.com
www.sanyovideo.com
www.t-yuden.com
Diode Selection

 1  VIN × (VOUT – VIN ) 
V
IL (PEAK ) =  IOUT × OUT  + 
VIN  2  L ×VOUT × fS  (4)


(VOUT – VIN ) 
COUT ≥ 8 × IOUT 

f
×
 S VOUT × ∆VOUT 
Table II. Capacitor Manufacturers
(2)
(5)
In specifying a diode, consideration must be given to speed,
forward current, forward voltage drop, reverse leakage current,
and the breakdown voltage. The output diode should be rated to
handle the maximum output current. If the output can be subjected to accidental short circuits, then the diode must be rated to
handle currents up to the current limit of the ADP3041. The
breakdown rating of the diode must exceed the output voltage. A
high speed diode with low forward drop and low leakage will help
improve the efficiency of the converter by lowering the losses of
the diode. Schottky diodes are recommended.
Loop Compensation
Like most current programmed PWM converters, the ADP3041
needs compensation to maintain stability over the operating
conditions of the particular application. For operation at duty
cycles above 50%, the choice of inductor is critical in maintaining stability. If the slope of the inductor current is too small or
too large, the circuit will be unstable. See the Inductor Selection
section for more information on choosing the proper inductor.
The ADP3041 provides a pin (COMP) for compensating the
voltage feedback loop. This is done by connecting a series RC
network from the COMP pin to GND (see Figure 2). For most
applications, the compensation resistor, RC, should be in the
range of 5 kΩ < RC < 400 kΩ, and the compensation capacitor,
C C, in the range of 100 pF < CC < 10 nF. Further details for
selecting the compensation components follow.
(6)
–12–
REV. D
ADP3041
So the compensation resistor, RC, can be calculated by determining the open-loop gain at the crossover frequency, fC, and
setting RC to adjust the closed-loop gain to zero. The open-loop
gain can be approximated (in dB) by
ERROR
AMP
COMP
REF
gm
FB
RC
2

 fC 
 V × RLOAD 

GOC ( fC ) = 20 log IN
–
20log
1
+

 

 f P 1   (12)
 VOUT × 0.65 



C2
CC
gm ×
The boost regulator introduces a right half plane (RHP) zero. This
zero behaves like a zero with respect to the gain but behaves
like a pole with respect to phase. As a result, the RHP zero can
cause instability of the control loop if the bandwidth (in Hertz)
of the loop includes it.
2
V 
R
f Z (RHP ) =  IN  × LOAD
2π × L
 VOUT 
(8)
Note that the RHP zero is dependant on the load. To optimize
the compensation, a nominal load must be chosen. Typically,
choosing an RLOAD that is halfway between no load and full
load works well; but make sure that this load is enough to ensure
CCM operation. The critical value of load resistance, RCRIT, for
CCM is given by
RCRIT =
f ZC =
(9)
(10)
where fC is the crossover frequency.
Another frequency of interest is the pole caused by the output
load and output capacitor. This frequency (in Hertz) is calculated using
fP1 =
REV. D
C2 =
(11)
Note that the frequency varies with load current. Again, use the
nominal load resistance for the calculation.
(14)
1
2 × π × f ZC × RC
(15)
1
(16)
2 × π × RESR × COUT
So, a high frequency pole should be placed to cancel the ESR
zero or at half the switching frequency, whichever is lower. By
placing a pole at half the switching frequency, the high frequency gain is rolled off for better phase margin. Note that the
high frequency pole must be at least a decade above the compensation zero in order for the compensation to work properly.
If this is not the case, the high frequency pole should not be used.
1
2π × RLOAD × COUT
1
2 × π × RC × CC
f Z (ESR) =
To make sure the RHP zero does not cause stability problems,
the control loop bandwidth should be set at around 1/8 the
frequency (in Hertz) of the RHP zero.
1
× f Z (RHP )
8
(13)
20
If the output capacitor selected has a high ESR value, it may be
necessary to add another pole to cancel the zero introduced by
the capacitor’s ESR. The ESR zero location is determined by
So for the nominal load resistance RLOAD, use the half load
resistance or RCRIT, whichever is lower.
fC =
GOC ( f C )
So, the value of CC can be calculated using
CC =
2
VFB
× 10
VOUT
Once the value of the compensation resistor is determined, the
value of the compensation capacitor, CC, can be calculated. The
compensation capacitor sets up a zero to cancel out the pole
created by the output load, fP1. Since the load pole position
varies with load current, the compensation zero should be located
approximately four times the worst-case load pole, 4 × fP1, or at
one half the crossover frequency, 1/2 × fC, whichever is lower.
The frequency of the compensation zero is located at
2 × L × fSW

VIN   VIN 


1 – V

OUT   VOUT 
1
RC =
Figure 2. Compensation Components
(
CC
1 + 2π × fP (HF ) × RC × CC
)
(17)
After all the compensation components have been selected, the
best check for stability and response time is to observe the transient performance of the ADP3041. Adjust RC and CC as necessary
to optimize the transient response. Increasing RC increases
–13–
ADP3041
the high frequency gain. Increasing CC decreases the compensation zero frequency, which increases the stability but slows the
transient response.
as possible. Use the following general guidelines when designing
printed circuit boards (see Figure 1):
Shutdown
2. Keep the high current path from CIN through L1 to the SW
pin and PGND pin as short as possible.
1. Keep CIN close to the IN pin of the ADP3041.
The ADP3041 shuts down to reduce the supply current to a 10 µA
maximum when the shutdown pin is pulled low. In this mode,
the internal reference, error amplifier, comparator, biasing circuitry, and the internal MOSFET switch are turned off. Note
that the output is still connected to the input via the inductor
and Schottky diode when in shutdown.
Layout Procedure
To get high efficiency, good regulation, and stability, a good
printed circuit board layout is required. It is strongly recommended that the evaluation board layout be followed as closely
3. Similarly, keep the high current path from CIN through L1,
D1, and COUT as short as possible.
4. Keep high current traces as short and wide as possible.
5. Place the feedback resistors as close to the FB pin as possible
to prevent noise pickup.
6. Place the compensation components as close to the COMP
pin as possible.
7. Avoid routing noise sensitive traces near the high current
traces and components.
–14–
REV. D
ADP3041
OUTLINE DIMENSIONS
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
1
6.40 BSC
10
PIN 1
0.65
BSC
0.15
0.05
0.30
COPLANARITY 0.19
0.10
1.20
MAX
0.20
0.09
SEATING
PLANE
8ⴗ
0ⴗ
COMPLIANT TO JEDEC STANDARDS MO-153AC
REV. D
–15–
0.75
0.60
0.45
ADP3041
Revision History
Location
Page
12/03—Data Sheet changed from REV. C to REV. D.
Updated formatting of Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Change to TPC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5/03—Data Sheet changed from REV. B to REV. C.
Replaced all TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10/02—Data Sheet changed from REV. A to REV. B.
Updated Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Removed RT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
–16–
REV. D
C03361–0–12/03(D)
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4