ETC LCD08C

05018
LCD05C
thru
LCD24C
. . . engineered solutions for the transient environment™
HIGH SPEED TVS DIODE ARRAY
APPLICATIONS
✔ Ethernet - 10/100 Base T
✔ RS-485
✔ xDSL & ATM
✔ SCSI & USB
✔ Audio/Video I/O Ports
IEC COMPATIBILITY (EN61000-4)
✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV
✔ 61000-4-4 (EFT): 40A - 5/50ns
✔ 61000-4-5 (Surge): 24A, 8/20µs Level 2 (Line to Ground) & Level 3 (Line to Line)
16 PIN DIP
FEATURES
✔ 800 Watts Peak Pulse Power per Line (tp=8/20µs)
✔ Bidirectional Configuration
✔ ESD Protection > 40 kilovolts
✔ Available in Five Voltage Types: 5.0V to 24V
✔ Standard Dual-In-Line Package
✔ PROTECTS UP TO EIGHT (8) LINES
✔ LOW CAPACITANCE: 15pF
MECHANICAL CHARACTERISTICS
✔ Molded 16 Pin Dual-in-Line Package
✔ Weight 1.2grams (Approximate)
✔ Flammability Rating UL 94V-0
✔ Packaged in Tubes 25 per
✔ Marking: Logo, Part Number, Date Code & Pin 1 Indicated by DOT on Top of Package
CIRCUIT DIAGRAM
05018.R5 12/02
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1
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DEVICE CHARACTERISTICS
MAXIMUM RATINGS @ 25°C Unless Otherwise Specified
SYMBOL
VALUE
UNITS
Peak Pulse Power (tp = 8/20µs) - See Figure 1
PPP
800
Watts
Operating Temperature
TJ
-55°C to 150°C
°C
TSTG
-55°C to 150°C
°C
PARAMETER
Storage Temperature
-9
T
T Clamping (0 VoltsTo V(BR) MIN.)
Sec
< 10 x 10
C
ELECTRICAL CHARACTERISTICS PER LINE @ 25°C Unless Otherwise Specified
PART
NUMBER
(Notes 1)
MAXIMUM
CLAMPING
VOLTAGE
(See Fig. 2)
@ 1mA
V(BR)
VOLTS
MAXIMUM
CLAMPING
VOLTAGE
(See Fig. 2)
@ IP = 1 A
VC
VOLTS
@ 8/20µs
VC @ IPP
@VWM
ID
µA
@ 0V, 1 MHz
C
pF
θV(BR)
mV/°C
6.0
8.5
13.3
16.7
26.7
9.8
12.3
19.0
25.5
40.0
24V @ 45A
25.5V @ 40A
32V @ 34A
38V @ 27A
48V @ 22A
100
10
4
4
4
15
15
15
15
15
3
9
16
17
26
RATED
STAND-OFF
VOLTAGE
MINIMUM
BREAKDOWN
VOLTAGE
V WM
VOLTS
5.0
8.0
12.0
15.0
24.0
LCD05C
LCD08C
LCD12C
LCD15C
LCD24C
MAXIMUM TEMPERATURE
CAPACITANCE COEFFICIENT
OF V(BR)
MAXIMUM
LEAKAGE
CURRENT
Note 1: Tested on pin pairs 1 & 16, 2 & 15, 3 &14, 4 & 13, 5 & 12, 6 & 11, 7 & 10 and 8 & 9.
FIGURE 1
PEAK PULSE POWER VS PULSE TIME
120
IPP - Peak Pulse Current - % of IPP
PPP - Peak Pulse Power - Watts
10,000
800W 8/20µs Waveform
1,000
100
10
0.1
1
10
100
1,000
10,000
td - Pulse Duration - µs
05018.R5 12/02
FIGURE 2
PULSE WAVE FORM
2
tf
100
TEST
WAVEFORM
PARAMETERS
tf = 8µs
td = 20µs
Peak Value IPP
80
e-t
60
40
td = t I /2
PP
20
0
0
5
10
15
t - Time - µs
20
25
30
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GRAPHS
FIGURE 3
POWER DERATING CURVE
100
Peak Pulse Power
8/20µs
% Of Rated Power
80
60
40
20
Average Power
0
0
25
50
75
100
125
TL - Lead Temperature - °C
150
FIGURE 4
OVERSHOOT & CLAMPING VOLTAGE FOR SM16LC05
5 Volts per Division
40
30
20
10
0
ESD Test Pulse: 25 kilovolt, 1/30ns (waveform)
FIGURE 5
TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT
VC - cLAMPING vOLTAGE - Volts
16
12
LCD05C
8
4
10
0
2
4
6
8
10
12
14
16
18
IPP - Peak Pulse Current - Amps
05018.R5 12/02
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LCD05C
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LCD24C
DEVICE SPECIFIC APPLICATION NOTE
The LCD Series are low capacitance, bidirectional TVS arrays that are designed to protect I/O or high speed data lines from the damaging effects of
ESD or EFT. This product series has a surge capability of 800 Watts PPP per line for an 8/20µs waveshape and offers ESD protection > 40kV.
BIDIRECTIONAL COMMON MODE CONFIGURATION (Figure 1)
Ideal for use in USB applications, the LCD Series provides up to eight (8) lines of protection in a common mode configuration as depicted in Figure
1.
Circuit connectivity is as follows:
✔ Pins 1, 2, 3, 4, 5, 6, 7, and 8 are connected to ground.
✔ Pins 16 and 15 connected to Port #1 D- and D+.
✔ Pins 14 and 13 connected to Port #2 D+ and D-.
✔ Pins 12 and 11 connected to Port #3 D- and D+.
✔ Pins 10 and 9 connected to Port #4 D+ and D-.
PORT #1
D+
USB OUTPUT
CONNECTOR
USB OUTPUT
CONNECTOR
D-
PORT #2
D+
D-
16
15
14
13
3
4
USB
IC
Circuit board Layout Recommendations
✔
The protection device should be placed near the input
terminals or connectors, the device will divert the
transient current immediately before it can be coupled
into the nearby traces.
USB OUTPUT
CONNECTOR
✔
1
D+
All conductive loops including power and ground loops
should be minimized
✔
The transient current return path to ground should be
kept as short as possible to reduce parasitic inductance.
✔
Ground planes should be used whenever possible.
For multilayer PCBs, use ground vias.
05018.R5 12/02
D+
D-
D12
11
10
9
PORT #3
The path length between the TVS devices and the
protected line should be minimized
✔
2
PORT #4
5
6
7
USB OUTPUT
CONNECTOR
Circuit board layout is critical for Electromagnetic Compatibility (EMC) protection. The following guidelines are
recommended:
8
Figure 1. Typical Common- Mode USB Protection Circuit
4
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LCD24C
PACKAGE OUTLINE & DIMENSIONS
PACKAGE OUTLINE
16 PIN DIP
A
DIMENSIONS
DIM
Orientation Dot
(Pin #1)
B
I
12 Places
C
F
J
12 Places
G
D
16 Places
H
L
K
16 Places
E
A
B
C
D
E
F
G
H
I
J
K
L
MILLIMETERS
MIN
MAX
6.10
7.37
0.25
0°
0.51
3.17
0.84 TYP
0.38
2.54 TYP
INCHES
MIN
MAX
19.8
0.780
6.60
0.240
0.260
7.87
0.290
0.310
0.50
0.010
0.020
10°
0°
10°
0.020
5.08
0.200
0.125
1.78
0.070
0.84 TYP 0.033 TYP 0.033 TYP
0.53
0.015
0.021
2.54 TYP 0.100 TYP 0.100 TYP
NOTES:
1. Dimensions are exclusive of mold flash and metal
burrs.
06003 Rev 1 - 11/01
BULK ORDERING INFORMATION:
No Suffix: Bulk Quantities - 25 pieces per tube.
ProTek Devices
2929 South Fair Lane, Tempe, AZ 85282
Tel: 602-431-8101 Fax: 602-431-2288
E-Mail: [email protected]
Web Site: www.protekdevices.com
COPYRIGHT © ProTek Devices 2003
SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC).
DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is the buyer’s and that in furnishing engineering and
technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products.
05018.R5 12/02
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