a Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10265 65 MSPS performance. The AD10265 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-Channel Matching, ⴞ0.1% Gain Error Channel-Channel Isolation, >80 dB AC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range (ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V) Gain Flatness up to Nyquist: < 0.5 dB 80 dB Spurious-Free Dynamic Range Twos Complement Output Format +3.3 V or +5 V CMOS-Compatible Output Levels 1.05 W Per Channel Industrial and Military Grade The AD10265 operates with ± 5.0 V for the analog signal conditioning with a separate +3.3 V supply for the analog-todigital conversion. Each channel is completely independent allowing operation with independent Encode and Analog inputs. The AD10265 also offers the user a choice of Analog Input Signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10265 is packaged in a 68-lead Ceramic Gull Wing Package, footprint compatible with the earlier generation AD10242 (12-bit, 40 MSPS). Manufacturing is done on Analog Devices’ MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–55°C to +125°C). The AD6640 internal components are manufactured on Analog Devices’ high speed complementary bipolar process (XFCB). APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Anti-Jamming Receivers Multichannel, Multimode Receivers PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD10265 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6640 ADCs. Each AD6640 has an AD9631/AD9632 ac-coupled amplifier front end. The AD6640s have on-chip track-and-hold circuitry, and utilize an innovative multipass architecture, to achieve 12-bit, 1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance for full channel. 5. Footprint compatible family; 68-lead LCCC. FUNCTIONAL BLOCK DIAGRAM AINA3 AINA2 AINA1 AD9632 AINB3 AINB2 AINB1 AD9632 AD9631 AD9631 (LSB) D0A D1A D2A AIN AIN AIN AIN TIMING AD6640 D4A D5A D6A AD6640 AD10265 D11B (MSB) 12 12 9 5 OUTPUT BUFFERING OUTPUT BUFFERING D8B 7 TIMING ENCODEA ENCODEA D10B D9B D7A D8A ENCODEB ENCODEB D3A D7B D9A D10A D11A (MSB) D0B (LSB) D1B D2B D3B D4B D5B D6B REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD10265–SPECIFICATIONS Electrical Characteristics (AV Parameter CC = +5 V; AVEE = –5.0 V; DVCC = +3.3 V; applies to each ADC unless otherwise noted) Temp Test Level Mil Subgroup Min RESOLUTION AD10265AZ Typ Max 12 ACCURACY No Missing Codes Offset Error Gain Error1 Gain Error Channel Match Pass Band Ripple to Nyquist Full Full +25°C Full Full Full VI IV I VI V I 1, 2, 3 2, 3 1 2, 3 –10 –1.0 –2.0 12 Guaranteed 3.5 ± 0.5 ± 0.8 ± 0.1 0.2 Units Bits +10 +1.0 +2.0 0.5 mV % FS % FS % dB ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth High 3 Analog Input Bandwidth Low 3 Full Full Full I I I Full Full Full +25°C +25°C +25°C IV IV IV IV V V 12 12 12 12 99 198 396 0 ENCODE INPUT4, 5 Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic “1” Current (VINH = 5 V) Logic “0” Current (VINL = 0 V) Input Capacitance Full Full Full Full +25°C I I I I V 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 12 2.0 0 500 –400 SWITCHING PERFORMANCE Maximum Conversion Rate6 Minimum Conversion Rate 6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) Full Full +25°C +25°C +25°C +25°C +25°C Full VI V V V V IV IV IV 4, 5, 6 12 65 12 12 12 6.5 6.5 7.0 9.0 +25°C Full +25°C Full +25°C Full I II I II I II 4 5, 6 4 5, 6 4 5, 6 62 60.5 61 60 61 59.5 66 66 65 65 63 62 dB dB dB dB dB dB +25°C Full +25°C Full +25°C Full I II I II I II 4 5, 6 4 5, 6 4 5, 6 61 60 61 59.5 61 59 65 64 64 63 62 62 dB dB dB dB dB dB SNR7 Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz SINAD8 Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz ± 0.5 ± 1.0 ±2 100 200 400 4.0 160 50 V V V 101 202 404 7.0 TTL/CMOS 5.0 0.8 650 800 –320 –200 4.5 7.0 6.5 400 ± 2.0 0.3 –2– 12.5 Ω Ω Ω pF MHz kHz V V µA µA pF MSPS MSPS ps ns ps rms ns ns ns REV. 0 AD10265 Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 1.24 MHz @ 32 MHz TWO-TONE IMD REJECTION 10 f1, f2 @ –7 dBFS CHANNEL-TO-CHANNEL ISOLATION DIGITAL OUTPUTS Logic Compatibility Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY AVCC Supply Voltage I (AVCC) Current AVEE Supply Voltage I (AVEE) Current DVCC Supply Voltage I (DVCC) Current ICC (Total) Supply Current Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) Test Level Mil Subgroup Min AD10265AZ Typ +25°C Full +25°C Full +25°C Full I II I II I II 4 5, 6 4 5, 6 4 5, 6 75 75 72 72 72 72 80 80 80 79 79 79 dBFS dBFS dBFS dBFS dBFS dBFS Full II 4, 5, 6 72 80 dBc +25°C IV 12 80 +25°C IV 12 –1.0 Full V Full Full I I Full Full Full Full Full Full Full Full Full VI V VI V VI V I I IV Max Units 9 @ 17 MHz LINEARITY Differential Nonlinearity (Encode = 20 MHz) Integral Nonlinearity (Encode = 20 MHz) Temp 11 dB ± 0.5 1.5 ± 1.25 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 7, 8 2.8 LSB CMOS DVCC – 0.2 0.2 0.5 Twos Complement +5.0 336 –5.0 66 +3.3 20 422 2.1 0.01 LSB 520 2.4 0.02 V V V mA V mA V mA mA W % FSR/% VS NOTES 1 Gain tests are performed on A IN1 over specified input voltage range. 2 Input capacitance specifications show only ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor. 5 ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD10265” for details. 6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS. 8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 9 Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 17.0 MHz ± 100 kHz, f 2 = 18.0 MHz ± 100 kHz. 11 Channel-to-channel isolation tested with A channel/50 ohm terminated <A IN2 grounded, and a full-scale signal applied to B channel (A IN1). All specifications guaranteed within 100 ms of initial power up regardless of sequencing. Specifications subject to change without notice. REV. 0 –3– AD10265 ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current Table I. Output Coding Min Max Units 0 –7 VEE –10 0 7 0 VCC +10 AVCC 4 +10 V V V mA V V mA +125 +175 +300 +150 °C °C °C °C –10 MSB 0111111111111 0000000000001 0000000000000 1111111111111 1000000000000 Base 10 Input 2047 +1 0 –1 2048 +FS 0.0 V –FS EXPLANATION OF TEST LEVELS 2 ENVIRONMENTAL Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) LSB Test Level –55 –65 I – 100% Production Tested. II – 100% production tested at +25°C, and sample tested at specified temperatures. AC testing done on sample basis. III – Sample Tested Only. NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances for “Z” package: θJC = 11°C/W; θJA = 30°C/W. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25°C; sample tested at temperature extremes. ORDERING GUIDE Model Temperature Range Package Description Package Option AD10265AZ AD10265/PCB –25°C to +85°C (Case) +25°C 68-Lead Leaded Ceramic Chip Carrier Evaluation Board with AD10265AZ Z-68A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10265 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD10265 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1 2, 5, 9–11, 26, 27 3, 4, 12, 15, 16, 34, 35, 55–57 6 7 8 13 14 17–25, 31–33 28 29 30 36–42, 45–49 43, 44, 53, 54, 58–61, 65, 68 50 51 52 62 63 64 66 67 SHIELD GNDA NC Internal Ground Shield between channels. A Channel Ground. A and B grounds should be connected as close to the device as possible. No Connect. Pins 15 and 17 are internal test pins: it is recommended to connect them to GND Analog Input for A side ADC (nominally ± 0.5 V). Analog Input for A side ADC (nominally ± 1.0 V). Analog Input for A side ADC (nominally ± 2.0 V). Analog Negative Supply Voltage (nominally –5.0 V). For A side ADC. Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital positive supply voltage (nominally +3.3 V) for A side ADC. Digital Outputs for ADC B. D0 (LSB). B Channel Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally +3.3 V) for B side ADC. Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Analog Input for B side ADC (nominally ± 0.5 V). Analog Input for B side ADC (nominally ± 1.0 V). Analog Input for B side ADC (nominally ± 2.0 V). Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC. Analog Negative Supply Voltage (nominally –5.0 V). For B side ADC. AINA1 AINA2 AINA3 AVEE AVCC D0A–D11A ENCODEA ENCODEA DVCC D0B–D11B GNDB DVCC ENCODEB ENCODEB AINB1 AINB2 AINB3 AVCC AVEE 9 GNDA GNDA NC AVEE AVCC NC NC (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA 8 7 6 5 4 3 2 GNDB GNDA AINA3 AINA2 AINA1 GNDA NC NC GNDA SHIELD GNDB AVEE AVCC GNDB AINB3 AINB2 AINB1 PIN CONFIGURATION 68-Lead Leaded Ceramic Chip Carrier 1 68 67 66 65 64 63 62 61 10 PIN 1 11 12 59 58 13 57 14 56 15 55 16 AD10265 17 TOP VIEW (Not to Scale) 18 19 54 53 52 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 GNDA ENCODEA ENCODEA DVCC D9A D10A (MSB) D11A NC NC (LSB) D0B D1B D2B D3B D4B D5B D6B GNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC = NO CONNECT REV. 0 60 –5– GNDB GNDB GNDB NC NC NC GNDB GNDB ENCODEB ENCODEB DVCC D11B (MSB) D10B D9B D8B D7B GNDB AD10265 Output Propagation Delay DEFINITION OF SPECIFICATIONS Analog Bandwidth The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels. The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Signal-to-Noise-and-Distortion (SINAD) The sample-to-sample variation in aperture delay. The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Differential Nonlinearity Signal-to-Noise Ratio (without Harmonics) The deviation of any code from an ideal 1 LSB step. The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Aperture Uncertainty (Jitter) Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic “1” state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale). Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. –6– REV. 0 AD10265 N N+2 N+1 N+3 N+4 N+5 ENC TTL CLOCK f 10MHz AIN 1/2 AD10265 SHOWN AINA3 tA D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ENC AINA2 AINA1 ENCODE tOD DIGITAL OUTPUTS N–2 N–1 N N+1 NOTE: ALL 65V SUPPLY PINS BYPASSED TO GND WITH A 0.1mF CAPACITOR N+2 Figure 1. Timing Diagram Figure 2. Equivalent Burn-In Circuit EQUIVALENT CIRCUITS DVCC AINA3 R4 200V CURRENT MIRROR AINA2 R3 100V AINA1 DVCC Figure 3. Analog Input Stage VREF D0 – D11 AVCC AVCC AVCC R1 17kV R1 17kV ENCODE ENCODE R2 8kV TIMING CIRCUITS CURRENT MIRROR R2 8kV Figure 4. Encode Inputs REV. 0 Figure 5. Digital Output Stage –7– AD10265–Typical Performance Characteristics 0 0 POWER RELATIVE TO FULL SCALE – dB –20 –30 –40 POWER RELATIVE TO FULL SCALE – dB ENCODE = 65.0MSPS AIN = 1.24MHz AIN = –1.004dBFS SNR = 64.88dB SFDR = 78.81dBc –10 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –10 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 1024 2048 3072 4096 5120 FREQUENCY – MHz 6144 7168 –140 8192 0 Figure 6. Single Tone @ 1.24 MHz 1024 3072 4096 5120 FREQUENCY – MHz 6144 7168 8192 66 –10 ENCODE = 65.0MSPS AIN = 17MHz AIN = –1dBFS SNR = 63.83dB SFDR = 78.22dBc –20 –30 –40 ENCODE = 65MHz 65 +258C 64 SNR – dB –50 –60 –70 –80 –90 63 +1258C 62 –100 –558C –110 61 –120 –130 –140 0 1024 2048 3072 4096 5120 FREQUENCY – MHz 6144 7168 60 1.24 8192 17 ANALOG FREQUENCY – MHz Figure 7. Single Tone @ 17 MHz 32 Figure 10. SNR vs. AIN 90 0 –10 ENCODE = 65.0MSPS AIN = 32MHz AIN = –1.021dBFS SNR = 64.11dB SFDR = 78.14dBc –20 –30 –40 80 70 SFDR – dBFS SFDR – dBc 60 –50 SFDR – dBc POWER RELATIVE TO FULL SCALE – dB 2048 Figure 9. Two-Tone FFT @ 17 MHz/18 MHz 0 POWER RELATIVE TO FULL SCALE – dB ENCODE = 65.0MSPS AIN = 17MHz AND 18MHz AIN = –7.067dBFS SFDR = 78dBc –20 –60 –70 –80 –90 50 SFDR – 75dB 40 30 –100 AIN = 17MHz ENCODE RATE 65MHz 20 –110 –120 10 –130 –140 0 1024 2048 3072 4096 5120 FREQUENCY – MHz 6144 7168 0 –70.18 8192 Figure 8. Single Tone @ 32 MHz –60.09 –50.18 –39.92 –30.07 –20.02 FUNDAMENTAL – dBFS –10.1 –1.099 Figure 11. Single Tone SFDR (AIN @ 17 MHz) vs. Power Level –8– REV. 0 90 0 80 –1 SFDR – dBc –2 70 –3 60 LEVEL – dBFS SNR, WORST SPUR – dB, dBc AD10265 SNR – dB 50 40 30 –6 ENCODE RATE = 65MHz ROOM TEMPERATURE –8 –9 10 17 32 37 65 80 ANALOG INPUT FREQUENCY – MHz –10 0.02 0.04 0.06 0.08 0.1 0.3 0.5 20 60 FREQUENCY – MHz 100 Figure 12. SNR/Harmonics to AIN > Nyquist MSPS REV. 0 –5 –7 ENCODE FREQUENCY = 65MHz AIN = –1dBFS 20 0 1.24 –4 90 120 140 160 Figure 13. Gain Flatness vs. Input Frequency –9– AD10265 THEORY OF OPERATION Refer to the Functional Block Diagram. The AD10265 employs three monolithic ADI components per channel (AD9631 AD9632 and AD6640), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit analog-to-digital converter. ENCODE SOURCE V1 0.01mF ENCODE +5V R1 R2 Rx AD10265 The input signal is first passed through a precision laser-trimmed resistor divider, allowing the user to externally select operation with a full-scale signal of ± 0.5 V, ± 1.0 V, or ± 2.0 V by choosing the proper input terminal for the application. Since the AD6640 implements a true differential analog input, the AD9631/AD9632 have been configured to provide a differential input for the AD6640 ADC through ac-coupling. The ac signal gain of the AD9631/AD9632 can be trimmed to provide a constant differential input to the AD6640. This allows the converter to be used in multiple system applications without the need for external gain circuit normally requiring trim. The AD9631/AD9632 were chosen for their superior ac performance and input drive capabilities, which have limited the ability of many amplifiers to drive high performance ADCs. As new amplifiers are developed, pin-compatible improvements are planned to incorporate the latest operational amplifier technology. APPLYING THE AD10265 Encoding the AD10265 Best performance is obtained by driving the encode pins differentially. However, the AD10265 is also designed to interface with TTL and CMOS logic families. The source used to drive the ENCODE pin(s) must be clean and free from jitter. Sources with excessive jitter will limit SNR and overall performance. Figure 15. Lower Threshold for Encode V1 = 5R2 R1Rx to raise logic threshold. R2 + R1+ Rx AVCC Rx +5V ENCODE SOURCE ENCODE ENCODE V1 R1 R2 0.01mF AD10265 Figure 16. Raise Logic Threshold for Encode While the single-ended encode will work well for many applications, driving the encode differentially will provide increased performance. Depending on circuit layout and system noise, a 1 dB to 3 dB improvement in SNR can be realized. It is recommended that differential TTL logic be used, however, because most TTL families that support complementary outputs are not delay or slew rate matched. Instead, it is recommended that the encode signal be ac-coupled into the ENCODE and ENCODE pins. The simplest option is shown below. The low jitter TTL signal is coupled with a limiting resistor, typically 100 Ω, to the primary side of an RF transformer (these transformers are inexpensive and readily available; part number in Figure 17 is from MiniCircuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Since both encode inputs are self-biased, no additional components are required. AD10265 TTL OR CMOS SOURCE ENCODE ENCODE ENCODE 0.01mF Figure 14. Single-Ended TTL/CMOS Encode 100V The AD10265 encode inputs are connected to a differential input stage (see Figure 4 under Equivalent Circuits). With no input connected to either ENCODE pin, the voltage divider biases the inputs to 1.6 volts. For TTL or CMOS usage, the encode source should be connected to ENCODE. ENCODE should be decoupled using a low inductance or microwave chip capacitor to ground. TTL ENCODE AD10265 ENCODE Figure 17. TTL Source—Differential Encode If a logic threshold other than the nominal +1.6 V is required, the following equations show how to use an external resistor, Rx, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ, R2 = 8 kΩ). V1 = T1–1T A clean sine wave may be substituted for a TTL clock. In this case, the matching network is shown below. Select a transformer ratio to match source and load impedances. The input impedance of the AD10265 encode is approximately 11 kΩ differentially. Therefore “R,” shown in Figure 18, may be any value that is convenient for available drive power. 5R2Rx to lower logic threshold. R1R2 + R1Rx + R2Rx SINE SOURCE T1–1T ENCODE AD10265 R ENCODE Figure 18. Sine Source—Differential Encode –10– REV. 0 AD10265 If a low jitter ECL clock is available, another option is to accouple a differential ECL signal to the encode input pins as shown below. The capacitors shown here should be chip capacitors, but do not need to be of the low inductance variety. 0.1mF ENCODE ECL GATE AD10265 0.1mF ENCODE 510V GROUNDING AND DECOUPLING Analog and Digital Grounding Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 510V 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. –VS Figure 19. Differential ECL for Encode As a final alternative, the ECL gate may be replaced by an ECL comparator. The input to the comparator could then be a logic signal or a sine signal. AD96687 (1/2) 0.1mF ENCODE AD10265 0.1mF 50V ENCODE 510V 510V –VS Figure 20. ECL Comparator for Encode These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling to the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. The AD10265 does not distinguish between analog and digital ground pins as the AD10265 should always be treated as an analog component. All ground pins should be connected together directly under the AD10265. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path and manage the power and ground currents. The ground plane should be removed from the area near the input pins to reduce stray capacitance. USING THE FLEXIBLE INPUT The AD10265 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. While the standard inputs are ± 0.5 V, ± 1.0 V and ± 2.0 V, the user can select the input impedance of the AD10265 on any input by using the other inputs as alternate locations for GND or an external resistor. The following chart summarizes the impedance options available at each input location: AIN1 = 100 Ω when AIN2 and AIN3 Are Open. AIN1 = 75 Ω when AIN3 Is Shorted to GND. AIN1 = 50 Ω when AIN2 Is Shorted to GND. AIN2 = 200 Ω when AIN3 Is Open. AIN2 = 100 Ω when AIN3 Is Shorted to GND. AIN2 = 75 Ω when AIN2 to AIN3 Has an External Resistor of AIN2 = 300 Ω, with AIN 3 Shorted to GND. AIN2 = 50 Ω when AIN2 to AIN3 Has an External Resistor of AIN2 = 100 Ω, with AIN3 Shorted to GND. AIN3 = 400 Ω. AIN3 = 100 Ω when AIN3 Has an External Resistor of 133 Ω to GND. AIN3 = 75 Ω when AIN3 Has an External Resistor of 92 Ω to GND. AIN3 = 50 Ω when AIN3 Has an External Resistor of 57 Ω to GND. REV. 0 LAYOUT INFORMATION The schematic of the evaluation board (Figure 21) represents a typical implementation of the AD10265. The pinout of the AD10265 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the AD6640 ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. –11– AD10265 U6 74LCX574 R37 2kV D8A GND +5VAA U3:A R38 348V +5VAA C2 0.1mF 1 3 74AS00 1 T1 6 5 4 3 C29 0.1mF ENCAB SMA J10 –5VAA 3 4 ENCA D0A D1A D2A D3A D4A D5A D6A D7A U5:B 5 6 BUFLATB 11 1 C8 0.1mF R43 100V C30 0.1mF 1 T2 6 5 4 3 1:1 GND D7B ENCBB D8B D9B D10B D11B GND GND ENCB –5VAB J14 –5VAB –5VAB GND J12 C23 0.1mF +5VAA GND D0A D1A D2A D3A D4A D5A D6A D7A D8A GND +5VAB GND AINB3 AINB2 AINB1 GND D0B D1B D2B D3B D4B D5B D6B GND 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 GNDA A IN A3 A IN A2 A IN A1 GNDA NCA NCA GNDA SHIELD GNDB –5VAB +5VAB GNDB A IN B3 A IN B2 A IN B1 GNDB 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GNDA GNDA NCA –5VAA +5VAA TESTA NCA D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA U1 AD10265 GNDB GNDB GNDB TESTB NCB NCB GNDB GNDB ENCBB ENCB +3.3VDB D11B D10B D9B D8B D7B GNDB 27 GNDA 28 ENCAB 29 ENCA 30 +3.3VDA 31 D9A 32 D10A 33 D11A 34 NCB 35 NCB 36 D0B 37 D1B 38 D2B 39 D3B 40 D4B 41 D5B 42 D6B 43 GNDB –5VAA GND GND GND GND GND GND AINA2 AINA2 AINA1 GND J16 GND GND ENCAB ENCA +3.3VDA D9A D10A D11A GND GND D0B D1B D2B D3B D4B D5B D6B GND J11 +5VAA –5VAA C22 0.1mF GND +5VAA E2 –5VAB J15 GND +5VAB 9 8 7 6 5 4 3 2 11 1 BUFLATB E1 +5VAB 9 8 7 6 5 4 3 2 R16 348V R17 348V B10A R18 348V B11A R19 348V B0A R20 348V BUFLATA B1A B3A B2A B1A B0A GND GND GND GND GND R21 348V 12 13 14 15 16 17 18 19 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 1 2 3 4 5 6 7 8 9 10 11 12 1 13 14 15 16 17 18 19 20 +3.3VDA B11A B10A B9A B8A B7A B6A B5A B4A B9A CLK OC 8D 7D 6D 5D 4D 3D 2D 1D H40DM J1 B8A B2A R22 348V B3A R23 348V B4A R24 348V 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B5A 74AS00 74AS00 14 U4 VCC 8 OUT VEE 7 K1115 R6 50V J13 –5VAA 1 2 U5:A R15 348V 12 8Q 13 7Q 14 6Q 15 5Q 16 4Q 17 3Q 18 2Q 19 1Q U7 74LCX574 R41 2kV R42 348V C7 0.1mF 11 1 BUFLATA 1:1 +5VAB BUFLATA 74AS00 R39 100V R5 50V +5VAB GND GND GND D9A D10A D11A C1 0.1mF 7 K1115 SMA J9 6 5 2 14 U2 VCC 8 OUT VEE U3:B 4 9 8D 8 7D 7 6D 6 5D 5 4D 4 3D 3 2D 2 1D 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 GND GND GND CLK OC R13 348V U8 74LCX574 R14 348V 8D 7D 6D 5D 4D 3D 2D 1D B7A H40DM J2 R26 348V 12 8Q 13 7Q 14 6Q 15 5Q 16 4Q 17 3Q 18 2Q 19 1Q B7B B8B R28 348V B9B R29 348V B10B R30 348V U9 74LCX574 R31 348V 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q B11B BUFLATB B3B B2B B1B B0B GND GND GND GND GND B0B 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 +3.3VDA B11B B10B B9B B8B B7B B6B B5B B4B R27 348V CLK OC 9 8D 8 7D 7 6D 6 5D 5 4D 4 3D 3 2D 2 1D 11 1 B6A R32 348V B1B R33 348V B2B R34 348V B3B R35 348V 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 13 14 15 16 17 18 19 20 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B4B CLK OC R36 348V B5B R25 348V GND GND ENCBB ENCB +3.3VDB D11B D10B D9B D8B D7B GND B6B 12 U3:D 11 13 74AS00 SMA J3 SMA J4 AINA1 9 U3:C 74AS00 SMA J5 AINA2 +3.3VDA 9 10 8 10 U5:C 8 74AS00 SMA J6 AINA3 12 U5:D 74AS00 SMA J7 AINB1 11 13 SMA J8 AINB2 AINB3 +3.3VDB +5VAA C25 + C9 10mF 0.1mF C10 0.1mF C11 0.1mF C12 0.1mF C26 + C16 10mF 0.1mF C17 0.1mF C18 0.1mF C19 0.1mF C20 0.1mF +5VAB C21 0.1mF Figure 21. Evaluation Board Schematic –12– REV. 0 AD10265 Power to the analog supply pins is connected via banana jacks. The analog supply powers the crystal oscillator, the associated components and amplifiers, and the analog section of the AD10265. The digital outputs of the AD10265 are powered via Pin 1 of either J1 or J2 found on the digital interface connector with +3.3 V. Contact the factory if additional layout or applications assistance is required. EVALUATION BOARD The AD10265 evaluation board (Figure 22) is designed to provide optimal performance for evaluation of the AD10265 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD10265. J2 +5VAB GND –5VAB U4 J10 ENCB J6 C16 AINB2 U8 J5 C17 AINB3 U9 U1 R R 25 R3 36 5 R 3 R R 33 4 R3 32 1 AINB1 R30 R29 8 R2 7 R2 R26 J8 C21 PIN 1 J3 AINA1 U6 J4 R1 8 R1 R1 7 6 R1 5 C23 U7 AINA2 J7 C10 J9 AINA3 R14 +5VAA GND R13 R24 R23 R22 R21 R20 R19 ENCA –5VAA C2 GS01685 ( 2 ) AD10265 EVALUATION BOARD YW Figure 22. Evaluation Board Mechanical Layout REV. 0 –13– J1 AD10265 Figure 23. Top Layer –14– REV. 0 AD10265 Figure 24. Bottom Layer REV. 0 –15– AD10265 Figure 25. Power Plane Layer –16– REV. 0 AD10265 Figure 26. Ground Plane Layer REV. 0 –17– AD10265 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Leaded Ceramic Chip Carrier (Z-68A) 1.180 (29.97) SQ 0.950 (24.13) SQ 0.060 (1.52) 9 61 10 60 PIN 1 0.800 (20.32) TOP VIEW (PINS DOWN) 26 44 27 43 0.050 (1.27) 0.240 (6.096) –18– 0.018 (0.457) REV. 0