开兵也品是控制暴 TDA16846 元串串 1/J 卒阁我校正电路的原理和雇用
开关电源控制器 TDA16846
无源功率因数校正电路的原理和应用
摘
中山大学
冯镇业
珠海市社会保险局
李莉莎
要:本文介绍 SIEMENS 公司提出的开关电源集成控制器 TDA16846 元源功率因数校正 (PFC) 电
路原理及其在电视机开关电源中的应用 O 功率因数的改善是基于一个特殊的由电感，电容及二极管
组成的充电泵电路，该电路在功率管的高压端兼起吸收缓冲作用，因此它具有输入谐波电流分量小，
PF 值高以及 EMI 小、电路简单、成本低和可靠性高等优点。这为电视机厂家提供了一个高效价廉的
解决电源谐波问题的新方案。
关键词:开关电源
功率因数校正
一、引言
二、无源 PFC 电路工作原理介绍
众所周知，目前电视机和大部分通用电器都广
图 1 示出一个不含 PFC 的标准型电源电路的输
泛地从交流电网中提取电能经整流后变成直流电供
入电压 Vm 和输入电流 ι 波形儿只在 Vm 为正最大
全机使用， AC 电源经桥式整流后常接一个滤波平整
和负最大的一小段时间内流通，在这些时间以外， ι
电容。由于该电容的存在，使整流臂的导通时间小于
为零。这是因为此时的正弦电压输入值小于泸波电容
半个周期，因而做成输入电源电压是正弦形，而输入
上的电压，导致整流二极管不导通的缘故。
电流却是正负交替的脉冲形。后者导致大量电流谐波
特别是三次谐波的产生，这既构成对电网效能的干扰
和损害，又降低了本机功率因数，为此，我国跟欧美各
国一样，已于去年 12 月 1 日起正式实施限制功耗大
于 75W 的通用电器产品输入谐波电流的新规定。面
一一告~t
对这种新情况，当前各电器厂家都必须考虑更新产
品中的电源设备，尤其是对 25 英寸以上的彩色电视
机，过去国内汇品绝大部分都没有安装 PFC 电路，
其 PF 值一般在 0.55 - 0.65 之间，输入电流谐波分量·
往往超出国家限定的标准，因此改进电源电路，增加
PFC 功能以便降低电视机的输入电流谐披分量是各
厂家的当务之急。
标准型电源中的输入电压和电流
为了在图 1 中获得一个形似 Imp 的电流，我们引
人充电泵的概念，即它的作用就是能够让输入电流
本文介绍由 SIEMENS 公司推出的与开关电惊集
从低压端流向高压端。图 2 示出一个简单的充电泵电
成控制器 TDA16846 配合使用的一个无源功率因数
路。图中电容 C 1 受直流电压 V1 充电，电容 C2 则受
校正 (PFC) 电路，该电路能将电源 PF 值提高到 0.9
直流电压民充电。
以上，与有惊 PFC 电路相比，它明显地具有结构简
充电泵电路是由二个二极管 D 1 和 D2 以及电容 C3
单，成本低，可靠性高，和 EMI 小等优点，因此对电视
扭成，电容 G 相对于 C 1 和 C2 都较小，从电压惊 V3
机厂家来说，不失为一个有效的解决电师、谐波问题
进来的脉冲通过电容 G 后加到 Dl 和 D 2 的连结点
的可行方案。
上。如果脉冲民的幅度大于差值 (V2
8
\\
图 1
V1 小于且，在 V1 和机之间的
-
Vl) ， 那么就有
{<tl手元~(非启用 hooo 年 5 月，第 2 卷
喝乒发应用如
第5期
Vcc
工
工 C1
图 2
号E
C2
充电泵电路
可能让电流 11 从较低的 Vl 流向较高的民。在每一周
期内通过电容 ι 上的电荷 Q3 为:
。3 =
图 4
C3 X (V3 - ( V, - Vl))
= C3 X ( V3 +
导通后从 Vm ， 产生大幅度电流脉冲对电容 C 充电。图
V1 - V2)
假设民的脉冲频率为元，则充电泵的电流 11 为 :
11 = C3
X
fi
X (
PFC 充电泵电路
2 中的脉冲电压源、 V3 现在由开关管漏极电压瓦代
替。由于充电泵电路不仅具有 PFC 功能而且兼有缓
V3 - ~包 + V1 )
如果电压 V1 不是 DC 电压而是一个己整流的脉动电
冲器功能，因此图 3 中的 RCD 缓冲电路不再需要。
压，并且如果民=见，则由上式可知电流 L 会是一
这个充电泵可以阻止开关变压器由充磁突变为
个正弦波。图 3 示出基于 TDA16846 的反激式标准型
消磁的过程中，由于 ι 的不连续而对电视机图象产
开关电源电路，它含有二个常规的 RCD 缓冲电路用
生的低频干扰。因为当开关管截止，变压器的消磁过
以消除开关管 T 漏极上的电压过冲。其实这个 RCD
程开始时，二极管 D 导通， ι 可通过 ιCJ彭成一个
缓冲电路完全可以用在图 4 中示出的一个由电感 ι
LC 振荡回路，保持了 Lp 流通瞬时的连续性，这使得
电容 C 及二极管 D 组成的充电泵电路所代替。这个
所生成的寄生干扰信号在频率和幅值上都大为下降，
充电泵电路是插入在桥式整流器 (BR) ，初级电容 Cp
而且由于没有电阻成分参与，所以原则上不会损失能
的正极和开关晶体管 T 漏极之间。现在 BR 代替了图
量.相比于原有的 RCD 缓冲器，其电源的转换效率
2 中的二极管队，电感 L 的放人是为了避免功率管 T
将有所提高。图 5 从工作波形上详细地描述了 PFC 充
电泵电路的原理和功能。假定输入 AC 电压为 230V ，
Vcc
在 to 时刻开关管 T 受 TDA16846 的控制而导通。漏
极电压民由约 600V 跳降到零伏。由于初级电感 Lp
的存在，初级电流 Lp 开始直线性上升。氏的跳变同时
通过电容 C 传送到 L 和 D 之间的连接点上(见图
4) ，所以电压 Vp 从 400V 降到近似 -200V 。由于负的
R
告E
Vp 电压，流过扼流圈 L 上的电流 h 会逐步上升。并
向电容 C 充电，这使 Vp 在 to ， tl 期间有类似形状的
少许爬升。这时二极管 D 是截止的， Id =0 。
当开关变压器和扼流圈 L 的充磁阶段在 t1 时刻
完成之后，开关管 T 受 TDA16846 的控制转为截止，
漏极电流 1， =0 。电压 V， 及 Vp 将急剧上升直到 Vp =
Vcp (400V) 。此后只改为缓慢的爬升，而怀则保持在
Vcp 电平上不变。与此同时电流 h( 它早先是向电容
图 3
RCD 缓冲电路
器充电的)改为经过二极管 D 流进电容 Cp 中。这使
9
开兵也爆栓剑导民 TDA16846 元舔功卒因我校且也路的尿理和应用
蕴含在 L 中的能量转移到 Cp 中。利用这个原理，就
变为 0 ，而漏极电流且会有 2 个极大值。这是因为在
使输入电流从较低的 Vm ， 值流向电容 Cp 上较高的
t3
Vcp 值。
t4 期间 ， 1， 为 L 和 - Ic 之和，而 t4 以后则且完全由
b 独自提供。在此种波形中， ι 不再周期性地返回到
从 tl 开始，由于二极管 D 的导通，由 Lp 与 C 就
形成一个回路，初级电流 b 将流过 Lp ，
零值。
C 和二极管
采用 PFC 充电泵电路的一大优点就是它的简单
而在 t2 时刻，次级二极管开始导
性和容易设计。事实上选择合适的 L， C 参数组合就
通，变压器开始向次级绕组释放磁能。在 t2 t3 的释放
能很快地把一个普通开关电漉转换成 PFC 型。对于
磁能阶段，初级电流 b 很快下降为 0 ，而扼流圈 L 的
25 -34 英寸 CTV 一般选择 L = 1 - 2mH /2. 2A C =
电流 ι 则逐步下降。但电压 Vp 仍保持在 Vcp 值上。
lO nF 1600V , D 可取快速恢复的耐高压 (600V 15A)
从图 5 可知，当开关管的导通时间 ton 越长，则 ι 峰
二极管，例如 STTA506D 或 FUF5406 ， FUF5407 等都
值越大，而 ton 是随着次级负载的加大以及随着输入
可以。在试验中可应用示波器监测 AC 电掘的输入电
电网电压的减少而加大的。亦即流入 PFC 充电泵电
流波形，并调节电容 C 数值，以得到最佳的输入电流
路的电流也会相应加大。但这不必担心扼流圈 L 的
Imp 波形(见图 1)0
磁心会受饱和。因为 h 的最大值总是受限制于电容
三、应用实例
D， 一直到时间 t2 。
C 上的充电电流 Ic 。图 5 同时画出 PFC 充电泵电路
图 6 给出了一个含 PFC 充电泵的 34 英寸彩色电
的下一个周期波形。此种波形通常会发生在输入 AC
视机开关电源应用电路。该电掘由以下部分组成，即:
电压为最大值时刻。此时 Vp 在导通期 t3 t5 内上升。但
1)共模电源滤波器及桥式整流电路; 2) 由 Lθ05 ， C93 1 ,
在中途 t4 处己达到固定值 Vcp 。所以 L 在时刻 t4 上
D 910 组成 PFC 电路; 3) TDA16846 开关电源控制器;
4) 600V 112A 的 MOSFET BUZ334; 5) 次级输出及光
祸反馈控制电路。开关电源工作机理以及 TDA16846
的功能介绍请参阅 [3] 。这里要强调的是为了抑制开关
电源的噪声，除在电源的输入端接入二个共模滤波器
乌问 ~02 及中心抽头落‘冷'地的二个电容 C904 、 C905
以外，我们还在初级电感 b 与 BUZ334 漏极之间接
入一只快速反向恢复二极管 D 908 ， 用以防止漏极电压
h 的正上冲通过 Lp 搞合到次级各输出绕组中。另外
··EBEE
P
i矗
FI
为了旁路一部分由漏极经 C931 ， ~05 漏出至电网的高
频脉冲分量以及减少纹波。我们接入了 C906 (220PF)
和 R93 2 (1. 8k!1/2W) ，经过这样处理后。用示波器监
测，输入波形明显改善，谐波分量大为减少。同时电视
机画面的干扰亮点变小，图象质量有所提高。实验还
表明，该 PFC 电路对 21 英寸 -25 英寸 CTV 中小功
t
且‘，
EEt
l
y--d
参考文献
[1] GB17625. 1 :""1998<低压电气及电子设备发生的谐波电流
限制}.国家技禾监督局 1998 - 12 - 14 发布 .1999-12
FI
C
h···EEE-
-01 实施
t7
to
图 5
10
率电源特别适合，其谐波失真改善效果更为明显。
PFC 充电泵电路的电压和电流啤形
[2] TDA16846 Application note. Siemens AG. 18.03.99.
[3 ]冯镇业.<利用 TDA16846 设计一个廉价高效能的 34" 彩
色电视机开关电源、}， ~电子元器件应用}， 2000 年第 4 期.
ICs for Consumer Electronics
Controller for Switch Mode Power Supplies Supporting Low Power
Standby and Power Factor Correction
TDA 16846/TDA 16847
Data Sheet 2000-01-14
TDA 16846/TDA 16847
Revision History:
Current Version: 2000-01-14
Previous Version: 1999-07-05
Page
Page
(in previous (in current
Version)
Version)
Subjects (major changes since last revision)
3
P-DSO package added
3, 28
Edition 01.00
Published by Infineon Technologies AG i. Gr.,
St.-Martin-Strasse 53
D-81541 München
© Infineon Technologies AG 2000
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts stated herein.
Infineon Technologiesis an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
TDA 16846
TDA 16847
Controller for Switch Mode Power Supplies
Supporting Low Power Standby and Power
Factor Correction
Preliminary Data
Bipolar IC
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Line Current Consumption with PFC
P-DIP-14-3
Low Power Consumption
Stable and Adjustable Standby Frequency
Very Low Start-up Current
Soft-Start for Quiet Start-up
Free usable Fault Comparators
Synchronization and Fixed Frequency Facility
P-DSO-14-3
Over- and Undervoltage Lockout
Switch Off at Mains Undervoltage
Temporary high power circuit (only TDA 16847)
Mains Voltage Dependent Fold Back Point Correction
Continuous Frequency Reduction with Decreasing Load
Adjustable and Voltage Dependent Ringing Suppression Time
Type
Ordering Code
Package
TDA 16846
Q67000-A9377
P-DIP-14-3
TDA 16847
Q67000-A9378
P-DIP-14-3
TDA 16846G
Q67006-A9430
P-DSO-14-3
TDA 16847G
Q67006-A9412
P-DSO-14-3
1.2
Description
The TDA 16846 is optimized to control free running or fixed frequency flyback converters
with or without Power Factor Correction (Current Pump). To provide low power
consumption at light loads, this device reduces the switching frequency continuously
with load, towards an adjustable minimum (e. g. 20 kHz in standby mode). Additionally,
the start up current is very low. To avoid switching stresses of the power devices, the
power transistor is always switched on at minimum voltage. A special circuit is
implemented to avoid jitter. The device has several protection functions: VCC over- and
undervoltage, mains undervoltage, current limiting and 2 free usable fault comparators.
Regulation can be done by using the internal error amplifier or an opto coupler feedback
(additional input). The output driver is ideally suited for driving a power MOSFET, but it
can also be used for a bipolar transistor. Fixed frequency and synchronized operation
are also possible.
Data Sheet
3
2000-01-14
TDA 16846
TDA 16847
The TDA 16846 is suited for TV-, VCR- sets and SAT receivers. It also can be good used
in PC monitors.
The TDA 16847 is identical with TDA 16846 but has an additional power measurement
output (pin 8) which can be used for a Temporary High Power Circuit.
OTC
1
14
VCC
PCS
2
13
OUT
RZI
3
12
GND
SRC
4
11
PVC
OCI
5
10
FC1
FC2
6
9
REF
SYN
7
8
N.C./PMO
AEP02647
Figure 1
1.3
Pin Configuration (top view)
Pin Definitions and Functions
Pin
Symbol
Function
1
OTC
Off Time Circuit
2
PCS
Primary Current Simulation
3
RZI
Regulation and Zero Crossing Input
4
SRC
Soft-Start and Regulation Capacitor
5
OCI
Opto Coupler Input
6
FC2
Fault Comparator 2
7
SYN
Synchronization Input
8
N.C./PMO
Not Connected (TDA 16846)/PMO (TDA 16847)
9
REF
Reference Voltage and Current
10
FC1
Fault Comparator 1
11
PVC
Primary Voltage Check
12
GND
Ground
13
OUT
Output
14
VCC
Supply Voltage
Data Sheet
4
2000-01-14
TDA 16846
TDA 16847
1.4
Short Description of the Pin Functions
Pin
Function
1
A parallel RC-circuit between this pin and ground determines the ringing
suppression time and the standby-frequency.
2
A capacitor between this pin and ground and a resistor between this pin and
the positive terminal of the primary elcap quantifies the max. possible output
power of the SMPS.
3
This is the input of the error amplifier and the zero crossing input. The output
of a voltage divider between the control winding and ground is connected to
this input. If the pulses at pin 3 exceed a 5 V threshold, the control voltage at
pin 4 is lowered.
4
This is the pin for the control voltage. A capacitor has to be connected
between this pin and ground. The value of this capacitor determines the
duration of the softstart and the speed of the control.
5
If an opto coupler for the control is used, it’s output has to be connected
between this pin and ground. The voltage divider at pin 3 has then to be
changed, so that the pulses at pin 3 are below 5 V.
6
Fault comparator 2: If a voltage > 1.2 V is applied to this pin, the SMPS stops.
7
If fixed frequency mode is wanted, a parallel RC circuit has to be connected
between this pin and ground. The RC-value determines the frequency. If
synchronized mode is wanted, sync pulses have to be fed into this pin.
8
Not connected (TDA 16846). / This is the power measurement output of the
Temporary High Power Circuit. A capacitor and a RC-circuit has to be
connected between this pin and ground (TDA 16847).
9
Output for reference voltage (5 V). With a resistor between this pin and ground
the fault comparator 2 (pin 6) is enabled.
10
Fault comparator 1: If a voltage > 1 V is applied to this pin, the SMPS stops.
11
This is the input of the primary voltage check. The voltage at the anode of the
primary elcap has to be fed to this pin via a voltage divider. If the voltage of
this pin falls below 1 V, the SMPS is switched off. A second function of this pin
is the primary voltage dependent fold back point correction (only active in free
running mode).
12
Common ground.
13
Output signal. This pin has to be connected across a serial resistor with the
gate of the power transistor.
14
Connection for supply voltage and startup capacitor. After startup the supply
voltage is produced by the control winding of the transformer and rectified by
an external diode.
Data Sheet
5
2000-01-14
TDA 16846
TDA 16847
1.5
Block Diagrams
PVC
KSY
R7
+
-
5V
G4
4
+
-
1
R2
ErrorFlipflop
S
R
Buffer for
Control Voltage
6
REF
N.C.
FC2
FC2 1.2 V
Q
+
+
-
5
R1
&
On Time
Comparator
20 k Ω
G2
+
-
PCS
+
OCI
8
D2
+
-
D3
SRC
9
ED2
Error
Amplifier
3
VCC
1
RSTC/RSTF
5V
3.5 V
RZI
3.5 V
G1
-
CS1
1V
1.5 V
-
1
D5
+
-
R3
75 k Ω
15 k Ω
Control Voltage
Off Time
Limit Comparator
2V
+
OTC
Primary
Voltage
Check
PVA
R6
30 k Ω
R8
11
Fold Back Point Correction
R 6 x 1/3
+
-
SYN
R4
D4
7
2 5V
On Time
Flipflop
G3
S
&
R
I1
Q
Output
Driver
13
OUT
ED1
Zero Crossing
Signal
1.5 V
VCC 14
GND
12
16 V
< 25 mV
Supply
Voltage
Comparator
Overvoltage
Comparator
+
-
FC1
+
-
D1
Startup
Diode
1V
+
-
15/8 V
10
1)
FC1
The input with the lower voltage becomes operative
Figure 2
Data Sheet
AEB02648
TDA 16846
6
2000-01-14
TDA 16846
TDA 16847
PVC
R4
D4
7
KSY
R7
+
-
5V
R2
ErrorFlipflop
S
R
Buffer for
Control Voltage 1)
G2
+
-
2 5V
FC2 1.2 V
I1
ED1
Zero
Crossing
Signal
1.5 V
D1
Startup
Diode
VCC 14
16 V
On Time
Flipflop
G3
S
&
R
S1
GND
FC2
Q
&
On Time
Comparator
20 k Ω
12
6
PMO
+
+
-
5
R1
PCS
+
-
1
REF
Q
Output
Driver
13
OUT
Discharge Time
Flipflop
S
< 25 mV
R
Q
FC1
Overvoltage
Comparator
+
-
Supply Voltage
Comparator
+
-
OCI
8
G4
D2
+
-
4
9
S2
ED2
Error
Amplifier
3
D3
SRC
+
RZI
1
RSTC/RSTF
5V
VCC
3.5 V
G1
+
-
CS1
3.5 V
-
OTC
1V
1.5 V
75 k Ω
15 k Ω
Control Voltage
Off Time
Limit Comparator
1
D5
+
-
R3
2V
Primary
Voltage
Check
PVA
R6
30 k Ω
R8
11
Fold Back Point Correction
R 6 x 1/3
+
-
SYN
1V
+
-
15/8 V
10
1)
FC1
The input with the lower voltage becomes operative
Figure 3
Data Sheet
AEB02737
TDA 16847
7
2000-01-14
TDA 16846
TDA 16847
2
Functional Description
Start Up Behaviour (Pin 14)
When power is applied to the chip and the voltage V14 at Pin 14 (VCC) is less than the
upper threshold (VON) of the Supply Voltage Comparator (SVC), input current I14 will be
less than 100 µA. The chip is not active and driver output (Pin 13) and control output
(Pin 4) will be actively held low. When V14 exceeds the upper SVC threshold (VON) the
chip starts working and I14 increases. When V14 falls below the lower SVC threshold
(VOFF) the chip starts again at his initial condition. Figure 4 shows the start-up circuit and
Figure 5 shows the voltage V14 during start up. Charging of C14 is done by resistor R2 of
the “Primary Current Simulation” (see later) and the internal diode D1, so no additional
start up resistor is needed. The capacitor C14 delivers the supply current until the
auxiliary winding of the transformer supplies the chip with current through the external
diode D14.
D14
C14
VCC
14
SVC
TR
D1
C2
PCS 2
R2
TDA 16846
V Out
Cp
AES02649
Figure 4
Data Sheet
Startup Circuit
8
2000-01-14
TDA 16846
TDA 16847
Vmax
V14 VOn
VOff
Startup
Operation
t
AED02650
Figure 5
Startup Voltage Diagram
Primary Current Simulation PCS (Pin 2) / Current Limiting
A voltage proportional to the current of the power transistor is generated at Pin 2 by the
RC-combination R2, C2 (Figure 4). The voltage at Pin 2 is forced to 1.5 V when the
power transistor is switched off and during its switch on time C2 is charged by R2 from
the rectified mains. The relation of V2 and the current in the power transistor (Iprimary) is
:
V 2 = 1,5 V +
L primary × I primary
-------------------------------R2 × C2
Lprimary: Primary inductance of the transformer
The voltage V2 is applied to one input of the On Time Comparator ONTC (see Figure 2).
The other input is the control voltage. If V2 exceeds the control voltage, the driver
switches off (current limiting). The maximum value of the control voltage is the internal
reference voltage 5 V, so the maximum current in the power transistor (IMprimary) is
:
3,5 V × R 2 × C 2
I Mprimary = -------------------------------------L primary
The control voltage can be reduced by either the Error Amplifier EA (current mode
regulation), or by an opto coupler at Pin 5 (regulation with opto coupler isolation) or by
the voltage V11 at Pin 11 (Fold Back Point Correction).
Data Sheet
9
2000-01-14
TDA 16846
TDA 16847
Fold Back Point Correction PVC (Pin 11)
V11 is deviated by a voltage divider from the rectified mains and reduces the limit of the
possible current maximum in the power transistor if the mains voltage increases. I.e. this
limit is independent of the mains (only active in free running mode). The maximum
current (IMprimary) depending on the voltage V11 at Pin 11 is
:
(4 V – V 11 ⁄ 3 ) × R 2 × C 2
I Mprimary = ----------------------------------------------------------L primary
Off-Time Circuit OTC (Pin 1)
Figure 6 shows the Off-Time Circuit which determines the load dependent frequency
course. When the driver switches off (Figure 7) the capacitor C1 is charged by current I1
(approx. 1 mA) until the capacitor’s voltage reaches 3.5 V. The charge time TC1 is
:
C 1 × 1,5 V
TC1 ≈ ------------------------1mA
For proper operation of the special internal anti jitter circuit, TC1 should have the same
value as the resonance time “TR” of the power circuit (Figure 7). After charging C1 up to
3.5 V the current source is disconnected and C1 is discharged by resistor R1. The voltage
V1 at Pin 1 is applied to the Off-Time Comparator (OFTC). The other input of OFTC is
the control voltage. The value of the control voltage at the input of OFTC is limited to a
minimum of 2 V (for stable frequency at very light load). The On-Time Flip Flop (ONTF)
is set, if the output of OFTC is high 1) and the voltage V3 at Pin 3 falls below 25 mV (zero
crossing signal is high). This ensures switching on of the power transistor at minimum
voltage. If no zero crossing signal is coming into pin 3, the power transistor is switched
on after an additional delay until V1 falls below 1.5 V (see Figure 6, OFTCD). As long as
V1 is higher than the limited control voltage, ONTF is disabled to suppress wrong zero
crossings of V3, due to parasitic oscillations from the transformer after switch-off. The
discharge time of C1 is a function of the control voltage.
1)
i.e. V1 is less than the limited control voltage.
.
Control Voltage
Output Power Off-time TD1
1.5 - 2 V
Low
Constant (TD1MAX.), const. frequency stand by
2 - 3.5 V
Medium
Decreasing
3.5 - 5 V
High
Free running, switch-on at first minimum
If the control voltage is below 2 V (at low output power) the “off-time” is maximum and
constant
TD1 max ≈ 0,47 × R 1 × C 1
Data Sheet
10
2000-01-14
TDA 16846
TDA 16847
External
Internal
From SYNC
Control Voltage
1.5 V
Limit
2V
+
-
OFTC
1
+
-
OTC 1
R1
From Error FF
OFTCD
&
ED3
C1
S
R
I1
Output
Driver
ONTF
Q
&
1
ED2
2V
RSTC
+
-
3.5 V
RZI 3
From ONTC
RSTC
S
Q
R
From UVLO
Ringing Suppression Time
ED1
Zero Crossing Signal
AES02651
Figure 6
Data Sheet
Off-Time-Circuit
11
2000-01-14
TDA 16846
TDA 16847
tR
Power
Trans.
VDrain
t C1
3.5 V
t D1max
V5
2V
V1
0V
V13
V3
t
AED02652
Figure 7
Pulse Diagram of Off-Time-Circuit
Figure 8 shows the converters switching frequency as a function of the output power.
f
Conventional
Free Running
TDA 16846
e.g. 20 kHz
POUT
AED02653
Figure 8
Data Sheet
Load Dependant Frequency Course
12
2000-01-14
TDA 16846
TDA 16847
Error Amplifier EA / Soft-Start (Pin 3, Pin 4)
Figure 9 shows the simplified Error Amplifier circuit. The positive input of the Error
Amplifier (EA) is the reference voltage 5 V. The negative input is the pulsed output
voltage from the auxiliary winding, divided by R31 and R32. The capacitor C3 is
dimensioned only for delaying zero crossings and smoothing the first spike after switchoff. Smoothing of the regulation voltage is done with the soft start capacitor C4 at Pin 4.
During start up C4 is charged with a current of approx. 2 µA (Soft Start). Figure 10 shows
the voltage diagrams of the Error Amplifier circuit.
External
TR
Internal
Error
Amplifier
C3
R 31
5V
RZI 3
R 32
C4
+
-
Down
VReg
SRC 4
AES02654
Figure 9
Error Amplifier
VRef
V3
Down
V4
t
AED02655
Figure 10
Data Sheet
Regulation Pulse Diagram
13
2000-01-14
TDA 16846
TDA 16847
Fixed Frequency and Synchronization Circuit SYN (Pin 7)
Figure 11 shows the Fixed Frequency and Synchronization Circuit. The circuit is
disabled when Pin 7 is not connected. With R7 and C7 at Pin 7 the circuit is working. C7
is charged fast by approx. 1 mA and discharged slowly by R7 (Figure 11). The power
transistor is switched on at beginning of the charge phase. The switching frequency is
(charge time ignored)
:
1,18
f ≈ -------------R7 × C7
When the oscillator circuit is working the Fold Back Point Correction is disabled (not
necessary in fixed frequency mode). “Switch on” is only possible when a “zero crossing”
has occurred at Pin 3, otherwise “switch-on” will be delayed (Figure 12).
External
Internal
OP1
SYN 7
+
-
R7
C7
30
kΩ
OP1OUT
15 k Ω
5V
75 k Ω
Logic
LO
OUT 13
RZI 3
Zero Crossing Signal
AES02656
Figure 11
Data Sheet
Synchronization and Fixed Frequency Circuit
14
2000-01-14
TDA 16846
TDA 16847
V
VTrans
3.6 V
V7
1.5 V
0.7 V
RZI(3)
t
AED02657
Figure 12
Pulse Diagram for Fixed Frequency Circuit
Synchronization mode is also possible. The synchronization frequency must be higher
than the oscillator frequency.
External
9
5 V 470 Ω
SYN
R7
39 k Ω
Internal
7
C7
1 nF
SFH 6136
AES02658
Figure 13
Ext. Synchronization Circuit
Data Sheet
15
2000-01-14
TDA 16846
TDA 16847
3
Protection Functions
The chip has several protection functions:
Current Limiting
See “Primary Current Simulation PCS (Pin 2) / Current Limiting” and “Fold Back Point
Correction PVC (Pin 11)”.
Over- and Undervoltage Lockout OV/SVC (Pin 14)
When V14 at Pin 14 exceeds 16 V, e. g. due to a fault in the regulation circuit, the Error
Flip Flop ERR is set and the output driver is shut-down. When V14 goes below the lower
SVC threshold, ERR is reset and the driver output (Pin 13) and the soft-start (Pin 4) are
shut down and actively held low.
Primary Voltage Check PVC (Pin 11)
When the voltage V11 at Pin 11 goes below 1 V the Error Flip Flop (ERR) is set. E.g. a
voltage divider from the rectified mains at Pin 11 prevents from high input currents at too
low input voltage.
Free Usable Fault Comparator FC1 (Pin 10)
When the voltage at Pin 10 exceeds 1 V, the Error Flip Flop (ERR) is set. This can be
used e. g. for mains overvoltage shutdown.
Free Usable Fault Comparator FC2 (Pin 6)
When the voltage at Pin 6 exceeds 1.2 V, the Error Flip Flop (ERR) is set. A resistor
between Pin 9 (REF) and ground is necessary to enable this fault comparator.
Voltage dependent Ringing Suppression Time
During start-up and short-circuit operation, the output voltage of the converter is low and
parasitic zero crossings are applied for a longer time at Pin 3. Therefore the Ringing
Suppression Time TC1 (see “Off-Time Circuit OTC (Pin 1)”) is made longer with
factor 2.5 at low output voltage. To ensure start-up of the circuit, the value of resistor R1
(Pin 1, Figure 6) must be higher than 20 kΩ.
Data Sheet
16
2000-01-14
TDA 16846
TDA 16847
4
Temporary High Power Circuit FC2, PMO, REF
(Pin 6, 8, 9, TDA 16847)
Figure 14 shows the Temporary High Power Circuit:
Internal
External
VCC
9 REF
CS2
R9
51 k Ω
I8
R8
8 PMO
Discharge Time
C8
S2
to Error Flipflop
1
C6
6 FC2
+
-
R6
10 M Ω
FC2
1.2 V
AEB02739
Figure 14
The Temporary High Power Circuit (THPC) consists of two parts:
First a power measurement circuit is implemented: The capacitor C8 at Pin 8 is charged
with a constant current I8 during the discharge time of the flyback transformer and
connected to ground the other time. So the average of the sawtooth voltage V8 at Pin 8
is proportional to the converters output power (at constant output voltages). The charge
current I8 for C8 is dimensioned by the resistor R9 at Pin 9:
I8 = 5 V/R9
Data Sheet
17
2000-01-14
TDA 16846
TDA 16847
Second a High Power Shutdown Comparator (FC2) is implemented: When the voltage
V6 at Pin 6 exceeds 1.2 V the Error Flip Flop (ERR) is set. The output voltage of the
power measurement circuit (Pin 8) is smoothed by R8/C6 and applied to the “high power
shutdown” input at Pin 6. The relation between this voltage V6 and the output power of
the converter P is approximately:
V6 ≈ (P × LSecondary × 5 V)/(VOUT2 × C8 × R9)
LSecondary: The transformers secondary inductance
VOUT: The converters output voltage
So the time constant of R9/C8 for a certain high power shutdown level PSD is:
R9 × C8 ≈ (PSD × LSecondary × 4.2)/VOUT2
The converters high power shutdown level can be dimensioned lower (by R9, C8) than
the current limit level (see “current limiting”). So because of the delay R8/C6, the
converter can deliver maximum output power (current limit level) for a certain time (e. g.
for power pulses like motor start current) and a power below the high power shutdown
level for unlimited time. This has the advantage that the thermal dimensioning of the
power devices is only needed for the lower power level. Once the voltage V6 exceeds
1.2 V there are no more charge or discharge actions at Pin 8. The voltage V6 remains
high due to the bias current out of HPC and the converter remains switched-off. Reset
can be done by either plug-off the supply from the mains or with a high value resistor R6
(Figure 14). R6 causes a reset every view seconds. When Pin 9 is not connected or gets
too less current the temporary high power circuit is disabled.
Data Sheet
18
2000-01-14
TDA 16846
TDA 16847
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
All voltages listed are referenced to ground (0 V, VSS) except where noted.
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
– 0.3
17
V
–
Voltage at Pin 1, 4, 5, 6, 7, 9, 10 –
– 0.3
6
V
–
Voltage at Pin 2, 8, 11
–
– 0.3
17
V
–
Voltage at Pin 3
Current into Pin 3
RZI
6
V
mA
V3 < – 0.3 V
Current into Pin 9
REF
–
mA
–
Current into Pin 13
OUT
100
mA
mA
V13 > VCC
V13 < 0 V
–
2
kV
MIL STD 883C
method 3015.6,
100 pF, 1500 Ω
– 65
125
°C
–
– 25
125
°C
–
–
110
K/W P-DIP-14-3
Supply Voltage at Pin 14
VCC
– 10
–1
– 100
ESD Protection
–
Tstg
Operating Junction Temperature TJ
RthJA
Thermal Resistance
Storage Temperature
Junction-Ambient
Soldering Temperature
–
–
260
°C
–
Soldering Time
–
–
10
s
–
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
19
2000-01-14
TDA 16846
TDA 16847
5.2
Characteristics
Unless otherwise stated, – 25 °C < Tj < 125 °C, VCC = 12 V
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
–
40
100
µA
0 < VCC < V14 ON
–
5
8
mA
Output low
14.5
15
15.5
V
–
7.5
8
8.5
V
–
Start-Up Circuit
Supply current, OFF
Supply current, ON
Turn-ON threshold
Turn-OFF threshold
I14
I14
V14 ON
V14 OFF
Primary Current Simulation PCS (Pin 2) / Current Limiting
1.45
1.5
1.55
V
Peak value
V2
V2
4.85
5
5.15
V
On-time
–
9.0
10.5
11.5
µs
I2 = 100 µA
V11 = 1.2 V
V11 = 1.2 V,
C2 = 220 pF,
I2 = 75 µA
Bias current Pin 2
–
– 1.0 – 0.3 –
µA
–
V11 = 4.5 V
V11 = 4.5 V,
C2 = 220 pF,
I2 = 75 µA
Basic value
Fold Back Point Correction PVC (Pin 11)
Peak value
V2
3.8
4.1
4.3
V
On-time
–
6.2
7.5
8.5
µs
Bias current Pin 11
–
– 1.0 – 0.3 –
µA
–
I1
I1
V1
V1
0.9
1.1
1.4
mA
0.35
0.5
0.65
mA
V3 > 3 V
V3 < 2 V
3.38
3.5
3.62
V
–
1.92
2
2.08
V
–
Off-Time Circuit OTC (Pin 1)
Charge current
Charge current
Peak value
Basic value
Data Sheet
20
2000-01-14
TDA 16846
TDA 16847
5.2
Characteristics (cont’d)
Unless otherwise stated, – 25 °C < Tj < 125 °C, VCC = 12 V
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
T12 Charge time
TC1
0.85
1.0
1.3
µs
T13 Charge time
TC1
1.9
2.4
3.0
µs
Off-time
TD1MAX.
65
72
80
µs
Bias current Pin 1
–
– 1.1 – 0.4 –
µA
–
Zero crossing threshold
(Pin 3)
–
15
25
35
mV
–
Delay to switch-on
–
280
350
480
ns
–
Bias current Pin 3
–
–2
– 1.2 –
µA
V3 < 25 mV
V
–
µA
V3 > 3 V
V3 > 3 V,
C1 = 680 pF,
R1 = 100 kΩ
V3 < 2 V,
C1 = 680 pF,
R1 = 100 kΩ
C1 = 680 pF,
R1 = 100 kΩ
Error Amplifier EA (Pin 3, Pin 4)
Input threshold (Pin 3)
VEATH
4.85
5
Bias current Pin 3
–
–
– 0.9 –
Soft-start charge current
(Pin 4)
–
– 2.5 – 1.8 – 1.2 µA
–
V5
R1
0.3
–
6
V
–
15
20
25
kΩ
–
5.15
Opto Coupler Input (Pin 5)
Input voltage range
Pull high resistor to VREF
Data Sheet
21
2000-01-14
TDA 16846
TDA 16847
5.2
Characteristics (cont’d)
Unless otherwise stated, – 25 °C < Tj < 125 °C, VCC = 12 V
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Fixed Frequency and Synchronization Circuit SYN (Pin 7)
Frequency
–
78
88
98
kHz C7 = 470 pF,
R7 = 20 kΩ
Charge current
1.0
1.3
1.6
mA
–
3.5
3.6
3.7
V
–
Lower threshold
I7
V7
V7
1.43
1.5
1.57
V
–
Charge time
–
0.4
0.55
0.75
µs
–
Bias current Pin 7
–
– 2.4 – 1.8 – 1.1 µA
–
Input voltage range
V7
0.3
–
6
V
–
7.5
8
8.5
V
–
Upper threshold
Undervoltage Lockout SVC (Pin 14)
Threshold
V14 OFF
Overvoltage Lockout OV (Pin 14)
Threshold
V14 OV
15.7
16.5
17
V
–
Delta-OV-V14 ON
–
0.5
–
–
V
–
V11
0.95
1
1.06
V
–
V9
I9
4.8
5
5.15
V
0
µA
I9 = 100 µA
VEATH(Pin 3) –
V9 < 50 mV
Primary Voltage Check PVC (Pin 11)
Threshold
Reference Voltage (Pin 9)
Voltage at Pin 9
Current into Pin 9
Data Sheet
– 200 –
22
2000-01-14
TDA 16846
TDA 16847
5.2
Characteristics (cont’d)
Unless otherwise stated, – 25 °C < Tj < 125 °C, VCC = 12 V
Parameter
Symbol
Limit Values
min.
typ.
max.
1.2
1.28
Unit Test Condition
Fault Comparator FC2 (Pin 6)
HPC Threshold
V6
1.12
Bias Current Pin 6
–
V
–
– 1.0 – 0.3 0.1
µA
–
Fault Comparator FC1 (Pin 10)
Threshold
V10
0.95
1
1.06
V
–
Bias current Pin 10
–
0.48
0.9
1.2
µA
–
µA
I9 = – 100 µA
I13 = 100 mA
I13 = – 100 mA
I13 = – 10 mA,
V14 increasing:
0 < V14 < V14 ON
V14 decreasing:
0 < V14 < V14 OFF
C13 = 10 nF,
V13 = 2 … 8 V
C13 = 10 nF,
V13 = 2 … 8 V
Power Measurement Output PMO (Pin 8, only TDA 16847)
Charge current Pin 8
I8
– 110 – 100 – 90
Output Driver OD (Pin 13)
V13 low
1.1
V13 high 9.2
V13 aclow 0.8
1.8
2.4
V
10
11
V
1.8
2.5
V
Rise time
–
70
110
180
ns
Fall time
–
30
50
80
ns
Output voltage low state
Output voltage high state
Output voltage during low
supply voltage
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Data Sheet
23
2000-01-14
TDA 16846
TDA 16847
4
1
R 62
3
820 Ω
2
C25
14
4
10 nF
18 k Ω
11
R 60
2.2 k Ω
P 60
500 Ω
R 38
R 29
9.1 k Ω
9.1 k Ω
IC1
TDA 16846
C24
100 k Ω
D26
1N4148
4.7 nF
3
C22
150 pF
D41
TR1
MUR4100
(AL = 190 nH)
7 Turns
52 Turns
R 23
6, 10, 12
3.9 MΩ
R 22
1 MΩ
C22
R 30
56 k Ω
2
560 pF
13
7
9
R 35
8
D1-D4
4 x BYW 76
C30
D9
MUR4100
SPP (0.6 Ω )
N6055
L8
2 mH
C8
10 nF
100 V
220 µF
V2
C42
16 V
470 µF
C9
D43
MUR120
220 pF
54 Turns
5 Turns
V3
C43
8.5 V
470 µF
D8
STTA506D
R5
C7
150 µF/450 V
C5
RFI Filter
9 Turns
1.5 nF
5.1 k Ω
1 nF
C10
1 nF
R 10
4.7 MΩ
3.15 A
Data Sheet
C41
N.C.
T1
15 Ω
Figure 15
V1
D42
MUR120
1
F1
R 65
100 k Ω
P10
2 kΩ
1 nF
180-270 V
10 nF
1 nF
R 63
5
R 24
C61
C62
1 kΩ
IC 02
SFH 617 A-2
C26
22 µF
C 28
R 61
AES02659
Circuit Diagram for Application with PFC
24
2000-01-14
TDA 16846
TDA 16847
D26
1N4148
C26
22 µF
C25
14
4
5
R 38
10 nF
3
R 24
18 k Ω
11
9.1 k Ω
IC1
TDA 16846
C24
9.1 k Ω
R 29
C22
150 pF
D41
TR1
MUR4100
(AL = 190 nH)
7 Turns
52 Turns
V1
C41
100 V
220 µF
P10
2 kΩ
1 nF
R 23
6, 10, 12
3.9 MΩ
D42
MUR120
1
R 22
1 MΩ
C22
C30
R 30
56 k Ω
2
680 pF
13
7
9
R 35
15 Ω
8
9 Turns
1.5 nF
V2
C42
16 V
470 µF
N.C.
C9
D43
MUR120
220 pF
T1
SPP (1.4 Ω )
N6055
D10
BA1 59
77 Turns
5 Turns
V3
C43
8.5 V
470 µF
D11
D1-D4
4 x 1N4007
C7
150 µF/385 V
180-270 V
RFI Filter
C10
F1
1 nF
R 10
4.7 MΩ
3.15 A
Figure 16
Data Sheet
AES02660
Circuit Diagram for Standard Application
25
2000-01-14
TDA 16846
TDA 16847
1N4148
C26
22 µF
C25
14
4
D26
5
R 38
10 nF
3
R 24
11
18 k Ω
9.1 k Ω
R 29
9.1 k Ω
C24
C22
150 pF
IC1
TDA 16847
1 nF
R 23
D41
TR1
MUR4100
(AL = 190 nH)
7 Turns
52 Turns
100 V
220 µF
D42
MUR120
1
C30
R 30
R 22
1 MΩ
C22
56 k Ω
7
1.5 nF
9 Turns
V2
C42
16 V
470 µF
R 32
2
8
680 pF
C41
P10
2 kΩ
10, 12
3.9 MΩ
V1
9
6 13
51 k Ω
R 35
1 MΩ
15 Ω
100 pF
C31
D43
MUR120
220 pF
T1
R 33
C32
C9
SPP (1.4 Ω )
N6055
D10 77 Turns
BA 159
4.7 µF
5 Turns
V3
C43
8.5 V
470 µF
D11
D1-D4
4 x 1N4007
C7
150 µF/385 V
180-270 V
RFI Filter
C10
F1
1 nF
3.15 A
Figure 17
Data Sheet
R 10
4.7 MΩ
AES02738
Circuit Diagram for Application with Temporary High Power Circuit
26
2000-01-14
TDA 16846
TDA 16847
Package Outlines
GPD05584
P-DIP-14-3
(Plastic Dual In-line Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
Data Sheet
27
2000-01-14
TDA 16846
TDA 16847
P-DSO-14-3
(Plastic Dual In-line Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
Data Sheet
28
2000-01-14