高佳能 PFC 与 PWM 组合控制暴 TDA16888 及其雇用
高性能 PFC 与 PWM 组合控制器 TDA16888 及真应用
摘
山东省临沂市电子工业局
毛兴武
山东省临沂市银河电子研究应用中心
周建军
北京 9711 信箱 602 分箱
祝大卫
要: TDA16888 是为新一代带通用线路输入和功率因数校正 (PFC) 的离线开关型电源 (SMPS) 而
设计的 O 本文介绍了 TDA16888 的功能及其应用。
关键词 :PFC
TDA16888
一、引言
开关电源 (SMPS) 、荧光灯交流电子镇流器和变
频调速器这类电力电子装置，采用传统的桥式整流、
电容滤波电路会使 AC 输入电流产生严重的波形畸
1.封装形式、内部结构及引脚功能
TDA16888 采用 P
- DIP -20-5 和 P -DSO-
20 -1 封装，顶视图及引脚排列如图 la ， b 所示。
PFCIAC 1 11
变。早在 80 年代初，人们已对这类装置产生的高次谐
波电流所造成的危害引起了关注。 1982 年，国际电工
委员会制订了 IEC55 一 2 限制高次谐波的规范(后来
的修订规范是 IEC1000 - 3 - 2) ，促使众多的电力电
子技术工作者开始了对谐波滤波和功率因数校正
(PFC) 技术的研究。
微电子技术日新月异地飞速发展，有源功率因数
控制器 IC 应运而生。自 80 年代中期开始，西门子等
公司推出了 TDA4814/TDA4815/TDA4816/TDA4817/
TDA4818 /TDA4819 /TDA4862 等系列 PFC 控制器单
片 IC ，其中 TDA4814/TDA4816/TDA4817/TDA4862
PWMCS
适合于在电子镇流器升压式 PFC 预调整器中用作控
制器，而 TDA4815/TDA4818/TDA4819 则适用于
图 1a
P - DIP - 20 - 5 封装顶视图
SM凹的谐波滤波及功率因数校正。进入 90 年代后，
有源 PFC 控制器单片 IC 迅速发展，品种规格已达近
PFCIAC
百个，有源 PFC 升压变换器的输出功率可达
民ER
2
4.5kW 。为降低..SMPS 的成本，使其线路进→步简化，
PFCCC
PFCCS
GNDS
PFCCL
GND
PFC OUT
Vcc
PWMOUT
3
4
90 年代中期， PFC 与 PWM 二合一单片 IC 开始崭露·
头角。其代表性产品有线性技术 (LT) 公司的 LT1508/
LT1 509 和微线性 (ML)公司的 ML4819/M L4 82 1/ ML
4824/M L4826/ML4801/ML4 803 等。其中， ML4 803
采用 8 脚封装，是 1999 年 1 月公布的新产品。本文介
绍的高性能 PFC 与 PWM 控制器 TDA16888 ，是西门
子公司新推出的高集成度单片 IC ，为 PCs 、 CTVs 、监视
器和工业用新一代 SMPS ，并利用失效模式结果分析
(英文缩写为 FMEA) 规则而设计。
二、封装形式、内部结构及主要特点
12
图 1b
O
5
6
7
8
9
10
P - DSO -
11
AUXVS
PFCVS
PFCVD
PFC FB
ROSC
PWM RMP
PWMIN
PWMSS
SYNC
PWMCS
20-1 封装顶视图
TDA16888 由 PFC 和 PWM 控制器两部分组成。
PFC 控制器主要包含有电压误差放大器( OPl) 、乘法
器、电流放大器( OP2) 、比较器 (Cl-C3) 、运算跨导放
大器 (OTA1 - OTA3) 、触发器 (FF I)和 PFC 输出驱动
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叫究开发应用;辛辛如
第5 期
器等电路。 PWM 部分主要包括振荡器(与 PFC 共
表 1
TDA1688 的引脚功能
用)、比较器( C4 - C to 人触发器 (FF2) 和 PWM 图腾柱
脚号
符号
(即推拉式)栅极驱动器等单元电路。此外， TDA16888
1
2
PFC AC
VREF
PFC CC
PFC CS
GND S
PFC CL
GND
FPC OUT
还内置 7.5V 的精密带隙基准、欠电压锁定 ( UVLO)
3
和电源控制电路。图 2 为 TDA16888 内部结构方框
图O
，-pd
『伊
4
5
6
7
8
9
TDA16888 的引脚功能见表 10
2.
主要特点
TDA16888 内的 PFC 控制器可以组成升压式预
调整器，也可以组成回扫式拓扑，在连续或断续方式
10
下工作，采用平均电流和电压传感双环控制及前沿触
11
12
发宽度调制，最大占空比为 949毛。改进的电流型控制
13
PWM 电路可用作设计正向或回扫式变换器。为防止
14
15
16
17
18
19
20
变压器饱和、后沿触发的 PWM 最大占空比限制在
50% 0 PFC 和 PWM 控制器在内部保持同步，在相同
的频率上工作，固定频率范围从 15kHz 直至
200kHz o PFC 与 PWM 均采用快速软开关图腾柱栅极
驱动 (IA) 0TDA16888 启动电源电流典型值为 50μA ，
Vcc
PWM OUT
PWM CS
SYNC
PWM SS
PWM IN
PWM RMP
ROSC
PFC FB
PFC VC
PFC VS
AUX VS
功
能
AC 线路电压传感器输入
7.5V 的基准
PFC 电流环路补偿
PFC 电流传感
电流传感输入地
FPC 电流限制传感输入
地
PFC 驱动器输出
电源电压
PWM 驱动器输出
PWM 电流传感
振荡器同步化输入
PWM 软启动
PWM 输出电压传感输入
PWM 斜坡电压
振荡器频率建立
PFC 电压环路反馈
PFC 电压环路补偿
PFC 输出电压传感输入
辅助电源电压传感
静态工作电流仅 15mA ，具有低待机功耗。监视和保
TDA16888 可用作设计适用于世界各国 AC 供电
护特征主要包括 PFC 直流输出过电压和欠电压监
线路、输入电压从 90V 到 270V 的高品质离线 SMPS ，
测、峰值电流限制和 IC 电源欠电压闭锁等。
满足 IEC1000 - 3 - 2 关于 AC 输入电流的谐波限量
V
C
.
<
MUV
15
PVVM RMP
12 116
SYNC ROSC
卧2
T7
POCT8
EE川U
阿
FUC3
Hus
节
阿
2
口r
T
PFCIAC VREF
℃ S4
℃ C1
问 V
au
FC
10
PVVM OUT
TDA16888 内部结构方框图
13
高性能 PFC ~ PWM 组合拴喇森 TDA16888 及其应用
要求，实现高于 0.99 的线路功率因数，并具有低成
一样，通过内部的振荡器同步化。为确保时钟频率的
本、低损耗和高可靠等优点。此外， IC 的 PFC 还可用
精确度，时钟信号由三角波而不是锯齿波信号派生而
作辅助电隙。
来，并且提供一个占空比为 50% 的时钟参考信号。在
三、工作原理概述
馈送到 PFC 和 PWM 之前，振荡器时钟信号的频率通
1.电源
过 D 寄存器 (D - Latch) 减半。
PFC 斜坡信号由一个缓慢的下降沿和陡峭的上
TDA16888 的脚 9( Vcc) 内部并联一支 17.5V 的
升沿组成。考虑到在脚 5(GND S) 土的电流测量和
齐纳二极管 Z3( 见图 2) ，只要该脚上的电压达
OP2的脚 5 与脚 3(PFC CC) 之间外部有补偿， PFC 斜
17.5V 以上， IC 则被保护。在 IC 的任意脚都有专门的
坡极性先于其它波形反转。
静电放电 (ESD) 电路，用作 ESD 保护。只要 Vcc 脚上
IC 的振荡器也可与施加到脚 12(SYNC) 上的外
电压超过 14V 的门限， IC 则从待机状态进入操作模
部时钟脉冲信号同步化。但由于振荡频率在进入 PFC
式。当电游、电压降至 llV 的门限以下时， IC 则从操作
和 PWM 电路之前被二等分减半，故同步频率宜为工
模式进入待机状态。
作频率的 2 倍。只要同步信号处于高电平，振荡器的
通过 TDA16888 的电源控制和脚 13(PWM SS) 的
三角波信号则被阻断，并且其时钟信号是高电平。外
软启动特性，在电源电压进入稳态后， PWM 控制器通
部的时钟信号从高到低变化，振荡器就释放。施加到
过内部的偏置控制被赋能运行。
脚 12(SYNC) 上的一个外部时钟信号，通过脚 16 脚
2. 保护电路
(ROSC) 上的外接电阻，可使振荡频率 fosc 从
TDA16888 的比较器 C6 通过脚 19(PFC VS) 传
感过电压后，立即关闭 PFC 和 PWM 的栅极驱动，履
行过电压保护功能。运算跨导放大器。 TA2 除了用作
改进 PFC 预调整器的负载调整之外，也通过对脚 19
上的信号检测，实现对乘法器输出价的适度控制和
快速过电压保护 O
0.66focs 到 2fosc 变化。为减小在低负载条件下的总
电流消耗，在脚 13 (PWM SS) 上的电压只要低于 0.4V
(PWM 控制器禁耗) ，振荡器频率则被平分。
4. PFC 控制器
TDA16888 中的 PFC 控制器带双环控制。其中，
内环控制由 OP2 ， C 1 和 PFC 驱动器组成，利用连续
万 -PFC 输出出现欠电压，比较器 G 通过脚 19
或断续模式的平均电流控制，实现对 AC 线路输入电
检测。为提升 PFC 输出电压，减小负载电流， PWM 控
流波形的校正。外环控制主要由 OPl 、乘法器、 OP2 ，
制器将关断其栅极驱动器输出。欠电压关闭必须在
C 1 、 FFl 和 PFC 驱动器支撑，控制 PFC 输出 DC 电
IC 欠电压自锁之前发生，也就是说，关闭 PWM 输出
压。此外 ， OTAl 、 OP2 、 C h FFl 和 PFC 驱动器组成第
时，脚 9( Vcc) 上的电压恰好在 llV 的欠电压自锁门
三个控制环路，在 PWM 控制器被禁能时，允许 PFC
限以上。如果在脚 19 上的电压由于某种原因降至 lV
电路作为辅助电源工作。此情况下，为减小总电流消
以下，比较器 C2 则被触发 ， IC 脚 8 上的 PFC 输出立
麓， PFC 电路工作频率应为正常工作频率的一半。为
即关闭。
得到最小的 AC 输入电流(过零时)间隙， PFC 驱动输
TDA16888 的比较器 G 和 G 分别通过脚 6
(PFC cL)和脚 11 (PWM CS) 传感器和检测 PFC 和
PWM 变换器的电流。只要脚 6 和脚 11 上的电压达到
峰值电流限制门限，则会立即关断脚 8(PFC OUT) 或
脚lO (PWM OUT) 栅极驱动输出。
此外， TDA16888 的每个引脚都具有抗 ESD 保护
功能。
3. 振荡器/同步化
出信号的最大占空比为 949毛。
5. PWM 控制器
与通常采用的前沿电流消隐比较" TDA16888 的
PWM 控制器采用改进的电流型控制，包含有效的斜
率补偿，以提高对尖峰脉冲噪声的抑制能力。该作用
的实现，通过 OP3、电压源 Vl (I .5V) 、低通滤波元件
R 1 及脚 15(PWM RMP) 上的外接电容实现。 PWM 负
载电流通过脚 11 (PWM CS) 外部的并联电阻检测，并
TDA16888 振荡器频率由一只连接于脚 16
由 OP3 进行放大。在功率晶体管开通时，由于电容放
(RSOC) 与地之间的外接电阻设定。为保证有一个低
电产生的超前尖峰，被一个低通滤波器所抑制。利用
电流消耗和对电磁干扰 (EMI)有一个高阻抗，相应的
电压 V1 与后随低通滤波器的结合，能产生一个带有
电容被集成。 PFC 和 PWM 时钟信号与 PFC 电压斜坡
超前陷波的阶跃斜坡，可完全补偿一个超前尖峰噪
14
绕开发应用 d 俨
(<tl乎无.a件应用 hooo 军 5 月，第 2 卷第 5 期
范围为 90 - 270V ，三路 DC 输出为一 12V /1 A 、 12V /
声。
PWM 控制器根据在脚 15(PWM RMP) 上的
4.2A 和 5V /20A ，辅助电源输出是 5V /0. lA; 系统功
PWM 斜坡电压和脚 14(PWM IN) 上的输入电压采用
率因数高于 0.99 ， AC 输入电流总谐坡畸变率 (THD)
后沿调制。而 PFC 控制器的脉冲宽度调制采用前沿
及各次谐波分量值符合 IEC1000 - 3 - 2 规定的限制
触发，这样可以避免 PFC 与 PWM 控制器之间的电磁
要求，属于一种新一代绿色 SMPS o
干扰 (EMI)。为阻止变压器饱和， PMW 最大占空比限
1.有源 PFC 升压式预变换器
制到 50% 。通过改进的电流方式控制，从最大负载到
有桥式整流器 D ， - D4 与铝电解电容 C3 之间，
无载，可得到稳定的脉冲宽度调制。
TDA16888 内的 PFC 控制器、升压电感 L 2 、升压二极
TDA16888 的振荡器频率设定电路及其相关披
管品、功率开关 Q ， (MOSFET) 和电流传感电阻品
形如图 3 所示。
等，组成有源 PFC 升压式预变换器。
在 SMPS 接通 AC 输入电压之后，流经高阻电阻
品的电流对组合 IC(Combi - IC) 脚 9 上的外接电容
CllA 充电。只要 CllA 被充电到脚 9( Vcc) l1 V 的门限
电压以上， IC 中的 PFC 控制器则被触发启动。
Rosc
COS E
电
Ljt
4
、
i
活，为 Q ， 栅极发送驱动脉冲。为节省电路，在 PFC 控
制器触发过程中， Combi -IC 用正常王作频率的 112
驱动升压晶体管 Q" 同时 PWM 控制器尚未被触发赋
j
~tI
(2) 内部 01钟
CllA 电跌落到 llV 的关断门坎电压之前， IC 可被激
路~/…
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容量应足够大(至少不低于 22μF) ，在脚 9 上电压因
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能。 IC 电源电压由 L2 的辅助绕组 AUXl 、 C'8 和 Dll 、
C! ock
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MAX Duty Cycle PWM
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(3) 最大 I ~I- 节比
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PFC
Cl ， A
11
(/
R28 、 Q3 及 CllA 组成的电源电路提供。 1a 的另一个辅
助绕组及 D'6 - D'9 、 IC5 和 C'9 、 C20 组成辅助电源电
路，输出为 5V /0. 1 A o '
在 Q ， 漏极通过 D6 和 ι 与其栅极驱动电路相
连接，一旦在 DC 母线电压出现一个过冲，通过 D6 能
在 100μ 之内被检测，并使因过冲停止工作的升压开
关。l 开始运行。在 IC 待机工作时， DC 总线电压仍保
持在正常的电平上。如果 DC 总线电压低于正常值，
IC 则依靠品和 R2 启动。 IC 的第一个过电压门限是
亡==::::J
(6) PFC输山
L/
fWM RAMPVoltag斗(Pin 1 句
6.5VmaxT
(7)咱:1坡咆压 V:!LL
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1.0V
电j在(脚 1 1>
‘
阻止 DC 总线电压的升高。当 DC 总线电压比设定值
高 20% 时，达到第二个过电压门限， IC 将迅速关闭
PFC 和 PWM 输出，并与输入端压敏兀件品。相结合，
履行过电压保护功能。
。
图 3b
况一旦发生，通过 IC 内的 OTA2 和乘法器关断矶，以
二，卢尺寸;三 A
, qPWMCAmMs叫 Uol同创刊川)
(8) PWM 电流传感
DC 母线电压比设定值 (380V) 高出 10% 以上时，此情
TDA16888 相关波形
四、 TDA16888 的典型应用
误差放大器 (OP1 )在脚 18 输出一个带有叠加
AC 小纹波的电压信号，与来自脚 1 的 AC 电流传感
信号相乘，在乘法器输出的电流波形如同 AC 输入电
TDA16888 适合于用作设计 AC 输入电压从 90V
压波形一样，按正弦规律变化。电流误差放大器
到 270V 、带 PFC 功能的新一代 SMPS 。利用 TDA16888
(OP2)用作控制乘法器输出，对乘法器包含的脚 18
能够组成多路输出回扫变换器，也可以组成多路输出
上的电压输入有二个扩充功能。在轻载和无载情况
前馈变换器等不同的拓扑。图 4 示出了用 TDA16888
下， IC 内的 OTA3 负责照管 PFC 电路 DC 输出总线电
作为控制器的 150W 高功率因数 PC 开关电源电路原
压的稳定性。只要 OP1 在脚 18 上的输出降至1. 2V
理图。该 150W 前馈多路输出 PC SMPS ， AC 输入电压
以下，通过校正乘法器输出电流，就可实现对 DC 总
15
高性能 PFC ~旨 PWM 组合控制暴 TDA16888 及其雇用
R3 1
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芹制E
用 TDA16888 作为控制器的 150W 高功率因数多路输出 PC 开关电源电路
不随 AC 输入电压波动变化的高度稳定的 DC 电压;
线电压的调节作用。
由 TDA16888 内的 PFC 控制器组成的有摞 PFC
二是 PFC 输出 DC 电压纹波 Vp -
p
11i小，且呈 100Hz/
升压变换器，主要作用有:一是在 AC 输入端产生与
120Hz( 工频 2 倍)的正弦波，可使用容量较小的滤波
AC 输入电压同相位的正弦电流披形(如图 5) ，具有
电容( C3) 。
低谐波畸变和几乎接近于 1 的高功率因数;二是输出
2.PWM 变换器
当 DC 总线电压升至设定值的 80%
ν卢、 p
100%
90%
-/-
./
2ms
二、 ---
7Reσt lified
'il1D罚
、、
v
J\
/. /
ρ'
Clnp
1 \11口 1I
\
飞
0%
/
v
\
10%
---
ACI pulC rrenl
(0.5
Div)
X、
阳、
-f :l
<-
10mV
图 5
16
100V
AC 整流电压与 AC 输入电流波形
以上时， PWM 变换器通过软启动(脚
启动电容 C l4 短路时 ， IC 的 PWM 控制器则禁能。 PFC
\
、/
=304V)
13) 用正常工作频率开始运行。当 Q4 饱和导通将软
\、
/
/
队
γ
80%
gs
(即 380 x
升压变换器开关 Ql 随脉冲宽度调制前沿导通，而
N
PWM 开关 Q2 则随后沿开通，延迟时间通常至少为
/
工作周期的 50%
0
PWM 开关 Q2 源极电阻 Rl5 上的电流信号，经
R32 和 C21 低通滤波器滤波，通过 IC 脚 11 检测。 Rl5
上的电压被 IC 内 OP3 放大 5 倍后，馈送到 IC 中
lOkn 电阻上。为进行斜举补偿，并抑制尖峰噪声， IC
脚 15 与地之间外接电容 C!3产生一个斜坡电压，与
〈也乎无~侍应用 hooo 军 5 月，第 2 卷
喝泛开发应用飞如
第5期
IC 中lOkfi( Rl) 电阻上的电压相叠加。斜坡电压高电
平为 6.5V ，脚 14 上相应的有源输入范围为 0.47V 。在 PWM 比较器上较高的电平，具有较好的操作
100V
0001c
回 0%
i
左X
一PVVIv1一D-raLin一
-Sour一
ce V-olta-g3e
---
(100V/Div， On-Ti me7.5μs ， L)
稳定性和抗 EMI 性能。 IC 脚 11 上的电流传感输入同
2μs
关
\
时还通过 IC 内门限电压是凹的快速比较器 (C9) ,
履行最大电流限制功能。 SMPS 的次边 DC 输出电压
的波动，通过光电相合器 IC3 反馈到 IC 脚 14 ，以调节
PWM 占空因数，从而在输出端获得稳定的 DC 电
压。
PFC Drain-S口 urce Voltage
(100V/Div， On-Ti me7.5μs ， L)
10%
0%
产-
---
3.PFC 和 PWM 栅极驱动
100V
为避免产生交叉传导电流，并产生一个电压调
制开通斜面， TDA16888 的 PFC 和 PWM(MOSFET 或
IGBT)MOS 栅极驱动器采用图腾柱拓扑结构。导通斜
面(即栅极驱动电压上升前沿)从 OV 适度地升高到
3V ，再从 3V 缓慢地增加到 5V ，最后从 5V 适度地上
升到 12V ，如图 6 所示。这种栅极驱动电压上升沿有
利于在 IC 履行电流限制功能时，能快速关断功率开
关，并使占空比可连续不断地减小到零 c 当峰值电流
大约达l. 5A 时， PFC 和 PWM 栅极驱动输出将迅速
200ms
5V
图 7
PFC 与 PWM 开关漏源、极之间电压波形
内部振荡器上。
TDA16888 的开关频率可通过锁相环 (PLL)
-
CMOS - IC 4046 的 (CRT 监视器的)基准频率同步
化，如图 8 所示。 4046 控制 TDA168888 脚 16 上的输
出电流，从而确立内部振荡器开关频率。 TDA16888
脚 10 上的 PWM 输出信号通过几。、 R 51 电压分配器
馈送到 4046 的脚 3 。取自 CRT 偏转线圈上的参考频
率信号输入到 4046 的 14 脚，与内部的相位比较器进
行比较。在 4046 脚 13 上的输出信号，代表 PWM 输出
栅极驱动电压
100%
--(5VlD iv)
90%
I
\
r
1/
/飞
气
、、
f
对 BUZ91 的驱动电压
O.5A1 Div
7
R"
IpVVIv1
Driver
Outpu
0%
-町-
10mV
图 6
栅极驱动电压与对开关 (BUZ91 )的驱动电流波形
关闭。当 Combi 一 IC 在欠电压门限以下工作时，其驱
图 8
动输出为低电事。
PFC 与 PWM 开关( Ql 、 Q2) 的漏一源极之间的.
电压波形如图 7 所示。
4. 振荡器与同步
由锁相环 4046 COMS - IC 组成
的 TDA16888 同步化电路
与参考信号的相位差，通过 R55 和 C44 组成低通滤波
器馈送至脚 9(VOC) ，形成相位差的平均值信号。 Q6
的基板电流由 4046 的脚 10(DEM OUT) 控制 ， R 24 、 R52
Combi 一 IC 的振荡器依靠内部集成的低容差小
可用作设定 TDA16888 振荡器最小和最大频率(从
电容、-个专门的电压和温度补偿的电流镜及脚 16
60kHz 到 120kHz 可调 )0 Q6 集电极上的动态信号经
上外接电阻 R 2 4 工作，内部振荡器频率为外部工作频
华及其 RC 网络反馈到 4046 的脚 9 0 C43 和 C7 用作
率的 2 倍，并通过触发器将 PWM 占空比限制在 50%
以内。通过改变 R24 上的电流可以使振荡器工作频率
旁路高频电流， PLL 的响应时间低于 10ms 。如果有些
PWM 输出脉冲错过，振荡器频率则偏移至最高值;女日
发生变化，同时影响脚 15 上外接电容 C 13 上的斜坡
果参考频率和触发器脉冲失踪，振荡器频率则降至最
电压。有一个外部同步信号可输入到脚 12 ，并叠加于
低值。
17
Da t a s h e e t , V 2 . 0 , 2 8 F e b 2 0 0 0
PWM+PFC Combi IC
TDA 16888 / TDA 16888G
High Performance Power
Combi Controller
Power Conversion
N e v e r
s t o p
t h i n k i n g .
TDA 16888/ TDA 16888G
Revision History:
2000-02-28
Datasheet
Previous Version:
Page
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
CoolMOS™, CoolSET™ are trademarks of Infineon Technologies AG.
Edition 2000-02-28
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 1999.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
High Performance Power Combi Controller
1
Overview
1.1
Features
TDA 16888
PFC Section
–
–
–
–
–
–
–
–
–
IEC 1000-3 compliant
Additional operation mode as auxiliary power supply
Fast, soft switching totem pole gate drive (1 A)
Dual loop control (average current and voltage
sensing)
Leading edge triggered pulse width modulation
Peak current limitation
Topologies of PFC preconverter are boost or flyback
Continuous/discontinuous mode possible
94% maximum duty cycle
P-DIP-20-5
P-DSO-20-1 /-6 /-7
PWM Section
–
–
–
–
–
–
–
Improved current mode control
Fast, soft switching totem pole gate drive (1 A)
Soft-start management
Trailing edge triggered pulse width modulation
Topologies of PWM converter are feed forward or flyback
50% maximum duty cycle to prevent transformer saturation
fPWM = fPFC
Type
Ordering Code
Package
▼ TDA 16888
Q67000-A9284-X201-K5
P-DIP-20-5
▼ TDA 16888 G
Q67000-A9310-A702
P-DSO-20-1
▼ New type
Version 2.0
3
28 Feb 2000
TDA 16888
Special Features
–
–
–
–
–
–
–
–
–
–
High power factor
Typical 50 µA start-up supply current
Low quiescent current (15 mA)
Undervoltage lockout with internal stand-by operation
Internally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz
External synchronization possible
Shutdown of both outputs externally triggerable
Peak current limitation
Overvoltage protection
Average current sensing by noise filtering
1.2
General Remarks
The TDA 16888 comprises the complete control for power factor controlled switched
mode power supplies. With its PFC and PWM section being internally synchronized, it
applies for off-line converters with input voltages ranging from 90 V to 270 V.
While the preferred topologies of the PFC preconverter are boost or flyback, the PWM
section can be designed as forward or flyback converter. In order to achieve minimal line
current gaps the maximum duty cycle of the PFC is about 94%. The maximum duty cycle
of the PWM, however, is limited to 50% to prevent transformer saturation.
Version 2.0
4
28 Feb 2000
TDA 16888
P-DIP-20-5
P-DSO-20-1
PFC IAC
1
20
AUX VS
VREF
2
19
PFC VS
PFC CC
3
18
PFC VC
PFC CS
4
17
PFC FB
GND S
5
16
ROSC
PFC CL
6
15
PWM RMP
GND
7
14
PWM IN
PFC OUT
8
13
PWM SS
VCC
9
12
SYNC
10
11
PWM CS
PWM OUT
PFC IAC
VREF
PFC CC
PFC CS
GND S
PFC CL
GND
PFC OUT
VCC
PWM OUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AUX VS
PFC VS
PFC VC
PFC FB
ROSC
PWM RMP
PWM IN
PWM SS
SYNC
PWM CS
AEP02486
AEP02461
Figure 1
Version 2.0
Pin Configuration (top view)
5
28 Feb 2000
TDA 16888
1.3
Pin Definitions and Functions
Pin No.
Symbol
Function
1
PFC IAC
AC line voltage sensing input
2
VREF
7.5 V reference
3
PFC CC
PFC current loop compensation
4
PFC CS
PFC current sense
5
GND S
Ground sensing input
6
PFC CL
Sensing input for PFC current limitation
7
GND
Ground
8
PFC OUT
PFC driver output
9
VCC
Supply voltage
10
PWM OUT
PWM driver output
11
PWM CS
PWM current sense
12
SYNC
Oscillator synchronization input
13
PWM SS
PWM soft-start
14
PWM IN
PWM output voltage sensing input
15
PWM RMP
PWM voltage ramp
16
ROSC
Oscillator frequency set-up
17
PFC FB
PFC voltage loop feedback
18
PFC VC
PFC voltage loop compensation
19
PFC VS
PFC output voltage sensing input
20
AUX VS
Auxiliary power supply voltage sense
Version 2.0
6
28 Feb 2000
R2
VS
M1
M2
M 3 D1
QM
2
V REF
Voltage Reference
7.5 V (Output Disable)
Power Management
Undervoltage Lockout
11 V-14 V
Z3
17.5 V
10 k Ω
5V
OP1
<_ 1
D2
OTA1
6V
12 16
SYNC ROSC
+
_
13
PWM
SS
7.4 V
5V
D3
AUX
VS
20
+
_
OP2
0.45 V
0.4 V C5
Ι1
30 µ A
GND
S
5
PWM
Bias
Control
+
_
PFC
CS
4
OTA3
1.2 V
OTA2
C1
C4
14
PWM
IN
Osc
PFC
CC
3
C6
+
_
C2
C7
C8
R1
0.4 V
10 k Ω
6V
5.5 V
15
PWM
RMP
R3
100 k Ω
4V
5.5 V 1 V
PFC
VS
19
+
_
+
_
7
+
_
+
_
1
C10
V1
1.5 V
+
_
+
_
+
_
Version 2.0
+
_
PFC
VC
18
FF1
R
S
11
PWM
CS
_
FF2
S
R
1V
C9
OP3 1 V
+
5
&
&
+
_
C3
PFC
CL
6
D4
&
&
7
GND
VS
Z2
VS
Z1
VS
9
V CC
AEB02357
10
PWM
OUT
PFC
OUT
8
1.4
+
_
PFC PFC
IAC FB
1
17
TDA 16888
Block Diagram
Figure 2
28 Feb 2000
TDA 16888
2
Functional Description
Power Supply
The TDA 16888 is protected against overvoltages typically above 17.5 V by an internal
Zener diode Z3 at pin 9 (VCC) and against electrostatic discharging at any pin by special
ESD circuitry.
By means of its power management the TDA 16888 will switch from internal stand-by,
which is characterized by negligible current consumption, to operation mode as soon as
a supply voltage threshold of 14 V at pin 9 (VCC) is exceeded. To avoid uncontrolled
ringing at switch-over an undervoltage lockout is implemented, which will cause the
power management to switch from operation mode to internal stand-by as soon as the
supply voltage falls below a threshold of 11 V. Therefore, even if the supply voltage will
fall below 14 V, operation mode will be maintained as long as the supply voltage is well
above 11 V.
As soon as the supply voltage has stabilized, which is determined by the TDA 16888’s
power management and its soft-start feature at pin 13 (PWM SS), the PWM section will
be enabled by means of its internal bias control.
Protection Circuitry
Both PFC and PWM section are equipped with a fast overvoltage protection (C6)
sensing at pin 19 (PFC VS), which when being activated will immediately shut down both
gate drives. In addition to improve the PFC section’s load regulation it uses a fast but soft
overvoltage protection (OTA2) prior to the one described above, which when being
activated will cause a well controlled throttling of the multiplier output QM.
In case an undervoltage of the PFC output voltage is detected at pin 19 (PFC VS) by
comparator C4 the gate drive of the PWM section will be shut down in order to reduce
the load current and to increase the PFC output voltage. This undervoltage shutdown
has to be prior to the undervoltage lockout of the internal power management and
therefore has to be bound to a threshold voltage at pin 9 (VCC) well above 11 V.
In order to prevent the external circuitry from destruction the PFC output PFC OUT
(pin 8) will immediately be switched off by comparator C2, if the voltage at pin 19
(PFC VS) drops to ground caused by a broken wire. In a similar way measures are taken
to handle a broken wire at any other pin in order to ensure a safe operation of the IC and
its adjoining circuitry.
If necessary both outputs, PFC OUT (pin 8) and PWM OUT (pin 10), can be shutdown
on external request. This is accomplished by shorting the external reference voltage at
pin 2 (VREF) to ground. To protect the external reference, it is equipped with a foldback
characteristic, which will cut down the output current when VREF (pin 2) is shorted (see
Figure 4).
Version 2.0
8
28 Feb 2000
TDA 16888
Both PFC and PWM section are equipped with a peak current limitation, which is realized
by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS)
respectively. When being activated this current limitation will immediately shut down the
respective gate drive PFC OUT (pin 8) or PWM OUT (pin 10).
Finally each pin is protected against electrostatic discharge.
Oscillator/Synchronization
The PFC and PWM clock signals as well as the PFC voltage ramp are synchronized by
the internal oscillator (see Figure 18). The oscillator’s frequency is set by an external
resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding
capacitor, however, is integrated to guarantee a low current consumption and a high
resistance against electromagnetic interferences. In order to ensure superior precision
of the clock frequency, the clock signal CLK OSC is derived from a triangular instead of
a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50%
duty cycle, the frequency of the oscillator’s clock signal CLK OSC is halved by a D-latch
before being fed into the PFC and PWM section respectively (see Figure 18).
The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a
steeply rising edge. This ramp has been reversed in contrast to the common practice, in
order to simultaneously allow for current measurement at pin 5 (GND S) and for external
compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC).
The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). However, since the oscillator’s frequency is halved before being fed into the
PFC and PWM section, a synchronization frequency being twice the operating frequency
is recommended. As long as the synchronization signal is H the oscillator’s triangular
signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and
Figure 20). However, as soon as the external clock changes from H to L the oscillator is
released. Correspondingly, by means of an external clock signal supplied at pin 12
(SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be
varied on principle only within the range from 0.66 fOSC to 2 fOSC. If the oscillator has to
be synchronized over a wider frequency range, a synchronization by means of the sink
current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12
(SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanently
shutdown both PFC and PWM section. It can be used to halt the oscillator freezing the
prevailing state of both drivers but does not allow to automatically shut them down. A
shutdown can be achieved by shorting pin 2 (VREF) to ground, instead.
Finally, In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
Version 2.0
9
28 Feb 2000
TDA 16888
PFC Section
At normal operation the PFC section operates with dual loop control. An inner loop,
which includes OP2, C1, FF1 and the PFC’s driver, controls the shape of the line current
by average current control enabling either continuous or discontinuous operation. By the
outer loop, which is supported by OP1, the multiplier, OP2, C1, FF1 and the PFC's driver,
the PFC output voltage is controlled. Furthermore there is a third control loop composed
of OTA1, OP2, C1, FF1 and the PFC’s driver, which allows the PFC section to be
operated as an auxiliary power supply even when the PWM section is disabled. With
disabled PWM section, however, the PFC section is operated with half of its nominal
operating frequency in order to reduce the overall current consumption.
Based on a pulse-width-modulation, which is leading edge triggered with respect to the
internal clock reference CLK OUT and which is trailing edge modulated according to the
PFC ramp signal VPFC RMP and the output voltage of OP2 VPFC CC (see Figure 18), the
PFC section is designed for a maximum duty cycle of ca. 94% to achieve minimal line
current gaps.
PWM Section
The PWM section is equipped with improved current mode control containing effective
slope compensation as well as enhanced spike suppression in contrast to the commonly
used leading edge current blanking. This is achieved by the chain of operational amplifier
OP3, voltage source V1 and the 1st order low pass filter composed of R1 and an external
capacitor, which is connected to pin 15 (PWM RMP). For crosstalk suppression between
PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled
PWM’s is set by operational amplifier OP3 performing a fivefold amplification of the PWM
load current, which is sensed by an external shunt resistor. In order to simultaneously
perform effective slope compensation and to suppress leading spikes, which are due to
parasitic capacitances being discharged whenever the power transistor is switched on,
the resulting signal is subsequently increased by the constant voltage of V1 and finally
fed into the 1st order low pass filter. The peak ramp voltage, that in this way can be
reached, amounts to ca. 6.5 V. By combination of voltage source V1 and the following
low pass filter a basic ramp (step response) with a leading notch is created, which will
fully compensate a leading spike (see Figure 12) provided, the external capacitor at
pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly.
Version 2.0
10
28 Feb 2000
TDA 16888
The pulse-width-modulation of the PWM section is trailing edge modulated according to
the PWM ramp signal VPWM RMP at pin 15 (PWM RMP) and the input voltage VPWM IN at
pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulsewidth-modulation of the PWM section is trailing edge triggered with respect to the
internal clock reference CLK OUT in order to avoid undesirable electromagnetic
interference of both sections. Moreover the maximum duty cycle of the PWM is limited
to 50% to prevent transformer saturation.
By means of the above mentioned improved current mode control a stable pulse-widthmodulation from maximum load down to no load is achieved. Finally, in case of no load
conditions the PWM section may as well be disabled by shorting pin 13 (PWM SS) to
ground.
Version 2.0
11
28 Feb 2000
TDA 16888
3
Functional Block Description
Gate Drive
Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and
pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents
and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the
attached power transistors as well as to protect them against undesirable gate
overvoltages. At voltages below the undervoltage lockout threshold these gate drives are
active low. In order to keep the switching losses of the involved power diodes low and to
minimize electromagnetic emissions, both gate drives are optimized for soft switching
operation. This is achieved by a novel slope control of the rising edge at each driver’s
output (see Figure 13).
Oscillator
The TDA 16888’s clock signals as well as the PFC voltage ramp are provided by the
internal oscillator. The oscillator’s frequency is set by an external resistor connected to
pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is
integrated to guarantee a low current consumption and a high resistance against
electromagnetic interferences. In order to ensure superior precision of the clock
frequency, the clock signal CLK OSC is derived from the minima and maxima of a
triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock
reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator’s clock
signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section
respectively.
The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a
steeply rising edge, the latter of which is triggered by the rising edge of the clock
reference CLK OUT. This ramp has been reversed in contrast to the common practice,
in order to simultaneously allow for current measurement at pin 5 (GND S) and for
external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The
slope of the falling edge, which in conjunction with the output of OP2 controls the pulsewidth-modulation of the PFC output signal VPFC OUT, is derived from the current set by the
external resistor at pin 16 (ROSC). In this way a constant amplitude of the ramp signal
(ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum
blanking interval and therefore limits the maximum duty cycle ton,max of the PFC output
signal, is determined by an internal current source.
In contrast to the PFC section the ramp signal of the PWM section is trailing edge
triggered with respect to the internal clock reference CLK OUT to avoid undesirable
electromagnetic interference of both sections. Moreover, the maximum duty cycle of the
PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent
transformer saturation.
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The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). As long as this clock signal is H the oscillator’s triangular signal VOSC is
interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However,
as soon as the external clock changes from H to L the oscillator is released.
Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the
oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on
principle only within the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the
falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead
the lower voltage peak is modulated. Consequently, on the one hand at high
synchronization frequencies fSYNC > fOSC the amplitude of the ramp signal and
correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand
at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the
minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which
may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops
below this threshold. However, if the oscillator has to be synchronized over a wide
frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has
to be preferred to a synchronization by means of pin 12 (SYNC).
In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
Multiplier
The multiplier serves to provide the controlled current IQM by combination of the shape
of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means
of the 10 kΩ resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18
(PFC VC) and the possibility for soft overvoltage protection VM3 (see Chapter
Protection Circuitry ). By means of this current the required power factor as well as the
magnitude of the PFC output voltage is ensured. To achieve an excellent performance
over a wide range of output power and input voltage, the input voltage VM2 is amplified
by an exponential function before being fed into the multiplier (see Figure 8).
Voltage Amplifier OP1
Being part of the outer loop the error amplifier OP1 controls the magnitude of the PFC
output voltage by comparison of the PFC output voltage measured at pin 17 (PFC FB)
with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity
from external noise. To allow for individual feedback the output of OP1 is connected to
pin 18 (PFC VC).
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Current Amplifier OP2
Being part of the inner loop the error amplifier OP2 controls the shape of the line current
by comparison of the controlled current IQM with the measured average line current. This
is achieved by setting the pulse width of the PFC gate drive in conjunction with the
comparator C1. In order to limit the voltage range supplied at pin 4 (PFC CS) and at pin 5
(GND S), clamping diodes D1, D2 and D3 are connected with these pins and ground. To
allow for individual feedback the output of OP2 is connected to pin 3 (PFC CC).
Ramp Amplifier OP3
For crosstalk suppression between PFC and PWM section a signal-to-noise ratio
comparable to voltage mode controlled PWMs is set by operational amplifier OP3
performing a fivefold amplification of the PWM load current, which is sensed by an
external shunt resistor. In order to suppress leading spikes, which are due to parasitic
capacitances being discharged whenever the power transistor is switched on, the
resulting signal is subsequently increased by the constant voltage of V1 and finally fed
into a 1st order low pass filter. By combination of voltage source V1 and the following low
pass filter a step response with a leading notch is created, which will fully compensate a
leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP)
and the external current sensing shunt resistor are scaled properly.
Operational Transconductance Amplifier OTA1
The TDA 16888’s auxiliary power supply mode is controlled by the fast operational
transconductance amplifier OTA1. When under low load or no load conditions a voltage
below 5 V is sensed at pin 20 (AUX VS), it will start to superimpose its output on the
output QM of the multiplier and in this way will replace the error amplifier OP1 and the
multiplier. At normal operation, however, when the voltage at pin 20 (AUX VS) is well
above 5 V, this operational transconductance amplifier is disabled.
Operational Transconductance Amplifier OTA2
By means of the operational transconductance amplifier OTA2 sensing at pin 19
(PFC VS) a fast but soft overvoltage protection of the PFC output voltage is achieved,
which when being activated (VPFC VS > 5.5 V) will cause a well controlled throttling of the
multiplier output QM (see Figure 9).
Operational Transconductance Amplifier OTA3
In order to achieve offset compensation of error amplifier OP2 under low load conditions,
that will not suffice to start OTA1, the operational transconductance amplifier OTA3 is
introduced. It will start operation as soon as these conditions are reached, i.e. the voltage
at pin 18 (PFC VC) falls below 1.2 V.
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Comparator C1
The comparator C1 serves to adjust the duty cycle of the PFC gate drive. This is
achieved by comparison of the output voltage of OP2 given at pin 3 (PFC CC) and the
voltage ramp of the oscillator.
Comparator C2
The comparator C2 serves to prevent the external circuitry from destruction by
immediately switching the PFC output PFC OUT (pin 8) off, if the voltage at pin 19
(PFC VS) drops below 1 V due to a broken wire.
Comparator C3
By means of this extremely fast comparator sensing at pin 6 (PFC CL) peak current
limitation is realized. When being activated (VPFC CL < 1 V) it will immediately shut down
the gate drive of the PFC section (pin 8, PFC OUT). In order to protect C3 against
undervoltages at pin 6 (PFC CL) due to large inrush currents, this pin is equipped with
an additional clamping diode D4.
Comparator C4
This comparator along with the TDA 16888’s power management serves to reset the
PWM section’s soft start at pin 13 (PWM SS). C4 becomes active as soon as an
undervoltage (VPFC VS < 4 V) of the PFC output voltage is sensed at pin 19 (PFC VS).
Comparator C5
Based on the status of the PWM section’s soft start at pin 13 (PWM SS), the comparator
C5 controls the bias of the entire PWM section. In this way the PWM section is switched
off giving a very low quiescent current, until its soft start is released.
Comparator C6
Overvoltage protection of the PWM section’s input voltage sensed at pin 19 (PFC VS) is
realized by comparator C6, which when being activated will immediately shut down both
gate drives PFC OUT (pin 8) and PWM OUT (pin 10).
Comparator C7
This comparator sensing at pin 13 (PWM SS) and at pin 15 (PWM RMP) controls the
pulse width modulation of the PWM section during the soft start. This is done right after
the PWM section is biased by comparator C5.
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Comparator C8
The control of the pulse width modulation of the PWM section is taken over by
comparator C8 as soon as the soft start is finished. This is achieved by comparison of
the PWM output voltage at pin 14 (PWM IN) and the PWM voltage ramp at pin 15
(PWM RMP).
Comparator C9
By means of this extremely fast comparator sensing at pin 11 (PWM CS) peak current
limitation is realized. When being activated (VPWM CS > 1 V) it will immediately shut down
the gate drive of the PWM section (PWM OUT).
Comparator C10
By means of the threshold of 0.4 V the comparator C10 allows the PWM duty cycle to be
continuously controlled from 0 to 50%. As long as the ramp voltage at pin 15
(PWM RMP) is below this threshold the gate drive of the PWM section (pin 10,
PWM OUT) is turned off.
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4
Electrical Characteristics
4.1
Absolute Maximum Ratings
TA = – 25 to 85 °C
Parameter#
Symbol
Limit Values Unit
Remarks
min.
max.
VS
IZ3
VVREF
VROSC
VSYNC
VPFC FB
VPFC IAC
VAUX VS
VPFC VS
VPFC CL
VPWM SS
VPWM IN
VPWM RMP
VPWM CS
VPFC VC
IPFC VC
IPFC CS
IGND S
VPFC CC
IPFC CC
IOUT
– 0.3
VZ3
V
VZ3 = Zener voltage of Z3
–
50
mA
–
– 0.3
8
V
– 0.3
8
V
VVREF < VS
VROSC < VS
– 0.3
8
V
–
– 0.3
8
V
–
– 0.3
15
V
–
– 0.3
8
V
–
– 0.3
8
V
|IPFC VS| < 1 mA
–1
3
V
|IPFC CL| < 1 mA
– 0.3
8
V
VPWM SS < VVREF
– 0.3
8
V
–
– 0.3
8
V
VPWM RMP < VVREF
– 0.3
3
V
–
– 0.3
8
V
–
– 20
20
mA
–
–5
5
mA
–
–5
5
mA
–
– 0.3
8
V
–
– 20
20
mA
–
– 100 100
mA
–
PFC/PWM OUT peak
clamping current
IOUT
–
mA
VOUT = High
PFC/PWM OUT peak
clamping current
IOUT
– 500 –
mA
VOUT = Low
Junction temperature
TJ
– 40
°C
–
VCC supply voltage
Zener current of Z3
VREF voltage
ROSC voltage
SYNC voltage
PFC FB voltage
PFC IAC voltage
AUX VS voltage
PFC VS voltage
PFC CL voltage
PWM SS voltage
PWM IN voltage
PWM RMP voltage
PWM CS voltage
PFC VC voltage
PFC VC current
PFC CS current
GND S current
PFC CC voltage
PFC CC current
PFC/PWM OUT DC
current
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4.1
Absolute Maximum Ratings (cont’d)
TA = – 25 to 85 °C
Parameter#
Storage temperature
Thermal resistance
Thermal resistance
Symbol
TS
RthJA
RthJA
Limit Values Unit
Remarks
min.
max.
– 65
150
°C
–
–
60
K/W
P-DIP-20-5
–
70
K/W
P-DSO-20-1
Note: Absolute maximum ratings are defined as ratings, which when being exceeded
may lead to destruction of the integrated circuit. To avoid destruction make sure,
that for any pin except for pins PFC OUT and PWM OUT the currents caused by
transient processes stay well below 100 mA. For the same reason make sure, that
any capacitor that will be connected to pin 9 (VCC) is discharged before
assembling the application circuit. In order to characterize the gate driver’s output
performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided,
instead of referring just to a single parameter like the maximum gate charge or the
maximum output energy.
4.2
Operating Range
Parameter
VCC supply voltage
Symbol
VS
IZ3
Zener current
PFC/PWM OUT current IOUT
IPFC IAC
PFC IAC input current
fOUT
PFC/PWM frequency
TJ
Junction temperature
Limit Values Unit
Remarks
min.
max.
0
VZ3
V
0
50
mA
VZ3 = Zener voltage of Z3
Limited by TJ,max
–1
1.5
A
–
0
1
mA
–
15
200
kHz
–
– 25
125
°C
–
Note: Within the operating range the IC operates as described in the functional
description. In order to characterize the gate driver’s output performance
Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring
just to a single parameter like the maximum gate charge or the maximum output
energy.
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4.3
Characteristics
Supply Section
Parameter
Symbol
1)
Zener voltage
Zener current
Quiescent supply
current
VZ3
IZ3
IS
Limit Values
Unit
Test Condition
IZ3 = 30 mA
VS ≤ 15.5 V2)
VPWM SS = 0 V
RROSC = 51 kΩ
CL = 0 V
min.
typ.
max.
16.0
17.5
19.0
V
–
–
500
µA
–
–
12
mA
PFC enabled
PWM disabled
–
–
15
mA
VPWM SS = 6 V
RROSC = 51 kΩ
CL = 0 F
PFC enabled
PWM enabled
Supply current
IS
–
–
40
mA
VPWM SS = 6 V
RROSC = 51 kΩ
CL = 4.7 nF
PFC enabled
PWM enabled
1)
2)
See Figure 3
Design characteristics (not meant for production testing)
Note: The electrical characteristics involve the spread of values guaranteed within the
specified supply voltage and ambient temperature range TA from – 25 °C to 85 °C
Typical values represent the median values, which are related to production
processes. If not otherwise stated, a supply voltage of VS = 15 V is assumed.
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Undervoltage Lockout
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Power up,
rising voltage
threshold1)
VS,UP
13.0
14.0
14.5
V
–
Power down,
falling voltage
threshold1)
VS,DWN
10.5
11.0
11.5
V
–
Power up,
threshold current
IS,UP
–
23
100
µA
VS = VS,UP – 0.1 V
VPFC CL < 0.3 V2)
Stand-by mode
1)
2)
See Figure 3
To ensure the voltage fallback of pin PFC CL is disabled.
Internal Voltage Reference
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Trimmed reference
voltage
VREF
4.9
5.0
5.1
V
Measured at
pin PFC VC
Line regulation
∆VREF
–
–
40
mV
∆VS = 3 V
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External Voltage Reference
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
VVREF
∆VVREF
∆VVREF
IVREF
7.2
7.5
7.8
V
– 3 mA ≤ IVREF ≤ 0
–
–
50
mV
∆VS = 3 V
0
40
100
mV
∆IVREF = 2 mA
– 10
–6
–4
mA
VVREF = 6.5 V
IVREF
VVREF
–
–2
–
mA
VVREF = 0 V
–
6.6
–
V
–
VVREF
Shutdown hysteresis,
falling voltage threshold
–
6.2
–
V
–
td,VREF
–
500
–
ns
VVREF = 5 V2)3)
VPFC OUT = 3 V2)3)
VPWM OUT = 3 V2)3)
Unit
Test Condition
RROSC = 110 kΩ
RROSC = 51 kΩ
∆VS = 3 V
RROSC = 51 kΩ
Buffered output voltage
Line regulation
Load regulation
Maximum output
current1)
Short circuit current1)
Shutdown hysteresis,
rising voltage threshold
Shutdown delay
1)
2)
3)
See Figure 4
Design characteristics (not meant for production testing)
Transient reference value
Oscillator
Parameter
PFC/PWM frequency1)
PFC/PWM frequency1)
PFC/PWM frequency,
line regulation
Symbol
fOUT50
fOUT100
∆fOUT
Limit Values
min.
typ.
max.
43
50
57
kHz
87
100
113
kHz
–
–
1
%
5.4
5.6
V
–
VPFC RMP 5.0
Minimum ramp voltage VPFC RMP 0.8
–
SYNC, low level voltage VSYNC
1.1
1.4
V
–
–
0.4
V
–
SYNC, high level voltage VSYNC
3.5
–
VVREF V
–
–
–
20
µA
–
–
150
µA
Maximum ramp voltage
SYNC, input current
1)
ISYNC
VSYNC < 0.4 V
VSYNC = 3.5 V
See Figure 5
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PFC Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
VPFC OUT = 2 V3)
RROSC = 51 kΩ
CL = 4.7 nF
0.9 IPFC CS
IPFC IAC = 100 µA
VPFC VC = 6 V
Max duty cycle1)
Don,PFC
91
94
98
%
Multiplier throttling
(OTA2), threshold
voltage2)
VPFC VS
5.2
5.5
5.8
V
OTA1 disabled
Overvoltage protection
(C6), rising voltage
threshold
VPFC VS
5.8
6
6.2
V
–
Overvoltage protection
(C6), falling voltage
threshold
VPFC VS
5.3
5.5
5.7
V
–
Overvoltage protection
(C6), turn-off delay
td,OV
–
2
–
µs
VPFC VS = 6.5 V3)4)
VPFC OUT = 3 V3)4)
Broken wire detection
(C2), threshold voltage
VPFC VS
0.93
1
1.07
V
–
Voltage sense, input
current
IPFC VS
0.2
0.45
0.7
µA
VPFC VS = 1 V
Current limitation (C3),
threshold voltage
VPFC CL
0.93
1
1.07
V
–
Current limitation (C3),
input current
IPFC CL
1
–
10
µA
VPFC CL = 1 V
Current limitation (C3,
D4), clamping voltage
VPFC CL
– 0.9
–
– 0.1
V
IPFC CL = – 500 µA
Current limitation (C3),
turn-off delay
td,CL
30
–
150
ns
VPFC CL = 0.75 V3)
VPFC OUT = 3 V3)
CL = 4.7 nF
1)
2)
3)
4)
See Figure 6
See Figure 9
Transient reference value
Design characteristics (not meant for production testing)
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Multiplier
Parameter
Input current
Input voltage
Exponential function,
threshold voltage
Symbol
IPFC IAC
VPFC VC
VPFC VC
Limit Values
Unit
Test Condition
min.
typ.
max.
0
–
1
mA
–
0
–
6.7
V
–
–
1.1
–
V
1)2)
Maximum output current IPFC CS
– 320 – 420 – 550 µA
OTA1 disabled
Output current3)
–
IPFC IAC = 0 A
VPFC VC = 2 V
IPFC CS
– 100 – 500 nA
OTA1 disabled
–
– 1.2
–
µA
IPFC IAC = 25 µA
VPFC VC = 2 V
OTA1 disabled
–
– 10
–
µA
IPFC IAC = 25 µA
VPFC VC = 4 V
OTA1 disabled
–
– 40
–
µA
IPFC IAC = 100 µA
VPFC VC = 4 V
OTA1 disabled
–
– 150 –
µA
IPFC IAC = 400 µA
VPFC VC = 4 V
OTA1 disabled
–
– 170 –
µA
IPFC IAC = 100 µA
VPFC VC = 6 V
OTA1 disabled
1)
2)
3)
Design characteristics (not meant for production testing)
For input voltages below this threshold the multiplier output current remains constant. For input voltages above
this threshold the output rises exponentially (see Figure 8).
See Figure 7
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Operational Transconductance Amplifier (OTA1)
Parameter
Symbol
Auxiliary power supply,
threshold voltage1)
VAUX VS
Input current
IAUX VS
Output current
1)
Limit Values
min.
typ.
max.
4.8
5.0
5.2
Unit
Test Condition
V
IPFC CS = – 1 µA
Multiplier disabled
IPFC CS
–
–
15
µA
– 20
–
–
µA
–
0
–
µA
–
– 30
–
µA
VAUX VS > 5.2 V
VAUX VS < 4.8 V
VAUX VS > 5.2 V1)
VAUX VS < 4.8 V
For input voltages below this threshold the output current is linearly increasing until at ca. 4.8 V the maximum
output current is reached.
Operational Transconductance Amplifier (OTA3)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Offset compensation,
threshold voltage
VPFC VC
1.1
1.2
–
V
–
Input current
IPFC VC
IGND S
–1
–
–
µA
1)
–
0
–
µA
–
– 10
–
µA
VPFC VC > 1.2 V
VPFC VC < 1.1 V
Output current
1)
Design characteristics (not meant for production testing)
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Voltage Amplifier (OP1)
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
VOff
IPFC FB
APFC VC
VPFC FB
VPFC FB
–4
–
4
mV
1)
–1
–
1
µA
VPFC FB = 4 V
–
85
–
dB
2)
0
–
6
V
–
4.9
5
5.1
V
–
Output, maximum
voltage
VPFC VC
6.3
–
VVREF V
IPFC VC = – 500 µA
Output, minimum
voltage
VPFC VC
0.5
–
1.1
V
IPFC VC = 500 µA
Output, short circuit
source current
IPFC VC
–
– 10
–
mA
Output, short circuit sink IPFC VC
current
–
10
–
mA
VPFC VC = 0 V
VPFC FB = 4.9 V
VPFC VC = 6.4 V
VPFC FB = 5.1 V
Offset voltage
Input current
Open loop gain
Input voltage range
Voltage sense,
threshold voltage
1)
2)
Guaranteed by wafer test
Design characteristics (not meant for production testing)
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Current Amplifier (OP2)
Parameter
Symbol
VOff
IPFC CS
Input current
IGND S
Open loop gain
APFC CC
Gain bandwidth product fT
Offset voltage
Phase margin
ϕ
Common mode voltage VCMVR
range
Limit Values
Unit
Test Condition
min.
typ.
max.
–5
–1
3
mV
–
– 500 –
500
nA
–
–
110
–
dB
–
–
2.5
–
MHz
1)
–
60
–
°
1)
– 0.2
–
0.5
V
1)
0.4
–
1.0
V
IPFC CS = 500 µA
IGND S = 500 µA
Clamped input voltage,
upper threshold
(D2, D3)
VPFC CS
VGND S
Clamped input voltage,
lower threshold (D1)
VPFC CS
Output, maximum
voltage
VPFC CC
6.3
–
VVREF V
IPFC CC = – 500 µA
Output, minimum
voltage
VPFC CC
0.5
–
1.1
V
IPFC CC = 500 µA
Output, short circuit
source current
IPFC CC
–
– 10
–
mA
Output, short circuit sink IPFC CC
current
–
10
–
mA
VPFC CC = 0 V
VPFC CS = 0 V
VGND S = 0.5 V
VPFC CC = 6.5 V
VPFC CS = 0.5 V
VGND S = 0 V
1)
Multiplier, OTA1
and OTA3 disabled
– 0.9
–
– 0.1
V
IPFC CS = – 500 µA
Multiplier and OTA1
disabled
Design characteristics (not meant for production testing)
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PWM Section
Parameter
Symbol
Undervoltage protection (C4), VPFC VS
threshold voltage
Limit Values
Unit Test Condition
min.
typ.
max.
3.8
4.0
4.2
V
–
Bias control (C5),
rising voltage threshold
VBC,Th
–
0.45
–
V
–
Bias control (C5),
falling voltage threshold
VBC,Th
–
0.4
–
V
–
Softstart (I1),
charging current
II1
20
30
40
µA
–
Softstart, maximum voltage
VPWM SS
VPWM IN
R3
AOP3
VRMP
–
6.7
–
V
–
0.4
–
7.4
V
–
75
100
150
kΩ
–
–
5
–
V/V –
0.36
0.4
0.5
V
–
VRMP
VV1
ZRMP
–
6.5
–
V
–
–
1.5
–
V
–
–
10
–
kΩ
–
Input voltage
PWM IN – GND resistance
Ramp (OP3), voltage gain
Ramp (C10), pulse start
threshold voltage
Ramp, maximum voltage
Ramp (V1), voltage offset
Ramp (R1),
output impedance
Maximum duty cycle
Don,PWM 41
–
50
%
VPWM OUT = 2 V1)
RROSC = 51 kΩ
CL = 4.7 nF
Current sense (C9),
voltage threshold
VCS,Th
0.9
1.0
1.1
V
–
Current sense (C9),
overload turn-off delay
td,CS
30
–
250
ns
VPWM CS = 1.25 V1)
VPWM OUT = 3 V1)
CL = 4.7 nF
1)
Transient reference value
Version 2.0
27
28 Feb 2000
TDA 16888
Gate Drive (PWM and PFC Section)
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
VOUT
–
–
1.2
V
VS = 5 V
IOUT = 5 mA
–
–
1.5
V
–
0.8
–
V
–
1.6
2.0
V
– 0.2 0.2
–
V
10
11
12
V
10.0
10.5 –
V
8.8
–
V
–
150 –
ns
–
100 –
ns
–
30
–
ns
–
40
–
ns
Output current, rising edge3) IOUT
–1
–
–
A
Output current, falling edge3) IOUT
–
–
1.5
A
VS = 5 V
IOUT = 20 mA
IOUT = 0 A
IOUT = 50 mA
IOUT = – 50 mA
VS = 16 V
tH = 10 µs
CL = 4.7 nF
VS = 12 V
tH = 10 µs
CL = 4.7 nF
VS = VS,DWN + 0.2 V
tH = 10 µs
CL = 4.7 nF
VOUT = 2 V … 8 V2)
CL = 4.7 nF
VOUT = 3 V … 6 V2)
CL = 4.7 nF
VOUT = 9 V … 3 V2)
CL = 4.7 nF
VOUT = 9 V … 2 V2)
CL = 4.7 nF
CL = 4.7 nF4)
CL = 4.7 nF4)
Output, minimum voltage
Output, maximum voltage
Rise time1)
Fall time
1)
2)
3)
4)
VOUT
tr
tf
–
See Figure 13
Transient reference value
The gate driver’s output performance is characterized in Figure 14, Figure 15, Figure 16 and Figure 17.
Design characteristics (not meant for production testing)
Note: If not otherwise stated the figures shown in this section represent typical
performance characteristics.
Version 2.0
28
28 Feb 2000
TDA 16888
AED02462
Ι VCC
ΙS
Ι S, UP
V S, DWN
Figure 3
V S, UP
V Z3
V VCC
Undervoltage Lockout Hysteresis and Zener Diode Overvoltage
Protection
Ι VREF
AED02463
-8
mA
-7
-6
-5
-4
-3
-2
-1
0
Figure 4
Version 2.0
0
1
2
3
4
5
6
7 V
V VREF
8
Foldback Characteristic of Pin 2 (VREF)
29
28 Feb 2000
TDA 16888
AED02464
400
kHz
f OUT
100
10
10
100
kΩ 500
R OSC
Figure 5
PFC/PWM Frequency
AED02465
100
%
Don, PFC, max
95
90
85
80
0
100
200
300
kΩ 400
R OSC
Figure 6
Version 2.0
Maximum PFC Duty Cycle
30
28 Feb 2000
TDA 16888
AED02466
500
µA
VPFC VC = 7 V
Ι PFC CCS
400
6V
5V
4V
300
200
3V
100
2V
0
0
0.2
0.4
0.6
0.8
mA 1
Ι PFC IAC
Figure 7
Multiplier Linearity
AED02356
500
µA
Ι PFC CCS
Ι PFC IAC = 800 µA
400 µA
200 µA
100 µA
50 µA
25 µA
400
300
200
100
0
Figure 8
Version 2.0
0
1
2
3
4
5
6
V 7
VPFC VC
Multiplier Dynamic
31
28 Feb 2000
TDA 16888
AED02467
500
µA Ι PFC IAC > 300 µA
VPFC VC = 6 V
Ι PFC CCS
250 µA
400
200 µA
300
150 µA
200
100 µA
100
50 µA
0
5.0
5.25
5.5
5.75
V 6.0
VPFC VS
Figure 9
Multiplier Throttling by OTA2
AED02468
100
dB
φ
A PFC VC
80
-30
φ
60
Version 2.0
A PFC VC
-60
40
-90
20
-120
0
10 -2
Figure 10
0
deg
10 -1
10 0
10 1
10 2
10 3
10 4
10 5
-150
10 6 Hz 10 7
Frequency
Open Loop Gain and Phase Characteristic of Voltage Amplifier OP1
32
28 Feb 2000
TDA 16888
AED02469
120
dB
A PFC CC
100
φ
-30
φ
A PFC CC
80
-60
60
-90
40
-120
20
-150
0
10 -2
Figure 11
0
deg
10 -1
10 0
10 1
10 2
10 3
10 4
10 5
-180
10 6 Hz 10 7
Frequency
Open Loop Gain and Phase Characteristic of Current Amplifier OP2
AED02470
V1
VPWM CS
V1 /2
0
4V1
VPWM RMP
3V1
VPWMCS = 0
2V1
V1
0
T/2
0
T
Time
Figure 12
Version 2.0
PWM Ramp Composition Scheme
33
28 Feb 2000
TDA 16888
AED02471
12
V
VPFC OUT
10
8
6
4
2
0
0
0.1
0.2
µs 0.4
0.3
Time
Figure 13
Rising Edge of Driver Output
AED02542
150
PD
RL = 0 Ω
RL = 1 Ω
RL = 2 Ω
RL = 5 Ω
R L = 10 Ω
mW
100
50
f OUT = 15 kHz
P D0 = 0.194 W
0
0
10
20
30
40
nF
50
CL
Figure 14
Power Dissipation of Single Gate Driver at fOUT = 15 kHz
Version 2.0
34
28 Feb 2000
TDA 16888
AED02543
500
PD
RL = 0 Ω
RL = 1 Ω
RL = 2 Ω
RL = 5 Ω
R L = 10 Ω
mW
400
300
200
100
f OUT = 50 kHz
P D0 = 0.197 W
0
0
10
20
30
40
nF
50
CL
Power Dissipation of Single Gate Driver at fOUT = 50 kHz
Figure 15
AED02544
1
PD
RL = 0 Ω
RL = 1 Ω
RL = 2 Ω
RL = 5 Ω
R L = 10 Ω
mW
0.8
0.6
0.4
0.2
f OUT = 100 kHz
P D0 = 0.201 W
0
0
10
20
30
40
nF
50
CL
Figure 16
Version 2.0
Power Dissipation of Single Gate Driver at fOUT = 100 kHz
35
28 Feb 2000
TDA 16888
AED02545
1.5
PD
RL = 0 Ω
RL = 1 Ω
RL = 2 Ω
RL = 5 Ω
R L = 10 Ω
mW
1.0
0.5
f OUT = 200 kHz
P D0 = 0.212 W
0
0
10
20
30
40
nF
50
CL
Figure 17
Version 2.0
Power Dissipation of Single Gate Driver at fOUT = 200 kHz
36
28 Feb 2000
TDA 16888
VOSC
CLK OSC
CLK OUT
VPFC RMP
VPFC CC
VPFC OUT
t on, max
VPWM RMP
VPWM IN
VBC, Th
VPWM OUT
t on, max
Time
Figure 18
Version 2.0
AET02546
Timing Diagram without Synchronization
37
28 Feb 2000
TDA 16888
VOSC
VSYNC
CLK OSC
CLK OUT
VPFC RMP
VPFC CC
VPFC OUT
t on, max
VPWM RMP
VPWM IN
VBC, Th
VPWM OUT
t on, max
Time
Figure 19
Version 2.0
AET02547
Timing Diagram with Synchronization (fSYNC > fOSC)
38
28 Feb 2000
TDA 16888
VOSC
VSYNC
CLK OSC
CLK OUT
VPFC RMP
VPFC CC
VPFC OUT
t on, max
VPWM RMP
VPWM IN
VBC, Th
VPWM OUT
t on, max
Time
Figure 20
Version 2.0
AET02548
Timing Diagram with Synchronization (fSYNC < fOSC)
39
28 Feb 2000
TDA 16888
5
Package Outlines
GPD05587
P-DIP-20-5
(Plastic Dual In-line Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Version 2.0
40
Dimensions in mm
28 Feb 2000
TDA 16888
1.27
x
8˚ ma
7.6 -0.2 1)
+0.09
0.35 x 45˚
0.23
2.65 max
2.45 -0.2
0.2 -0.1
P-DSO-20-1
(Plastic Dual Small Outline)
0.4 +0.8
0.35 +0.15 2)
0.2 24x
20
0.1
10.3 ±0.3
11
GPS05094
1 12.8 1) 10
-0.2
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Version 2.0
41
GPS 05094
Index Marking
Dimensions in mm
28 Feb 2000
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere Anstrengungen gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Quality takes on an all encompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Dazu gehört eine bestimmte
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
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Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.
Version 1.1 , March 2001
Application Note
AN-TDA16888-0-010323
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Author:
Michael Herfurth
Published by Infineon Technologies AG
http://www.infineon.com
Power Management & Supply
N e v e r
s t o p
t h i n k i n g
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
150W Output: 5V/18A; 12V/4A; -12V/1A; Standby: 5V/100mA
Operating Frequency: 100kHz
Contents:
1.Circuit description...................................................................
2. Circuit diagram.......................................................................
3. Test results.............................................................................
4. Bill of materials......................................................................
5. Control PCB layout................................................................
6. Power PCB layout..................................................................
7. Transformer design...............................................................
8. Smoothing choke design......................................................
9. Boost inductor design...........................................................
10. RFI choke design.................................................................
11. Picture of testboard.............................................................
2 of 20
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6
7
8
11
12
13
14
15
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AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Circuit description
Multioutput single transistor forward converter with boost PFC preconverter
The power supply for a PC using up to 150 W of power must, for example, provide the following
voltages: 5V/18A; 12V/4A; -12V/0.7A; -5V/0,3A; and Standby 5V/0.1A. If any of the mains systems
in use around the world may be used as a power source, then an input voltage range of 90V to 270V
AC is required, taking into account the relevant tolerances.
The application circuit using the TDA 16888 is able to cover universal input voltage range mentioned
above (if required). In this circuit a boost converter (Q1, L2, D5, C3) works as an active harmonic filter
to provide power factor correction, intermediate circuit voltage stabilization and to supply the primary
and secondary side control logic in normal and standby operation. In addition, the bridging time for
dips in the mains voltage is not dependent on the mains voltage level. How the IC works in a typical
application circuit is described below.
Start up
When the mains voltage is switched on, the smoothing capacitor C3 is charged by a current pulse, the
current being limited by the winding resistances of the chokes and NTC resistor R36. Start-up
capacitor C11A is charged by a low current (<1mA) through resistors R2 and R43. Once the switch-on
threshold (14V) is reached at pin 19, the TDA 16888 changes from the passive to the active state. In
the passive state the IC draws a maximum current of 100µA while monitoring the switching thresholds
and actively maintaining the driver outputs at the L-level. In the active state the chip first checks
whether the intermediate circuit voltage at pin 19 lies between 20% and 120% of its nominal value
(e.g. between 80V and 480V for a nominal value of 400V). If this is the case, the chip concludes that
monitoring for the intermediate circuit voltage is connected (FMEA) and there is no risk to operation
from an overvoltage.
If the intermediate circuit voltage is found to be satisfactory, and no excess current is detected at pin
6, then the PFC converter starts working at half the rated frequency to cut the IC current consumption.
During this process the TDA 16888 is initially powered from the start-up capacitor C11A until the boost
converter starts to supply it, or, should the IC switch-off threshold (11V) be reached first, it switches
into the passive state and a new start-up attempt is initiated. As soon as the intermediate circuit
voltage has reached 80% of its nominal value, the PWM also starts running, with both converter
sections now operating at the rated frequency. A soft-start procedure is used for the PMW converter,
the rise time being set using C14 at pin 13.
If the voltage at pin 13 is less than 0.4V, the chip interprets this condition as standby mode, and shuts
off the PWM section. In standby mode the PFC converter again works at half the rated frequency to
reduce current consumption.
While the MOSFET Q1is switching, a modulated AC voltage appears at the secondary windings of
choke L2. The voltage across the main winding of choke L2 varies during rated operation from 400V
when Q1 is cut off and the AC input voltage passes through zero, to 400V when Q1 is conducting and
the maximum input voltage is at its peak value. The lowest voltage across the main winding (±200V)
arises when the input voltage is exactly half as large as the intermediate circuit voltage. This is why
the standby and IC supply voltages are derived from bridge rectification of the auxiliary windings on
L2, in order to use both the cut-off and conduction phase of the inductance. The voltage regulators IC5
and Q3/D11 are required because of the variation by a factor of 2 in the dc voltage obtained.
When the PFC converter is run up, the intermediate circuit voltage overshoots. Under low load it takes
a considerable time to return to its nominal level, because of the slow discharge of the smoothing
capacitor C3. During this period the voltage regulator would cut off the MOSFET Q1(up to more than
100ms), which would prevent the control logic being supplied from the boost converter choke. This is
why the TDA 16888 has a further control loop, using input pin 20, in addition to the two control loops
for the intermediate circuit voltage and the input current. A second output path from the boost
converter (D6, C4, R2) is taken via potential divider R1, R27 to detect whether Q1 is operating.
3 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
This works by the voltage at C4 being set using voltage divider R1, R27 to the nominal value of the
intermediate circuit voltage, or a few percent below. The short time constant of the second output path
from the boost converter (C4≈10nF, R2≈500kΩ) means that any drop in the voltage at C4 is rapidly
detected, and the MOSFET Q1 switched on via the PFC current regulator. If necessary this is done
with such short pulses that the voltage at the main output from the boost converter does not rise, even
with no load at all. The limited controllability of the boost converter during no-load conditions means
that the power available at the standby output is limited. For example 5V/100mA is provided with a
quite good efficiency.
Normal operation
The oscillator frequency is set by just one external resistor R24. The ramp voltages for the oscillator
and the pulse width modulation (PWM) of the PFC section are generated across integrated capacitors.
The duty cycle of the PFC section varies from 0 to over 90%, and for the PWM section from 0 to 50%
maximum. During one switching period, the PFC MOSFET Q1 switches on first. The PWM MOSFET
Q2 switches on half a period later. For greater reliability, flip-flops are used to control this timing
sequence. The oscillator therefore runs at twice the rate of the external operating frequency. By
integrating the capacitors, external circuitry is not required, and so the current consumption is reduced
because of the smaller capacitances.
The waveform of the rectified, unsmoothed mains voltage is detected across resistors R4A, R4B, and
applied to the first input of an integrated multiplier. The output voltage from the PFC voltage control
amplifier is taken to at the second input to the multiplier. The current at the output of the multiplier, pin
4, is a reference value having the waveform of the rectified mains voltage and an amplitude controlled
by the voltage regulator. The PFC current regulator controls the rectified mains current such that the
voltage drop across shunt R6 assumes exactly the same value as the voltage drop across R5
produced by the output current from the multiplier. The output current from the PFC current regulator
(pin 3) sets up the duty cycle for the MOSFET Q1 by comparison with an internally generated ramp
voltage.
The intermediate circuit voltage is regulated by the PFC voltage regulator (pin 17, pin 18) at a level
that is greater than or equal to the peak value of the maximum input voltage (270V⋅√2= 382V). An
intermediate circuit voltage of 380V is often chosen, because one must expect a maximum voltage of
this magnitude even without a PFC converter. A 450V type smoothing capacitor (C3) is used,
however, to ensure that even under transient conditions, the voltage remains below the permitted
capacitor voltage. In this case it is worth increasing the intermediate circuit voltage to 410V, and to
design the onset threshold for overvoltage limiting to be 430V (R11, R12 to give 5.5V at pin 19). The
intermediate circuit voltage still remains below 450V during transient conditions, and the benefit lies in
the 40% higher hold time, which can be bridged if the mains drops out.
The PWM converter is designed to work as a single-ended forward converter. The turn-on time is
determined by the oscillator, as soon as the voltage at the soft start input pin 13 and the control input
pin 14 exceeds 0.4V. After the soft start phase, the voltage at control input pin 14 together with the
ramp voltage at pin 15 controls the turn-off time. An improved current ramp control technique (current
mode control) is used here, where the ramp voltage has an amplitude 5 times higher than those
traditionally used. The current in the Q2 source path is also measured across shunt resistor R15, and
detected at pin 11. At a voltage of 1V at pin 11, the integrated overcurrent comparator switches off
MOSFET Q2. The signal at pin 11 is also amplified by a factor of 5 by a linear amplifier, and taken via
an internal 10k resistor to pin 15. A base ramp voltage with an amplitude of 1.5V is produced across
capacitor C13 connected to this pin, even when there is no transistor current (slope compensation).
This voltage can rise to over 6V when the maximum current flows through Q2. This allows pulse width
modulation at higher signal levels, enabling stable operation right up to no-load conditions.
The transformer Tr1 in the forward converter works at the pre-regulated intermediate circuit voltage.
This means that a higher transformer ratio can be selected, reducing the current load for the
MOSFET. Furthermore, a larger duty cycle can be set during normal operation because there is a
smaller variation range for the input voltage. The magnetization energy can be fed back into the
smoothing capacitor using a demagnetization winding and demagnetization diode D7.
4 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
In forward converters with universal input voltage range this is not possible without pre-regulation, or
causes significant losses in the required demagnetization network. In our application circuit,
overvoltage peaks across MOSFET Q2 and diode D7 are efficiently limited using diodes D22 and D27
and network C31, R40. On the secondary side there is one rectifying and one freewheeling diode (D8,
D9; D20, D21) for each output voltage. A damping network (e.g. R41, C29; R42, C30) is connected in
parallel with every diode, to attenuate commutation-induced overvoltage spikes and transients.
Another RC element (R47, C34) damps the voltage decay in intermittent dc flow, to avoid irregular
premagnetization of the smoothing choke. The output voltages are taken via separate windings on a
common smoothing choke L3 to convert the switched voltages into a flow of current. The smoothing
capacitors (e.g. C15, C28) reduce the ripple on the output voltage and serve as a storage device when
the load changes rapidly. For high output currents it is advisable to divide up the smoothing
capacitance with small inductances (L5, L6), to compensate for the equivalent series resistance (ESR)
of the capacitors.
The output voltage with the highest stability specification is controlled directly by regulating amplifier
IC2 and optocoupler IC3. The other output voltages are stabilized indirectly by the choice of winding
ratio for transformer Tr1 and choke L3 according to the ratio of the output voltages. An extra
comparator IC6 and optocoupler IC4 monitor the standby output voltage. When the standby switch is
closed, the PWM converter is only started once the PFC converter has produced at least 90% of the
nominal voltage at the standby output. Standby operation can be initiated by opening the switch.
Transistor Q4 with low-pass filter at its base, prevents noise spikes and leakage currents from the
optocoupler from discharging the soft-start capacitor during normal operation.
Protective features
When a short circuit occurs on the output side, the primary current is limited by measuring the drop
across shunt R15. In applications with several output voltages, this only works as a short-term
protective measure, because the output rectifier, for example, cannot withstand the overload. Extra
protection can be provided by monitoring the output voltages for a minimum value, with a delayed
switch into standby mode.
To deal with overshoots in the intermediate circuit voltage, a switch-off threshold can be set as
required (e.g. 5% above the nominal value) using potential divider R11, R12. If this is exceeded than
the PFC converter cuts off the power to the intermediate circuit.
When transient mains surges occur which charge the smoothing capacitor C3 to 10% above the PFC
switch-off threshold, the PWM MOSFEET Q2 is also cut-off to protect the power supply unit. If the
mains voltage rises still further, then varistor R30 can limit it. Using these protective devices, the
application circuit can withstand transient mains surges of 600V and more.
Figure 1:
A 150W PC power supply
design with power factor
correction using TDA 16888
fits inside a typical PC
power supply silver box.
5 of 20
AN-TDA16888-0-010323
V1.1
6 of 20
C18
+
Q3
L4
D10
R1 =
R36
C24
R27
D11
R28
D12...D15
RFI
L1
= means
two resistors in series
R29
90V270V AC
Fuse
6
1
4
=
+
-
3
C7
C13
15
PWM
8
13
C3
14
=
C22
R35
10
PWM
Q4
11
IC1
R34
R18
R35A
C22A
C21
R32
Voltage EA
R23
C29 R41
D9
D8
C33 R45
D21
D20
D24
SIPMOS
1000V
Q2
R17
18
C5
D7
R16 R15
D27
D22
C31
Tr.1
C20
=
+
-
= C6
R14
R40
17
R13
Overvoltage
19
C41
R12
R11
Softstart
7
C14
R9
R10
C4
C3A
VBUS = 410V
C19
IC5
R22
L3
C15
C36
R21
IC6
C39 C42
R33
IC4
+
C38
C17
R39
L3
C34
R47
L3
C35
R46
IC2
C16
IC3
C30
R42
C32
R44
D23
L5
C28
L6
C37
C27
R19
R20
+
+
IC6
+
C38A
OFF =
STANDBY
+
+
R48
R38
R37
Circuit Diagram of single transistor multioutput forward converter with PFC
R24
20 16
OSC
D6
D5
R62
D16...D19
R43
Q1
R8
Current EA
5
+
R25
C12
2
9
C23
VREF
R26
C8
R5
R7
STANDBY EA
C9A
AUX1
L2
SIPMOS
C2 600V
R6
Startup
UVLO
12
R3
R4B
D1...D4
R4A
Currentlimitation
C10
C11
C11A
+
= R2
C26
R30
C1
C25
-
R36A
R31
5V
18A
12V
4A
-12V
0,7A
-5V/0,3A
5V
0,1A
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
AN-TDA16888-0-010323
V1.1
7 of 20
AN-TDA16888-0-010323
V1.1
0,85 196,0 99,4 4,0
0,59 135,0 98,9 4,5
0,24 51,0 94,0 14,0
4,6
2,5
0,73 196,0 98,9 4,4
0,51 134,0 98,3 5,1
0,21 51,0 90,4 16,0
4,4
2,5
230
230
230
230
230
270
270
270
270
270
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
380,00
5,00
5,00
5,00
5,00
0,00
5,00
5,00
5,00
5,00
0,00
5,00
5,00
5,00
5,00
0,00
5,00
5,00
5,00
5,00
0,00
18,10
18,00
5,00
0,00
18,10
18,00
5,00
0,00
18,10
18,00
5,00
0,00
18,10
18,00
5,00
0,00
12,60
13,10
12,20
12,10
0,00
12,60
13,10
12,20
12,10
0,00
12,60
13,10
12,20
12,10
0,00
12,60
13,10
12,20
12,10
0,00
V BUS V out1 I out1 V out2
V DC V DC
A
V DC
380,00 5,00 18,10 12,60
380,00 5,00 18,00 13,10
380,00 5,00 5,00 12,20
380,00 5,00 0,00 12,10
380,00 0,00
0,00
4,00
1,00
1,00
0,00
4,00
1,00
1,00
0,00
4,00
1,00
1,00
0,00
4,00
1,00
1,00
0,00
I out2
A
4,00
1,00
1,00
0,00
-12,70
-13,40
-12,30
-11,90
0,00
-12,70
-13,40
-12,30
-11,90
0,00
-12,70
-13,40
-12,30
-11,90
0,00
-12,70
-13,40
-12,30
-11,90
0,00
V out3
V DC
-12,70
-13,40
-12,30
-11,90
0,00
0,70
0,10
0,10
0,00
0,70
0,10
0,10
0,00
0,70
0,10
0,10
0,00
0,70
0,10
0,10
0,00
I out3
A
0,70
0,10
0,10
0,00
-5,00
-5,00
-5,00
-5,00
0,00
-5,00
-5,00
-5,00
-5,00
0,00
-5,00
-5,00
-5,00
-5,00
0,00
-5,00
-5,00
-5,00
-5,00
0,00
V out4
V DC
-5,00
-5,00
-5,00
-5,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,00
0,30
0,00
0,00
0,00
I out4
A
0,30
0,00
0,00
0,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
5,00
VStby
V
5,00
5,00
5,00
5,00
5,00
Test Results of single transistor multioutput forward converter with PFC
1,10 198,0 99,7 3,6
0,76 136,0 99,5 1,5
0,29 51,0 97,0 12,5
4,5
2,6
180
180
180
180
180
THD
%
4,6
3,5
2,8
1,70 205,0 99,9 3,4
1,17 140,0 99,9 2,8
0,44 53,0 99,4 6,0
4,7
2,7
PF
%
99,8
99,9
99,8
120
120
120
120
120
P in
W
220,0
146,0
54,0
4,8
2,7
I in
A rms
2,45
1,62
0,60
V in
V AC
90
90
90
90
90
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
0,10
IStby
A
0,10
0,10
0,10
0,10
0,10
150,3
104,9
38,9
0,5
0,5
150,3
104,9
38,9
0,5
0,5
150,3
104,9
38,9
0,5
0,5
151,8
104,9
38,9
0,5
0,5
76,7
78,3
76,3
76,7
77,7
76,3
75,9
77,2
76,3
74,0
75,0
73,5
P out Efficiency
W
%
151,8
69,0
104,9
71,9
38,9
72,1
0,5
0,5
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Bill of Materials
Component
Value
IC 1
IC 2
IC 3
IC 4
IC 5
IC 6
* TDA 16888
TL 431 C
CNY 17 F-3
CNY 17-3
TLE 4264 G
TL 431 C
Q1
Q2
Q3
Q4
BUZ 91
(600V/ 0,8 Ω)
BUZ 51
(1000V/ 4Ω)
BSS 129
(240V/ 20Ω, Depletion)
* BC 338 (30V/ 800mA, NPN)
D 1...D 4
D5
D6
D7
D 8, D 9
D 10
D 11
D 12...D 15
D 16...D 19
D 20, D 21
D 22
D 23, D 24
D 27
L1
L2
Order-Nr.
Manufacturer
Q67000-A9284
Infineon
TI
Infineon
Infineon
Infineon
TI
Q62703-N50
Q62703-N88
Q67006-A-9139
GR B250 C5000/3300
STTA506D
(600V; 5A; 20ns)
MUR 160
(600V; 1A; 75ns)
BYT 11-1000
(1000V; 1A; 100ns)
MBR 2535 CTL (Schottky 35V; 2x 12,5A)
1N4148
BZX 83 C13
UF 4003
(100V; 1A; 50ns)
UF 4003
(100V; 1A; 50ns)
BYV 32-100
(100V; 2x 10A; 25ns)
BYT 11-1000
(1000V; 1A; 100ns)
MUR 120
(200V; 1A; 50ns)
BYT 11-1000
(1000V; 1A; 100ns)
2x 6,8mH/ 2A
1mH
E36/11; N27; GAP 2mm
100turns, 0,6mm ∅
AUX 1: 8turns 0,33mm ∅
AUX 2: 5turns 0,33mm ∅
Q67078-S1342-A2
Q67078-S1344-A2
Q67000-S116
Q62702-C314
Infineon
Infineon
Infineon
Infineon
ST
Motorola
ST
Motorola
B82724-J2202-N1
B66389-G1000-X127
GI
GI
Eupec, Philips
ST
Motorola
ST
EPCOS
EPCOS
B66389-G1000-X127
EPCOS
B66317-G1000-X127
EPCOS
L5
L6
Fuse
(W3) E36/11, N27, GAP 2mm
W3: 9turns 2x 2x0,9mm ∅
W1: 21turns
0,7mm ∅
W2: 21turns
0,3mm ∅
500µH EF25, N27, GAP 2mm
90turns, 0,45mm ∅
1µH
9turns 2mm ∅
airchoke
1µH
10turns 1,2mm ∅
airchoke
2,5A MT
Component
Value
Order-Nr.
Manufacturer
T1
E36/11, N27, without GAP
Primary: 68 turns 0,40mm ∅
Demagn.: 68 turns 0,22mm ∅
Sec.1:
3 turns 4x 0,8mm ∅
Sec.2:
7 turns 2x 0,8mm ∅
Sec.3:
7 turns 0,4mm ∅
B66389-G-X127
EPCOS
L3
L4
8µH
8 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Component
Value
Order-Nr.
Manufacturer
C1
C2
C3
C 3A
C4
C5
C6
C7
C8
C9
C 9A
C 10
C 11
C 11A
C 11B
C 12
C 13
C 14
C 15
C 16
C 17
C 18
C 19
C 20
C 21
C 22
C 22A
C 23
C 24
C 25, C 26
C 25, C 26
C 27
C 28
C 29
C 30
C 31
C 32
C 33
0,33µF
275V AC, X2
not assembled
150µF/ 450V
Elko
0,15µF/ 630V
MKP
10nF/ 1000V
MKP
47nF/63V
MKT
100nF/63V
MKT
1nF/63V
MKT
10nF/63V
MKT
not assembled
6,8nF/63V
MKT
10pF/100V
CG
0,47µF/63V
MKT
100µF/25V
Elko
47nF/50V
X7R
0,15µF/63V
MKT
100pF/50V
CG
100nF/63V
MKT
2200µF/10V
Elko
68nF/63V
MKT
2,2nF/63V
MKT
100µF/63V
Elko
470µF/35V
Elko
100µF/25V
Elko
220pF/50V
CG
4,7nF/63V
MKT
10nF
MKT
not assembled
0,33µF
275V AC, X2
3,3nF 250V AC, Y2, lead spacing 15mm
3,3nF 250V AC, Y2, lead spacing 10mm
4,7nF/63V
MKT
2200µF/10V
Elko
1nF/63V
MKT
1nF/63V
MKT
1nF/630V
Position R 40
2,2nF/63V
MKT
2,2nF/63V
MKT
B81133-D1334-M
EPCOS
B43501-J5157-M
B32652-A6154-K
B32652-A103-K
B32529-C473-K
B32529-C104-K
B32529-C102-K
B32529-C103-K
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
B32529-C682-K
B37979-G1100-J51
B32529-C474-K
B41283-C5107-T90
B37981-F5473-K51
B32529-C154-K
B37979-G5101-J51
B32529-C104-K
B41822-A3228-M
B32529-C683-K
B32529-C222-K
B41822-A8107-M
B41822-A7477-M
B41822-A1107-M
B37979-G5221-J51
B32529-C472-K
B32529-C103-K
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
B81133-D1334-M
B81121-C-B142
B81122-C1332-M
B32529-C472-K
B41822-A3228-M
B32529-C102-K
B32529-C102-K
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
B32529-C222-K
B32529-C222-K
EPCOS
EPCOS
B41822-A4108-M
B41822-A4108-M
B41822-A4477-M
B81123-C1332-M
B37979-G5221-J51
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
C 34
C 35
C 36
C 37
C 38
C 39
C 41
C 40
C 42
C
insert wire bridge
insert wire bridge
1000µF/16V
1000µF/16V
470µF/16V
3,3nF
250V AC, Y1
* 220pF/50V
CG
not assembled
insert wire bridge
1,5nF/630V assembled between Heatsink of
Q2 and BUS Voltage
* = located on control board
9 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Component
Value
R1
* 3825K
2x 1,91M
metal
R2
220K
R 2A
220K
R3
* 22K
R 4A
* 390K
metal
R 4B
* 390K
metal
R5
* 2,2K
R6
0,22
1 + 2x 0,56 parallel
R7
* 2,2K
R8
* 7,5K
R9
3,3
R 10
18K
R 11
* 51K
metal
R 12
* 3825K
2x 1,91M
metal
R 13
* 3825K
2x 1,91M
metal
R 14
* 51K
metal
R 15
0,50
2x 1 parallel
R 16
* 390K
R 17
18K
R 18
3,3
R 19
5,1K
metal
R 20
5,1K
metal
R 21
10K
R 22
680
R 23
* 33K
R 24
* 51 K
metal
R 25
* 10K
R 26
* 68K
R 27
* 51K
metal
R 28
4,7K
R 29
1
R 30
SIOV-S14K250G5
R 31
insert wire bridge
R 32
* 1,1K
R 33
470
R 34
* 56K
R 35
* 1,1K
R 35A
* 680
R 36A
56
4W
R 37
3,9K
metal
R 38
5,1K
metal
R 39
1K1
R 40
220K
2W
R 41
33
R 42
33
R 43
not assembled
R 43 A
330K 2W between VBUS and VCC
R 44
56
R 45
56
R 46
470
R 47
100
R 48
470
R 49
not assembled
• = located on control board
Order-Nr.
Manufacturer
Q69x4603
EPCOS
Warning: Heatsink of D5 is connected to 380V BUS Voltage !
10 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Printed Circuit Board of control circuit
马8mm
8
I~-;
己一巳 5
..
r-
ø
/向 E
P F" C CS
GN 口
s
P F" C CL
GND
VCC
PIIH OUT
P F" C OUT
GND
PIIH CS
SYNC
SS/ST 自 NDßY/O l<
PIIH IN/Ol<
V RE:F"
DC ßUS VS
自 UX
VS
T 118M咽T ~a:Jqla:J 1
Board 忏 8
Name:
' 55mm
x 66mm
CB工 PCB1t
11 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
zom=o
〉 ωDm 〉口∞伺OHZHBEgum-mO 宅星 ZEEZ-EEm 主
Printed Circuit Board of power circuit
』
EE曲皿
N
ll
EE-叫
-J
12 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Single ended feed forward Transformer
150W / 100kHz; Output voltage: 5V/18A; 12V/4A; -12V/1A
Core E36/18/11; N27; without gap; ALMIN = 2330nH; coil former vertical
34 turns 0,22 mm Ø
34 turns 0,40 mm Ø
MAG
Pin 5
Pin 1
PRIM
Pin 7
Pin 2
Pin 13
Pin 16
Pin 14
7 turns
0,4mm Ø
SEC
7 turns
2 x 0,8mm Ø
SEC
3 turns
4 x 0,8mm Ø
SEC
Pin 15
Pin 9+10
Pin 11+12
34 turns 0,40 mm Ø
PRIM
34 turns 0,22 mm Ø
MAG
Pin 2
Pin 5
Pin 1
Pin 4
center
means one layer Makrofol
Primary winding
68 turns 0,40 mm ∅
transformer wire
Demagnetization 68 turns 0,22 mm ∅
transformer wire
Secondary winding1
3 turns 4 x 0,8 mm ∅
transformer wire
Secondary winding2
7 turns 2 x 0,8 mm ∅
transformer wire
7 turns
0,4 mm ∅
transformer wire
Secondary winding3
Top
5
11, 12
4
1
2
2
M
A
G
P
RI
1
5
M
A
G
P
RI
7
S
E
C
S
E
C
S
E
C
15
16
13
14
9, 10
13 of 20
Pin 1 •
Pin 2 •
•
Pin 4 •
Pin 5 •
•
Pin 7 •
Pin 8 •
•
•
•
•
•
•
•
•
Pin 16
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Pin 10
Pin 9
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Smoothing Choke of single ended forward converter
Core E36/18/11; N27; total gap = 2mm; AL = 100nH; coil former horizontal;
L = 8µH; @5V output
Pin 6
21 turns 0,3mm Ø
w3
Pin 13
Pin 7
21 turns 0,7mm Ø
w2
Pin 10
Pin 3
9 turns 2x 0,95mm Ø
w1
Pin 14
Pin 2
9 turns 2x 0,95mm Ø
w1
Pin 15
center
Winding 1: 9 turns 2 x 2 x 0,95 mm ∅ transformer wire
Winding 2: 21 turns
0,7 mm ∅ transformer wire
0,3 mm ∅ transformer wire
Winding 2: 21 turns
Top
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
8•
7•
6•
5•
4•
3•
2•
1•
• Pin 9
• Pin 10
• Pin 11
• Pin 12
• Pin 13
• Pin 14
• Pin 15
• Pin 16
14 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Boost converter choke for PFC
Core E36/18/11; N27; total gap = 2mm; AL = 100 nH;
L = 1 mH; IPEAK = 3,5 A; coil former vertical
Pin 11
W1: 25 turns 30x 0,1 mm Ø
Pin 14
Pin 1
Pin 2
Pin 7
Pin 5
Pin 14
W1: 25 turns 30x 0,1 mm Ø
W3: 5 turns
0,30 mm Ø
W2: 8 turns
0,30 mm Ø
W1: 25 turns 30x 0,1 mm Ø
Pin 13
W1: 25 turns 30x 0,1 mm Ø
center
1 layer
W1 : 100 turns 30 x 0,1stranded wire w/ silk
W2 : 8 turns
0,30 transformer wire
W3 : 5 turns
0,30 transformer wire
15 of 20
Top
Pin 1 •
Pin 2 •
•
Pin 4 •
Pin 5 •
•
Pin 7 •
Pin 8 •
•
•
•
•
•
•
•
•
Pin 16
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Pin 10
Pin 9
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
RFI Choke
L= 470µH, IPEAK= 3,5A
Core E 25/13/7 (EF25), N27, total gap= 2mm, AL=54 nH,
coil former vertical
22,5 turns
0,55 mm Ø
22 turns
0,55 mm Ø
22 turns
0,55 mm Ø
22 turns
0,55 mm Ø
Pin 4
Pin 9
means one layer of Makrofol
88,5 turns transformer wire 0,55 mm Ø
Top
Pin 1 •
•
•
•
Pin 5 •
• Pin 10
•
•
•
• Pin 6
16 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
17 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
References:
[1] nnn
Revision History
Application Note AN-TDA16888-0-010323
Actual Release: V1.1 Date:2001-03-23
Previous Release: V0.1
Page of
actual
Release
Page of
prev.
Release
Subjects changed since last release
18 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see the address list on the last page or our webpage at
http://www.infineon.com
CoolMOS and CoolSET are trademarks of Infineon Technologies AG.
Edition 2000-03--03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 2000.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts
stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in
Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your
nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon
Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the
safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be
endangered.
19 of 20
AN-TDA16888-0-010323
V1.1
TDA 16888: Multioutput Single Transistor
Forward Converter 150W / 100kHz
Infineon Technologies AG sales offices worldwide –
partly represented by Siemens AG
A
F
J
RC
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AN-TDA16888-0-010323
V1.1
Power Semiconductors
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Product Information 01.98
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TDA 16888
High Performance Power Combi Controller
Edition 01.98
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München.
© Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of
third parties are concerned, liability is
only assumed for components, not for
applications, processes and circuits
implemented within components or
assemblies.
The information describes the type of
component and shall not be considered
as assured characteristics.
Terms of delivery and rights to change
design reserved.
For questions on technology, delivery
and prices please contact the
Semiconductor Group Offices in
Germany or the Siemens Companies
and Representatives worldwide (see
address list).
Due to technical requirements
components may contain dangerous
substances. For information on the
types in question please contact your
nearest Siemens Office, Semiconductor
Group.
Siemens AG is an approved CECC
manufacturer.
Packing
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known to you. We can also help you –
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You must bear the costs of transport.
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Components used in life-support
devices or systems must be expressly
authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may
only be used in life-support devices
or systems2 with the express written
approval of the Semiconductor Group
of Siemens AG.
1 A critical component is a component
used in a life-support device or system
whose failure can reasonably be
expected to cause the failure of that
life-support device or system, or to
affect its safety or effectiveness of that
device or system.
2 Life-support devices or systems are
intended (a) to be implanted in the
human body, or (b) support and/or
maintain and sustain human life.
If they fail, it is reasonably to assume
that the health of the user may be
endangered.
TDA 16888 – High Performance Power Combi Controller
Introduction
Functionality and Benefits
PFC Preconverter
PWM Converter
PFC and PWM Gate Drive
Oscillator and Synchronisation
3
Siemens Aktiengesellschaft
Introduction
TDA 16888 is designed for new
generations of off-line Switched
Mode Power Supplies (SMPS)
with optional universal input and
Power Factor Correction (PFC) e.g.
for PCs, Monitors, CTVs
and industrial applications.
AUX/
Standby
380 V DC
AC/DC
Input
90 V - 270V
Output 1
TDA 16888
Output N
Figure 1 Basic Application Circuitry
Functionality and Benefits
This high performance SMPS
Power Combi Controller is optimized to reduce system costs,
supports solutions for global requirements, generates less EMI and
is designed by FMEA rules.
The TDA 16888 allows load
variations down to zero watts and
controls low power standby operation by switching off its Pulse
Width Modulation (PWM) stage.
Siemens Aktiengesellschaft
4
TDA 16888 – High Performance Power Combi Controller
The Power Combi Control-lC
TDA 16888 includes the PWM
control for an SMPS and the
control for the preconverter to
improve the power factor and to
reduce the harmonics of the AC
input current. Both sections are
internally synchronized on the
same operating frequency.
2 ms
100%
Rectified AC Input Voltage
(100 V/Div)
90%
10%
0%
AC Input Current
(0.5 A/Div)
10 mV
100 V
Figure 2 Input Signals
The preferred topology of the
PFC preconverter is boost, but flyback is possible, too. The PWM
section can be designed as a forward or as a flyback converter.
Maximum duty cycle of the PFC
is about 94%, in order to achieve
minimal line current gaps. Maximum duty cycle of the PWM is
limited to 50% to prevent
transformer saturation.
There are monitoring and protection functions such as broken wire
detection, undervoltage and dual
step overvoltage monitoring of the
bus voltage, peak current limitation
for PFC and PWM section and
undervoltage lockout of the IC
supply voltage. The Combi-lC
TDA 16888 is designed with
respect to a Failure Mode Effect
Analysis (FMEA).
5
The limitation of the PWM duty
cycle, i.e. the leading edge PFCand the trailing edge PWM
operation, are done in a digital way
by flip-flops. Handling the signals
this way meets the requirements
for an external synchronisation.
On the other hand an oscillator is
necessary that operates at twice
of the operating frequency. For a
lower current consumption and
higher EMI resistance the capacitor of the oscillator is integrated.
The operating frequency is set by
only one resistor. The operating
frequency can be increased by a
sink current in parallel to this
resistor. There is an additional
synchronisation input that can be
used for frequency adjustment or
in connection with a phase locked
operation.
Siemens Aktiengesellschaft
TDA 16888 – High Performance Power Combi Controller
PFC Preconverter
In normal operation the PFC section of TDA 16888 operates with
dual loop control. A first control
loop controls the shape of the line
current by average current control
enabling either continuous or discontinuous operation mode.
The second loop controls the
DC bus voltage. There is a third
control loop available that enables
the PFC section as an auxiliary
power supply even when the
PWM section is disabled. During
standby operation mode (disabled
PWM) the PFC section is operating with half of its nominal operating frequency in order to save
operating power.
Rectification of an AC voltage and
smoothing with an electrolytic
capacitor effects a peak current
during the peak input voltage and
a break in current flow during the
rest of the half period of the line
frequency. The RMS value of such
a pulsed input current is about
twice of a sinusoidal current and
the harmonics of that pulsed
current effect EMI to other devices. The power factor is the relation between real input power to
apparent input power. With a
typical main voltage rectification in
electronic devices the power factor is about 0.5. Standards to
improve the power factor will
become effective in the near future.
But system cost must not increase
by introduction of power factor
correction. It depends on the
output power and features like the
option to supply a device from
different line voltages.
R 36A
L1
Fuse
IIN
90 V –
V
270 V AC IN
C25
L4
C1
C24
RFI
R 30
C26
2 µs
100 V
100%
90%
10%
PWM Drain-Source Voltage
(100 V/Div; On-Time 3.5 µs,L)
PFC Drain-Source Voltage
(100 V/Div; On-Time 7.5 µs,L)
0%
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PFC IAC
VREF
PFC CC
PFC CS
GND S
PFC CL
GND
PFC OUT
VCC
PWM OUT
PWM CS
SYNC
PWM SS
PWM IN
PWM RMP
ROSC
PFC FB
PFC VC
PFC VS
AUX VS
Input AC
Reference Voltage
Current Compensation
Current Sense
Ground Sense
Current Limitation
Ground
Driver Output
Supply Voltage
Driver Output
Current Sense
Synchronisation
Softstart
Input
RAMP Voltage
Oscillator
Feedback
Voltage Compensation
Voltage Sense
Auxiliary Voltage Sense
D10
100 V
R 29
Q3
+
Figure 3 Output Signals
AUX1
R 28
C18
D11
D12...D15
Means two resistors in series
R 27
150 W Feed-Forward Multioutput SMPS for PC
Figure 4 Application Circuitry
Siemens Aktiengesellschaft
6
The most efficient way to correct
the power factor with an active
circuitry is to use a boost converter.
Most of the energy flowing from
the input via rectifiers to the bus
capacitor bypasses the
switching transistor of the boost
converter. Connecting the boost
preconverter to the line, an inrush
current occurs due to charging the
bus capacitor. As the capacitance
of the bus capacitor is between
There is a peak current limitation
(Pin 6) to prevent an overload of
the boost transistor during inrush
currents and during maximum
load, which occurs for example
after turn on to charge the bus
capacitor. The turn off threshold
D16...D19
IC5
+
C19
-12 V
1A
+
C20
D24
D1...D4
D5
L2
V BUS = 380 V DC
AUX1
+
L3
D21
+
R 46
R 44
C33 R 45
R 40
D6
D23
C38
R 48
D20
Tr.1
C31
6
is designed at +1 V to meet FMEA
requirements. A broken wire to
Pin 6 activates the current
limitation. Another comparator (C2)
at Pin 19 is detecting a broken wire
to the bus voltage sense. At least
20% of nominal bus voltage is
necessary to make the Combi-lC
active. This feature has to be taken
into account when testing the IC at
low input voltages.
5V
100 mA
R 31
5
three to ten times lower than with
conventional rectification, the
inrush current is much smaller
even without additional measures
like NTCs.
C35 L3
C32
C36
L6
+
12 V
4.2 A
C37
D8
C3A
C4
D7
Q1
R 10
SIPMOS
600 V
+
C3
C2
R 4A
C29 R 41
Q2
R 12
R3
R 4B
R5
R7
C10
SIPMOS
1000 V
IC3
R 39
R 13
R 11
R9
R8
C8
1
C28
L5
R 14
R 32
C5
C21
C6
C41
C7
R 16
R 22
R 20
C16
4
5
3
+
Current
limitation
8
7
PFC
Current EA
17
19
Overvoltage
Off=
Standby
C17
IC1
6
5V
20 A
R 15
C9
R2
C15
C34 L3
C30
+
R 43
R6
R1
D9
+
R 47
R 42
R 21
18
5V
IC2
R 19
R 17
Voltage EA
STANDBY EA
Startup
UVLO
9
12
R 26
+
VREF
R18
PWM
IC4
R 33
5 V 20
2
Soft
Start
OSC
16
15
13
14
10
C11A
C11
R 37
R 25
R 35
+
C27
11
C23
C39
C42
IC6
C12
R 24
C13
C14
C22
R 23
Q4
R 38
R 34
7
Siemens Aktiengesellschaft
The power supply of the Combi-lC
can be realized by a separate winding on the boost converter choke.
Our proposal is to use a bridge
rectifier on the auxiliary winding
AUX 1. In this way a current can
flow at low input voltages in
flyback mode and at high input
voltages in forward mode. The
minimum supply voltage at
capacitor C18 will occur at an input
voltage level half of the bus voltage.
There is another operating
condition when the supply voltage
at C18 becomes low, i.e. at
disabled PWM section and high
input voltages. This condition may
be the worst for the auxiliary
power supply. In this application
we got the power to supply the
Combi-lC during all operating
conditions and in addition the
circuit offers an isolated auxiliary
voltage of 5 V / 100 mA.
An increase of output power of the
auxiliary power supply will be an
option of future applications.
In order to continue the description
of the auxiliary power supply there
is a separate control loop and
a separate output of the boost
converter via diode D6. This
additional circuitry is necessary to
get a fast response at load
changes. There are operating
conditions resulting in an
overshoot at the bus voltage that
would stop the boost transistor for
more than 100 ms. With the
second output of the boost converter via D6 a not working transistor can be detected within 100 µs
and the transistor can be turned on
in a way, that the auxiliary output
gets power but not the main
output to the bus capacitor. During
the standby operation the bus
voltage remains at nominal level.
The separate control loop can be
activated by itself, when the
second output of the boost converter via D6 is designed for an
output voltage slightly below the
nominal bus voltage (e.g. 5%). The
load (R2) which is necessary at the
second output can be used for the
startup of the Combi-lC.
The PFC section is working initially
at half of the nominal operating
frequency until a level of 20%
below the nominal bus voltage is
reached. Then the PWM section
is able to run with a soft start
(Pin 13) with nominal operating
frequency on both sections or if it
is disabled by transistor Q4, then
the system is running in the
standby mode with half of its
nominal operating frequency.
Usually there is an overshoot
during the charging of the bus
capacitor. The reason is the long
response time of the bus voltage
control loop. There is a first overvoltage threshold at 10% above
nominal bus voltage. The operation
of the boost transistor is turned
down via OTA2 and the Multiplier
to avoid increasing bus voltage.
A second threshold at 20% above
nominal bus voltage will stop PFC
and PWM section immediately
until the bus voltage reaches
a level of 10% above nominal bus
voltage. This feature protects the
power supply during hazardous
mains overvoltages in combination
with varistor R30.
500
Input Current (Pin 1)
800 µ A
400 µ A
200 µ A
100 µ A
50 µ A
25 µ A
µA
400
Output Current (Pin 4)
The typical startup of the Combi-lC
is supported by the undervoltage
lockout (UVLO) feature of the IC.
Via a highly resistive resistor (R2)
a capacitor (C11) is charged up to
a threshold of 14 V at Pin 9. During
this operation the current
consumption of the IC is less than
100 µA. Reaching this threshold
the IC becomes active sending
drive pulses to the boost transistor
Q1. During this operation the
PWM section is not active yet in
order to save supply current. The
same reason is for driving the
boost transistor with only half of
the nominal operating frequency.
Capacitor C11 has to be designed
large enough that the circuitry is
able to supply the IC before the
voltage at Pin 9 reaches the turn
off threshold of 11 V.
300
90 V AC
180 V AC
270 V AC for
Nominal
Output Power
200
90 V AC
180 V AC
270 V AC for
10% Nominal
Output Power
100
0
0
1
2
Figure 5 Dynamic Characteristics
of the Multiplier
Siemens Aktiengesellschaft
8
3
4
5
Input Voltage (Pin 18)
6
V
7
TDA 16888 – High Performance Power Combi Controller
PFC
FB
17
OP1
PFC
VC
18
PFC
CS
4
AUX
VS
20
OTA3
1.2 V
–
+
5V
GND
S
5
D1
+
–
D3
OP2
5V
D2
RQ
SQ
Z1
C2
5.5 V
+
–
1V
C4
C6
–
+
Z3
17.5 V
–
+
6V
5.5 V
4V
VCC
OSC
7.4 V
Power Management
6V
SQ
RQ
–
+
0.45 V
0.4 V
T1
R2
10 kΩ
FF2
C7
I1=30 µA
Z2
C8
–
+
–
+
V1=1.5 V
R1
C5
10 kΩ
PWM
Bias
Control
2
VREF
D4
FF1
OTA2
Undervoltage Lockout
11 V - 14 V
VCC
1V
–
+
VCC
Voltage Reference 7.5 V
(output disable)
PFC
OUT
8
VCC
9
C1
+
–
–
+
1
PFC IAC
PFC
CL
6
C3
–
+
M2
QM
M3
PFC
VS
19
+
–
OTA1
M1
PFC
CC
3
12 16
SYNC ROSC
13
PWM SS
14
PWM IN
C10
R3
100 kΩ
0.4 V
OP3
C9
1V
+
–
x5
+
–
15
PWM RMP
11
PWM CS
7
GND
10
PWM OUT
Figure 6 Block Diagram of TDA 16888
At typical operating mode of the
PFC section a DC output signal
with a small superimposed AC
ripple can be found at the output
of the voltage error amplifier OP1
at Pin 18. This signal is multiplied
by the current at Pin 1, derived
from the rectified AC input voltage.
Consequently a multiplier output
current shaped like the input
voltage is achived, that can be
varied in amplitude by the voltage
error amplifier OP1.
A second error amplifier OP2
controls the input current like the
set value of the multiplier output.
In order to enlarge the effect of
the voltage error amplifier OP1
there is an exponential function at
the voltage input (Pin 18) of the
multiplier included (cf. Figure 5).
9
Furthermore there is an OTA3 that
cares for the stability of the bus
voltage during light load and no
load conditions.This is achieved by
compensating the multiplier output
current as long as the output
voltage of OP1 is well below 1.2 V.
The ramp voltage of the PFC
pulse width modulation starts
from a higher voltage level of 6 V
decreasing to the minimum of 1 V.
The reason for this shape which
is invers to commonly used ramp
voltages is that the feedback of
OP2 can be connected to the
current sense input (Pin 4). In this
way the sensed signal is smoothed
and the levels at Pin 4 can be kept
well above 0 V.
Siemens Aktiengesellschaft
PWM Converter
The PWM section operates with
improved current mode control,
with effective slope compensation,
spike suppression and especially
with amplified signal levels at the
pulse width comparator. The PWM
section can be disabled by a short
(controlled by transistor Q4) across
the soft start capacitor.
VREF = 7.5 V
2
Simplified Equivalent Circuit
of the Oscillator Frequency Setting Circuitry
ROSC
16
R OSC
GND
COSC
7
V COSC
5V
1V
t
0
Internal Clock
H
t
L
MAX Duty Cycle PWM
H
t
L
MAX Duty Cycle PFC
H
t
L
Internal PFC RAMP Voltage
6V
Output
Current EA
1V
t
0
PFC OUT
H
L
t
PWM RAMP Voltage (Pin 15)
6.5 V max
V PIN 14
0.4 V
t
0
PWM Current Sense Voltage (Pin 11)
1.0 V
t
0
Figure 7 Typical Shape of Signals
Siemens Aktiengesellschaft
10
TDA 16888 – High Performance Power Combi Controller
The PWM converter starts with
a soft start at a bus voltage higher
than 80% of its nominal value.
Operating frequency is the nominal and the same like that of the
PFC preconverter. The transistor of
the boost converter turns on with
leading edge and that of the PWM
turns on with trailing edge, delayed in minimum 50% of the operation period.
The way of control is an improved
current mode. There is a capacitor
at Pin 15, by means of which
a basic ramp voltage is generated
for slope compensation. This
voltage is superimposed by the
times 5 amplified voltage drop
across the shunt resistor (R15) fed
over an internal 10 kΩ resistor in
order to suppress spikes. The result
is a ramp voltage with a maximum
level up to 6.5 V. Correspondingly
the active input range of the PWM
input (Pin 14) is from 0.4 V to 7 V.
The higher level on the PWM comparator cares for better resistance
against EMI and better stability of
operation (cf. Figure 3). In addition
the current sense input (Pin 11)
feeds a fast comparator
(threshold = 1 V) for current
limitation.
PFC and PWM Gate Drive
Oscillator and Synchronisation
There is a new design for the gate
drive of both sections. The
employed totem pole configuration
avoids cross conduction currents
and has a voltage modulated turn
on slope. The turn on slope
increases moderately between 0 V
and 3 V, increases slowly between
3 V and 5 V and increases moderately above 5 V up to the maximum of 12 V. The reason for this
improved rising edge is a possible
fast turn off as soon as the current
limitation is activated, a continuously reduciable duty cycle
down to zero and a soft current
commutation from the boost or
output diode to the transistor. The
voltage modulation meets these
demands independent of the load
capacitance. The turn off is fast
with a current capability of about
1.5 A peak.
The oscillator operates with an
integrated low tolerance capacitor
and a special voltage and temperature compensated current mirror
set by only one external resistor at
Pin 16. The integration of this
capacitor operating with a ramp
voltage of 5 V increases the resistance against EMI and saves supply
current due to its small value. The
internal oscillator operates with
twice of the external operating
frequency for exact limitation of
the PWM duty cycle below 50%
by flip-flops. In the same way the
leading edge turn on of the PFC
and the trailing edge turn on of the
PWM is generated.
Therefore the operating frequency
can be changed during operation
only by bypassing a current to the
set resistor R24.
When operating the Combi-lC
below the undervoltage threshold,
the drive outputs are active low.
5V
Changing the frequency by the set
current at Pin 16 does not influence
the amplitude of the internal ramp
voltage of the PFC pulse width
modulation but will influence the
external ramp voltage of the PWM
at the external capacitor C13.
200 ms
Gate Drive Voltage
(5 V/Div)
100%
90%
Drive Current to BUZ 91
(0.5 A/Div)
10%
0%
10 mV
Figure 8 Gate Drive Signals
11
Siemens Aktiengesellschaft
TDA 16888 – High Performance Power Combi Controller
D75
R 31
D16...D19
R 36A
Fuse
IIN
90 V –
270 V AC V IN
L1
IC5
+
L4
C25
+
C19
D5
L2
C82
V BUS = 380 V DC
Tr.1
C79
C3A
D6
R 49
R 4A
C2
C76
C4
R 10
+
R 43
C3
R6
C9
R 29
R1 =
=
R2
R3
R 4B
R5
R7
C8
C10
R8
R 12
R 11
R9
C7
=
=
+
R 76
R 13
R 14
SIPMOS
1000 V
R 16
C41
C6
C77
+
R 74
C74
L
D71
R 15
C73
AUX1
C80
D72
D22
Q1
+
R 78
C40
AUX1
SIPMOS
600 V
C83
D73
R 30
C26
+
R 80
D74
C20
D1...D4
C1
C24
RFI
C85
+
R 72
C71
IC3
C5
D12...D15
Q2
IC1
6
C18
D10
Q3
4
3
5
Current
limitation
+
D11
1
8
7
19
OverVoltage
PFC
R 28
17
18
R 32
Voltage EA
Current EA
STANDBY EA
Startup
UVLO
3
Synchronisation 4
Circuit
1
5
SYNC
Input
9
VREF
12
R 26
5 V 20
16
15
14
10
R 18
11
R 35
R 27
+
C11A
There is a synchronisation input
Pin 12. A high level signal
(3.5 V - 7.5 V) discharges the internal oscillator capacitor. Correspondingly a low level signal
(below 0.4 V) enables the charging
with the set current (R24).
The internal oscillator can be
completely superimposed by an
external synchronisation signal.
However the influence on the
internal ramp voltages has to be
taken into account.
IC4
C39
Q4
C23
C12
C11
R 24
C13
C14
R 23
C22
R 34
Means two resistors in series
Siemens Aktiengesellschaft
13
PWM
R 25
R 60
=
R 17
Soft
Start
OSC
2
R 22
C21
5V
For a synchronisation over a wide
frequency range the variation of
the set current at Pin 16 is to be
preferred. For a synchronisation,
which will alter the set frequency
up to 20% the synchronisation
input may be the better choice.
Example for
External Synchronisation:
Synchronisation of the Combi-lC
TDA 16888 to a Reference
Frequency by a Phase-Locked
Loop (PLL)
The switching frequency of the
Power Factor- and PWM controller
TDA 16888 may be synchronized
to a reference frequency e.g. of a
CRT monitor by using the standard
PLL-CMOS-IC 4046.
12
5V
0.1 A
L75
+
3
C84
R 79
-12 V
0.2 A
1
VREF = 7.5 V
2
3
R 59
C46
L74
+
0
C81
R 77
5V
2A
C47
D26
14
4
16
13
+
7
C78
R 75
9
4
C75
R 73
3
85 V
0.28 A
+
1
C72
R 39
R 71
5
10
7
R 24
R 54
PWM
Driver
Output
R 57
8
R 51
TDA
16888
C45
Q5
10
C43
R 50
L71
R 58
16
R 52
C44
15 V
1A
L72
+
R 53
R 55
D25
4046
L73
C48
R 56
Q6
195 V
0.3 A
5
2
Figure 10 Synchronisation Circuitry
of TDA 16888 with PLL
R 20A
R 20
C16
C17
Off=
Standby
R 21
IC2
R 19
R 33
C27
R 37
C42
IC6
R 38
Figure 9 Application Circuitry
This device is supplied by the
7.5 V reference output VREF (Pin 2)
of the TDA 16888. Generally the
4046 controls the output current of
Pin 16, which allows to set-up the
switching frequency by the
internal oscillator.
The PWM output signal at Pin 10
is fed back via a voltage divider
(R50, R51) to Pin 3 of the 4046.
Pin 14 of the 4046 is the input of
the given reference frequency signal, fed from a separate winding
on the deflection transformer, and
compared internally by using phase
comparator II.
The level of the phase comparator II
output signal (Pin 13) represents
the phase difference between the
PWM output and the reference
signal. Pin 13 feeds a low pass
filter to provide VCO IN (Pin 9) of
the 4046 with the average of the
phase difference value. The VCO
is not used, but the signal is amplified by the internal source follower.
The DEM OUT (Pin 10) controls the
base current of Q6 and in this way
the oscillator of the TDA 16888.
R24 and R52 set the minimum and
maximum limits of the frequency
(adjusted to approximately 30 kHz
and 120 kHz respectively).
13
The phase comparator II output
signal at Pin 13 is filtered by R55
and C44 and fed into the VCO input
at Pin 9. In addition a dynamic
feedback from collector of Q6 is fed
into Pin 9 via Q5 and its network.
The capacitors C43 and C47 bypass
high frequent currents. The response time of the phase locked
loop is less than 10 ms. If there
are some PWM output pulses missing, the oscillator frequency runs
towards its maximum. If trigger
pulses of the reference frequency
are missing, the oscillator frequency
decreases to the minimum
set value.
The design works independent of
the duty cycle of the PWM output
signal, as long as its level is high
enough to be realized as 'high' by
the CMOS-IC.
The PLL frequency lock range and
capture range are determined by
R24 and R52.
Siemens Aktiengesellschaft
Version 1.0 , September 2004
Application Note
AN-CoolMOS-09
200W SMPS Demonstration Board II
Author:
Marko Scherf, Wolfgang Frank
Published by Infineon Technologies AG
http://www.infineon.com
Power Conversion
N e v e r
s t o p
t h i n k i n g
200W SMPS Demonstration Board II
This application note describes the 200W SMPS Demonstration Board with Infineon power
products like CoolMOS, OptiMOS, TDA16888, SiC Schottky diode thinQ!, small signal N- & Pchannel MOSFETs.
Table of Contents
1
2
3
4
Features / Parameters ...........................................................................................................3
General Description / Main Function......................................................................................4
Construction / Heatsinks ........................................................................................................4
Description of Functional Part Groups ...................................................................................5
4.1 Power Stages (“Main Board”) ..........................................................................................5
4.1.1 AC input/ EMI Filter ....................................................................................................5
4.1.2 PFC Converter ...........................................................................................................5
4.1.3 PWM Converter (Two Transistor Forward)................................................................6
4.1.4 Synchronous Rectification .........................................................................................6
4.2 Controlling Circuitry (“Control Board”) .............................................................................6
4.2.1 General Description of the Combi-IC TDA16888 ......................................................6
4.2.2 PFC Control ...............................................................................................................7
4.2.3 PWM Control..............................................................................................................7
4.2.4 Gate Drive Circuitry....................................................................................................7
5 Power Losses / Efficiency ......................................................................................................8
6 Power Loss Sources ..............................................................................................................9
7 Conducted EMI Measurements ...........................................................................................10
8 Construction of magnetic components.................................................................................11
8.1 PFC choke......................................................................................................................11
8.2 Main transformer ............................................................................................................12
8.3 Output filter choke ..........................................................................................................13
9 PCB Layout ..........................................................................................................................14
9.1 Main Board - Scaling 1:1................................................................................................14
9.2 Control Board- Scaling 1:1.............................................................................................17
10 Bill of Materials..................................................................................................................17
10.1 Main Board .....................................................................................................................17
10.2 Control Board .................................................................................................................20
Danger!
This demonstration board works with mortally high voltage. Do not touch it or any
other connected equipment while powered. Be aware that the board could carry
high voltage for at least 5 minutes after disconnecting from mains.
The unit can heat up to a high temperature. Risk of burning is given when
touching.
Assure yourself when working with this unit that no danger or risk can occur to
the user or any other person!
Do not run the main board without properly inserted control board!
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200W SMPS Demonstration Board II
1
Features / Parameters
Features:
- Infineon & EPCOS components on board
- Third generation of CoolMOS C3 as PFC, PWM switches
- Silicon Carbide (SiC) Schottky diode thinQ! as PFC diode
- OptiMOS2 as synchronous rectification switches
- PFC and PWM controller in one IC
- High efficiency
- No external heat sink required
- No minimum output load required
- Output over load protected
- Output short circuit protected
Parameters:
- wide input voltage range 90-265V
- output power 200W
- output voltages
- 5V / 20A max (load resistance = 0.25Ohm)
- 12V / 8.3A max (load resistance = 1.45Ohm)
- active Power Factor Correction boost converter operates at 200kHz
- hard switching two transistor forward converter operates at 200kHz
- synchronous rectification for 5V output operates at 200kHz
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2
General Description / Main Function
Boost inductor
~
SIC
SDD04S60
+
CoolMOS
SPB07N60C3
EMCON
IDD03E60
+12V
8A
Tr. 1
EMI
AC in
90-275V
Line
rectification
Filter
2 parallel
CoolMOS
SPB07N60C3
+5V
20A
EMCON
IDD03E60
~
fPFC =fPWM = 200 kHz
-
CoolMOS
SPB07N60C3
PFC/PWM
Control
TDA 16888
High and
Low Side
Driver
OPTIMOS 2
BSC022N03S
2 parallel
OPTIMOS 2
BSC022N03S
Block Diagram
The SMPS Demoboard consists of two power stages, a AC-DC- converter for power factor correction (PFC
section) and a PWM-controlled DC-DC-converter configured as a two-transistor forward topology (PWM section).
The PFC stage is a step up (boost) converter which serves to provide a 380V DC-bus at its output while
consuming sinusoidal line current (near a unity power factor) at the input. Another PFC related feature is the
ability to supply the converter with a wide range input voltage (90-265VAC) without range switches to re-configure
the rectifier assembly. The power semiconductors used are two CoolMOS SPB07N60C3 in parallel and a silicon
carbide diode prototype SDD04S60 (4A/600V).
The two-transistor forward-converter provides isolation from the AC line. There are two output voltages, 5VDC
and 12VDC. At the primary side the power semiconductors are two CoolMOS SPB07N60C3 and two EMCON
diodes IDD03E60 (3A/600V). At the secondary side the rectification principle is different for each output. At the
12V-path there is a conventional rectification with Schottky diodes. The 5V output is realized as synchronous
rectification using low voltage MOSFETS BSC022N03S.
One single integrated circuit, a TDA16888, provides control for both power stages, the PFC and PWM sections.
3
Construction / Heatsinks
A larger PCB (called “main board”) is the mechanical base of the SMPS. It carries the power semiconductors (in
SMD lead frame technology) and the passive devices of the power stages. No additional heatsink is used. The
copper layers of the board serve to distribute the dissipated energy with the help of a metal plate at the bottom of
the board. A smaller PCB (called “control board”) carries the controlling circuitry and is plugged to the “main
board” at its top.
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4
Description of Functional Part Groups
4.1
Power Stages (“Main Board”)
D10
BAV99
VCC
C101
100n
Q3
BSP129
D12
TMBYV10-60
C87
0µ47
R28
4k7
D11
13V
C18
47µ
R29
1R
C88
0µ47
D13
TMBYV10-60
D79
BAV99
Q5
BSP129
VCCtop
C100
100n
C89
0µ47
R81
4k7
D78
13V
SDD04S60
D5
D76
TMBYV10-60
C91
47µ
GNDtop
R80
1R
L2
500µH
C90
0µ47
rec AC+
L4
L1
Fuse
~
AC in R102
901M2
255V
D6
VBus2
R2
220k
C4
2n2
Q2B
D82
D77
TMBYV10-60
VBus =380V
VCC
G2B
SPB
07N60
C3
C24
µ47
+12V
8A
C33
R45
4R7
R44
4R7
C36
2200µ
D21
C32
2n2
L3A
R48
1k8
L6
R99
1k8
LED1
1N5408
C3B
C2
µ47
C3A
100n
R98
1R
R97
10R
C3
150µ
BSC022N03S BSC022N03S
R100
Q19
1R
Q19A
R103 47R
R30
~
C36
2200µ
+
D1...D4
KBU8K
C26
4n7
Tr. 1
2n2
C25
4n7
C86
µ47
D20
D22
GNDtop
Q2A
G2A
Q1B
Q1A
D27
rec ACG1B
R6
0R15
SPB
07N60
C3
G1A
SPB
07N60
C3
SPB
07N60
C3
S2A
R15
0R47
C97
4n7
Q18
BSP318
C98
4n7
R101
1R
L3B
C15
4700µ
C28
4700µ
L5
R104
1k8
+5V
20A
LED2
(LC)
Q21
BSC022N03S
C39
4n7
XS
IC3
CNY17-3
C99
2n2
R39
1k
R22
680R
C16
68n
C17
2n2
R20
5k1
R21
10k
IC2
TL431CD
R19
5k1
4.1.1
AC input/ EMI Filter
The input voltage of the SMPS is 90 to 265Vac (50/60Hz). A Fuse prevents greater damage in the case of
catastrophic failure. The function of the line EMI Filter (C86, L1, L4, C24...26, C2) is to suppress the high
frequency noise caused by the switching transitions of both power stages. Varistor R30 serves to suppress high
voltage line transients to protect the input. The line rectifier (D1...4) consists of standard silicon diodes.
4.1.2
PFC Converter
The PFC converter is a step up topology with continuous inductor current at full load. The switching frequency is
200kHz. The output voltage is approximately 380Vdc.
Main parts of the PFC are the boost inductor L2, switches Q1A/Q1B, boost diode D5 and the bulk capacitor C3.
L2 is an iron powder toroidal core with a single layer of copper wire to keep stray capacitance small.
Q1A/Q1B are CoolMOS SPB07N60C3 because of their high switching speed and their very low on-resistance
(important at low input voltagesÎhigher current, duty cycle). The only reason for paralleling is to get larger
cooling areas for better heat distribution at the PCB. The boost diode is a 600V silicon carbide Schottky diode,
which has an excellent switching characteristic (no charge storage). D82, a conventional silicon diode, is used to
initially charge the bulk capacitor from the rectified AC voltage, avoiding high surge current in the unipolar SiC
diode. The bulk capacitor C3 serves to store energy to reduce the second harmonic voltage ripple and it must
carry the switching frequency current. C3A keeps the commutation circuit short, it’s a bypass for high frequency
currents.
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4.1.3
PWM Converter (Two Transistor Forward)
The PWM converter is a two transistor forward topology. The operating frequency of 200 kHz is same as at the
PFC section. Main parts at the primary side are Q2A/Q2B and D22/D27. When the forward transistors Q2A/Q2B
are switched on simultaneously, energy is transferred to the output through the transformer. The transistors are
chosen as CoolMOS SPB07N60C3 because of their high switching speed. D22/D27 are EMCON diodes. They
serve to clamp the flyback voltages from the transformer leakage inductance, during reset of the transformer
magnetization, in every turn off cycle. The transformer Tr.1 provides galvanic isolation of the output from the line
and adapts the output voltages from the voltage of the bulk capacitor. The transformer consists of a ETD29/N97core by EPCOS with tape windings. The windings are interleaved to reduce leakage inductance and winding
losses. Main parts at the secondary are D20/D21, L3A, L6 and C36/C37 (12V-output) and Q19/Q21, L3B, L5 and
C15, C28 (5V-output). D20/D21 are 45-volts standard Schottky diodes, which handle the current in both
sequences, when the transistors are on in series rectifier mode or as freewheeling path if the transistors are off.
4.1.4
Synchronous Rectification
At the 5V-path there is used a synchronous rectifier with 30V-MOSFETs BSC022N03S featuring the Super-SO8package. It uses control waveforms generated by the secondary side of the transformer. Two MOSFETs in
parallel, Q19 and Q19A handle the freewheeling current in the “low” PWM state, and one MOSFET, Q21, handles
the series rectifier circuitry. The freewheeling synchronous rectifiers are turned on in the absence of the PWM
pulse output, driven through the body diode of Q18 during the primary transformer reset interval. When the
primary switches turn on, the gate of Q18 (previously biased negative), driven through R97 connected to the dot
transformer winding, starts switching positive.
4.2
Controlling Circuitry (“Control Board”)
R4B C9A
470k 2n2
R4A
470k
recAC+
1
C12
µ47
Vref
3 PFCCC
4 PFCCS
5 GNDS
C10
47p
6 PFCCL
R26
33k
PFCout
VCC
820k
C41 220p
1M
1M
1M
C11A
220µ
C11
µ47
PWMout
PFCVC 18
IC1 TDA 16888
C7
220p
R7
1k8
Vref
VBus = 380V
C5 47n
R5 C8
1k8 2n2
R3
10k
R1A
1M
R12D R12C R12B R12A
PFCVS 19
2 Vref
R1B
1M
VBus2
Aux vs 20
ac
R11 51k
R8
10k
recAC-
R1D R1C
820k 1M
R27 51k
Rosc
PWMRMP 15
PWMIN
8 PFCout
PWMSS 13
9 VCC
SYNC
10 PWMout
PWMCS 11
R93
10R
14
12
R82
10R
R14 R13D R13C R13B R13A
1M
1M
51k 820k 1M
R24
Vref
22k
R25
C22
10k
C13
4n7
47p
C14
R35
R23
µ47
1k
33k
16
7 GND
VCCtop
C6 100n
R16 390k
PFCFB 17
VDD
C92
µ47
XS
C95
47µ
5
6
IC9
HEF40106BT
C96
µ47
R83
4R7
Q10
BC817
9
8
11
10
13
12
2
3
4
5
6
9
C94
100n
4
R84
68R
R86
68R
G1A
G1B
R85
10R
R87
10R
Q9
BSP320S
R32
1k
VDDtop
IC8
SFH6711
R92
1k
3
Q7
BC807
Q14
BC817
R94
4R7
C93
100p
2
PFCout
14
D80
BAV99
1
S2A
C21
100p
Q8
BSP613P
Q6
BC817
14
open
1
R91
1k
D81
BAV99
IC7
HEF40106BT
VCC
Q16
BSP613P
R95
68R
8
G2B
11
10
R96
10R
13
12
Q15
BC807
R88
4R7
R89
68R
G2A
PWMout
7
Q12
BSP613P
R90
10R
Q11
BC807
Q13
BSP320S
Q17
BSP320S
7
GNDtop
4.2.1
General Description of the Combi-IC TDA16888
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The TDA 16888 comprises the complete control for power factor controlled switched mode power supplies. With
its PFC and PWM section being internally synchronized, it is suitable for two stage off-line converters with
worldwide input voltage range. It is designed to reduce system costs by less external parts count.
Special PFC features include:
• Dual loop control (average current and voltage sensing)
• Additional operation mode as auxiliary power supply
• Fast, soft switching totem pole gate drive (1A)
• Leading edge pulse width modulation
• Peak current limitation
• Overvoltage protection
Special PWM features include:
• Improved current mode control
• Fast, soft switching totem pole gate drive (1A)
• Soft-start management
• Trailing edge pulse width modulation
• 50% maximum duty cycle to prevent transformer saturation
• Individually adjustable Power Management
4.2.2
PFC Control
The TDA 16888 provides active power factor control in average current control mode. The “heart” of the PFC
section is an analog multiplier. It creates the current programming signal for the current amplifier OP2 by
multiplying the rectified line voltage with the output of the voltage amplifier so that the current programming signal
has the shape of the input voltage and an average amplitude which controls the output voltage.
At the Demoboard the external circuitry of the voltage amplifier (voltage sensing, compensating) consists of R13,
R14, R16, C5, and C6. The resistor R4 serves to monitor the actual rectified line voltage. R5, R7, R8, C7, and C8
are the components belonging to the current amplifier, the inductor current is monitored as a voltage drop at R6
(located at “main board”). R3, R26 determine the PFC current limit (approx. 6,5A). R11, R12 fix the overvoltage
thresholds.
4.2.3
PWM Control
The TDA 16888 provides an improved current mode control containing effective slope compensation as well as
enhanced spike suppression. The converter primary side switch current is monitored as voltage drop at R15
(located at “main board”). The amplified and “cleaned” current signal sensed at PWMCS (11), measurable at
PWMRMP (15), together with the output voltage control loop feedback signal at PWMIN (14), are both inputs of
the PWM comparator C8. Together they determine the actual duty cycle. C14 provides soft start of the PWM
section. The components of the output voltage control loop are located at the secondary side of the converter (on
the “main board”). The feedback signal is transferred across the isolation barrier via a low cost optocoupler, IC3.
4.2.4
Auxiliary Power Supply /Gate Drive Circuitry
The supply voltage of the control circuitry is generated by an additional winding of the PFC choke L2. This costefficient technique is featured by the TDA 16888 because of a special control loop, which ensures a continuous
generation of auxiliary power even at no load condition and sudden load drops.
Because of the very high operating frequency the PFC section power transistors (Q1A, Q1B) and the low side
power transistor (Q2A) of the PWM stage are driven by discrete high speed, high current driver stages using
small signal bipolar transistors and MOSFETs. That’s why the original gate drive signals at PFCOUT/ PWMOUT
are schmitt-trigerred and used as inputs of the discrete drivers. The gate drive signal of the high side power
transistor (Q2B) is transferred via a high-speed optocoupler, IC8 (SFH 6711), and amplified as described before.
The floating supply voltage for the high side driver circuitry is generated by another separate winding of L2.
7 of 21
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5
Power Losses / Efficiency
Measured power losses at nearly full load and different input voltages:
Vinac/V
Pin/W Pout/W V12v/V I12v/A V5v/V I5v/A
90
110
150
200
230
275
225
222
218
217
215
215
185,0
185,0
185,0
185,0
185,0
185,0
10,25
10,25
10,25
10,25
10,25
10,25
7,2
7,2
7,2
7,2
7,2
7,2
5,03
5,03
5,03
5,03
5,03
5,03
22,1
22,1
22,1
22,1
22,1
22,1
η/%
82,2
83,3
84,9
85,3
86,0
86,0
The best efficiency appears at high input voltage, the worst at the lowest. The reason is the variation of the line
current. Higher input currents result in increased conduction losses at the input rectifier, EMI Filter, PFC choke
and PFC current sense resistor. The RMS value of the PFC transistor current is much higher at low line
conditions, when the switches have to carry higher peak currents. Furthermore, the transistors switch at twice the
effective duty cycle in order to provide a higher step up rate for the PFC stage. The higher current values also
cause increased switching losses of the PFC stage. The behavior of the PWM stage doesn’t depend on the input
voltage, due to the pre-regulated bulk bus from the output of the PFC stage.
90
85
82,2
80
Efficiency [%]
83,3
84,9
85,3
86
86
75
70
65
60
55
50
50
100
150
200
250
300
Vin AC [V]
8 of 21
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200W SMPS Demonstration Board II
6
Power Loss Sources
The highest power dissipation appears at full load and low line condition.
Operation point:
Vin AC = 90V
Pin
= 225W
Pout = 185W
⇒Ploss = 40W
The distribution of the power losses is calculated or assumed by the help of measured device temperatures.
Power Loss Sources
Assumed Power
Dissipation/ W
1.5
3.5
3
1.5
5
1.5
2
3
3
4
3
2
3
4
40
EMI Filter
Line Rectifier (D1...4)
PFC Choke L2
Bulk Capacitor C3
PFC Transistors Q1
PFC Diode D5
Forward Transistors Q2
Transformer Tr.1
5V Rectifiers Q19, Q21
12V Rectifiers D20, D21
Output Choke L3
Output Capacitors C36, C37, C15, C28
Controlling, Driver, Supply Circuitry
Others
∑
5
5
4
3,5
3
3
3
3
3
3
2
2
1,5
1,5
2
1,5
1
ne
R
ie
r
ec
tif
EM
IF
ilt
PF (D er
Bu C C 1...
lk
ho 4)
PF Ca ke
pa
L
C
Tr cit 2
an or
C
s
Fo
PF isto 3
rw
r
ar C D s Q
d
Tr iod 1
e
an
D
5
5V Tra sist
o
ns
R
rs
Q
12 ect for
m 2
ifi
V
e
e
R
O
ec rs Q r Tr
ut
.
tif
pu
ie 19, 1
tC
rs
Q
C
21
D
on ap
O
2
ut
tro ac
0,
p
u
llin ito
D
g, rs C t Ch 21
D
riv 36, oke
er
L3
C
, S 37
up , .
pl ..
y
C
irc
u.
O ..
th
er
s
0
Li
Assumed Power Dissipation [W]
4
4
9 of 21
AN-CoolMOS-09
V 1.0
200W SMPS Demonstration Board II
7
Conducted EMI Measurements
Measuring of conducted noise with an EMI-Receiver FMLK 1518 at a Line-Impedance Stabilization Network
(LISN) NSLK 8128.
Conditions:
VAC in = 230V, Pout = 181,4W, main board in a metal case.
Phase 1, Average
Phase 2, Average
As it can be seen from the figures above the measured EMI spectra are below the norm limit lines.
10 of 21
AN-CoolMOS-09
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200W SMPS Demonstration Board II
8
Construction of magnetic components
8.1
PFC choke
Core: MAGNETICS Ringcore 77930 - A7; L = 490 µH (Pin1 - Pin8)
Hole arrangement
View in mounting direction
N3
N1
Pin 1
N2
N1: 56 turns 0,5mm ∅
N2: 4 turns 0,2mm ∅
N3: 4 turns 0,2mm ∅
2
N2
N1
Pin 8
11 of 21
3
7
4
N3
6
5
AN-CoolMOS-09
V 1.0
200W SMPS Demonstration Board II
8.2
Main transformer
Core: ETD29/16/10, N97
without airgap
ratio: 23:2:1
N11= 23
N2= 4
N12= 23
N3= 2
N11/ N12 are series connected (on PCB)
Windings:
Cu-tape
N1:
13,4 x 0,035 mm
N2:
13,4 x 0,070 mm
N3:
13,4 x 0,100 mm
Design: interleaved
N12= 23
N2= 4
N3= 2
N11= 23
Core
12 of 21
AN-CoolMOS-09
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200W SMPS Demonstration Board II
8.3
Output filter choke
Core: ETD29/16/10, N97
Air gap (total): 1,5 mm Î Al= 93,4nH
ÎInductance: L1= 27µH
L2= 4,6µH
Windings:
Cu-tape
N1:
15,4 x 0,050 mm
N2:
15,4 x 0,150 mm
Design:
N1= 17
N2= 7
Core
13 of 21
AN-CoolMOS-09
V 1.0
AN-CoolMOS-09
V 1.0
[
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C8S 口
CS0 口
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14 of 21
200W SMPS Demonstration Board II
m川巴
们们川川山
配旦
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Main Board - Scaling 1:1
9.1
9
PCB Layout
l二 1
口----------，
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日卢----------，
Main Board/ Top/ Components
979
200W SMPS Demonstration Board II
Main Board /Top / Copper
15 of 21
AN-CoolMOS-09
V 1.0
200W SMPS Demonstration Board II
Main Board/ Bottom/ Bottom View/ Copper
16 of 21
AN-CoolMOS-09
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200W SMPS Demonstration Board II
9.2
Control Board- Scaling 1:1
Control Board/ Top/ Components
Control Board/ Top/ Copper
Control Board/ Bottom/ Bottom View/ Components
Control Board/ Bottom/ Bottom View/ Copper
10 Bill of Materials
10.1 Main Board
Part
Value
+5V
Package
Position (mil)
FLSTL6,3
(500 3275)
+12V
FLSTL6,3
(500 4075)
AC_IN
KLEMME-3
(200 5150)
C22,5B11
(4650 5300)
C2
u47/X2
C3
150u/450V
EB35D
(6375 5053.74)
C3A
100n/630V
C15B7
(3375 4387.5)
C3B
100n/630V
C15B7
(6200 825)
C4
2n2/1kV
C7,5B4
(3937.5 4537.5)
C15
4m7/10V
C16
68n
1206
(700 200)
C17
2n2
1206
(500 200)
C18
47u/63V
E3,5-8
(5675 4375)
C24
u47/X2
C22,5B11
(2475 5300)
C25
4n7/Y
C10B6
(2125 5550)
C26
4n7/Y
C10B6
(2125 5025)
C28
4m7/10V
C32
2n2/1kV
C7,5B4
(2900 1800)
C33
2n2/1kV
C7,5B4
(2900 1625)
(1050 1525)
(1050 3275)
17 of 21
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200W SMPS Demonstration Board II
Value
Package
Position (mil)
C36
2m2/25V
(362.5 1112.5)
C37
2m2/25V
(362.5 2762.5)
C39
4n7/Y
C10B6
(1050 3800)
C86
u47/X2
C22,5B11
(1175 5300)
C87
u47
1812
(5450 4450)
C88
u47
1812
(5450 4175)
C89
u47
1812
(6425 3375)
C90
u47
1812
(6425 3200)
C91
47u/63V
E3,5-8
(6275 4150)
C97
4n7/Y
C10B6
(6812.5 4162.5)
C98
4n7
1206
(3362.5 1912.5)
C99
2n2
1206
(1143.75 250)
C100
100n
1206
(6750 3418.75)
C101
100n
1206
(5200 4075)
D1...4
KBU8K
KBU-L
(4375 5400)
D5
SDD04S60
DPAK
(4150 3925)
D6
IDD03E60
DPAK
(5837.5 3700)
D10
BAV99
SOT-23
(4681.25 4206.25)
D11
BZX84C13
SOT-23
(5287.5 4250)
D12
TMBYV10-60
MELF
(5062.5 4400)
D13
TMBYV10-60
MELF
(4725 4400)
D20
MBRB2545
D2PAK
(2737.5 2325)
D21
MBRB2545
D2PAK
(2100 2325)
D22
IDD03E60
DPAK
(6575 650)
D27
IDD03E60
DPAK
(5875 642.52)
D76
TMBYV10-60
MELF
(6425 3750)
D77
TMBYV10-60
MELF
(6425 3600)
D78
BZX84C13
SOT-23
(6725 3537.5)
D79
BAV99
SOT-23
(6862.5 2637.5)
D82
1N5408
DO201-15
(4531.25 4625)
BO3,2-P
(6889.76 3818.9)
BO3,2-P
(1574.8 3818.9)
SH22
(600 5300)
FLSTL6,3
(500 4325)
E$5
E$9
FUSE
4AT
GND
GND.
FLSTL6,3
(500 3525)
TL431CD
SO-8
(250 600)
IC3
CNY17-3
DIL06
(987.5 475)
L1
2x1m2
82722J
(1700 5300)
L2
500u
INF-PFC
(5275 5262.5)
L3
36/6uH
RM14-12A
(2075 1000)
L4
2x1m2
82722J
(3000 5300)
L5
1u
INAIR20A
(1050 2400)
L6
1u
INAIR8A
(312.5 1937.5)
IC2
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200W SMPS Demonstration Board II
Part
Value
Package
Position (mil)
LED_5V
LED_12V
Green/LC
LED3
(400 3706.25)
Red
LED3
(400 3893.75)
Q1A
SPB07N60C3
D2PAK
(3400 3925)
Q1B
SPB07N60C3
D2PAK
(2650 3925)
Q2A
SPB07N60C3
D2PAK
(5862.5 1625)
Q2B
SPB07N60C3
D2PAK
(6700 1625)
Q3
BSP129
SOT-223
(4887.5 4100)
Q5
BSP129
SOT-223
(6787.5 3100)
Q18
BSP318
SOT-223
(3350 1587.5)
Q19
BSC022N03S
P-TDSON-8
(4012.5 2325)
Q19A
BSC022N03S
P-TDSON-8
(3375 2325)
Q21
BSC022N03S
P-TDSON-8
(4650 2325)
R2
220k/2W
0411/15
(4100 4375)
R6
0R15/1W
R-SMR
(4900 3700)
R15
R47
R-SMR
(6112.5 2337.5)
R19
5k1
1206
(450 500)
R20
5k1
1206
(700 650)
R21
10k
1206
(450 350)
R22
680R
1206
(700 500)
R28
4k7
1206
(5112.5 4168.75)
R29
1R
1206
(5300 4425)
R30
S14K275
S14K275
(3425 5300)
R39
1k
1206
(700 350)
R44
4R7/0,6W
0207/10
(2900 1925)
R45
4R7/0,6W
0207/10
(2900 1500)
R48
1k8
1206
(593.7 3897.98)
R80
1R
1206
(6375 3950)
R81
4k7
1206
(6750 3325)
R97
10R
1206
(3550 1712.5)
R98
1R
1206
(4387.5 2087.5)
R99
1k8
1206
(593.75 3806.25)
R100
1R
1206
(3750 2075)
R101
1R
1206
(3112.5 2075)
R102
1M2/Netz
0411/15
(875 5300)
R103
47R
1206
(3362.5 1812.5)
R104
1k8
1206
(593.75 3712.5)
S$63
BO3,2-P
(3825 5400)
SVB_M_C
1X20SMDI
(5575 2850)
TR.1
RM14-12A
(4550 1000)
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200W SMPS Demonstration Board II
10.2 Control Board
Part
Value
Package
Position (mil)
C5
47n
1206
(900 968.75)
C6
100n
1206
(818.75 968.75)
C7
220p
1206
(1699.36 1050)
C8
2n2
1206
(1699.36 968.75)
C9A
2n2
1206
(1699.36 1131.26)
C10
47p
1206
(1424.36 906.24)
C11
u47
1812
(1511.85 528.12)
C11A
220u/25V
E3,5-8
(150 1025)
C12
u47
1812
(1561.87 1103.13)
C13
47p
1206
(1424.37 825)
C14
u47
1812
(1252.48 528.12)
C21
100p
1206
(1424.37 656.25)
C22
4n7
1206
(1424.37 743.75)
C41
220p
1206
(1424.36 987.5)
C92
u47
1812
(975 749.36)
C93
100p
1206
(1653.13 756.25)
C94
100n
1206
(2018.75 537.5)
C95
47u/63V
E3,5-8
(1965.63 993.75)
C96
u47
1812
(2287.5 703.13)
D80
BAV99
SOT-23
(1700 571.87)
D81
BAV99
SOT-23
(1678.12 734.37)
IC1
TDA16888
SO-20L
(1380.61 918.75)
IC7
HEF40106BT
SO-14
(849.36 981.25)
IC8
SFH6711
DIL-08
(1943.11 631.25)
IC9
HEF40106BT
SO-14
(2175 988.14)
Q6
BC817
SOT-23
(618.75 884.38)
Q7
BC807
SOT-23
(487.5 884.38)
Q8
BSP613P
SOT-223
(468.11 643.75)
Q9
BSP320S
SOT-223
(199.36 643.75)
Q10
BC817
SOT-23
(818.75 687.5)
Q11
BC807
SOT-23
(818.76 815.63)
Q12
BSP613P
SOT-223
(736.86 643.75)
Q13
BSP320S
SOT-223
(1005.61 643.75)
Q14
BC817
SOT-23
(2275.01 659.37)
Q15
BC807
SOT-23
(2275 471.88)
Q16
BSP613P
SOT-223
(1961.86 181.25)
Q17
BSP320S
SOT-223
(2224.35 181.25)
R1A
1M
1206
(568.11 550)
R1B
1M
1206
(568.11 725)
R1C
1M
1206
(568.11 900)
R1D
820k
1206
(568.11 1075)
20 of 21
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200W SMPS Demonstration Board II
Part
Value
Package
Position (mil)
R3
10k
1206
(1549.36 478.13)
R4A
470k
1206
(180.61 550)
R4B
470k
1206
(180.61 725)
R5
1k8
1206
(1374.36 478.13)
R7
1k8
1206
(1233.74 587.5)
R8
10k
1206
(1699.36 887.5)
R11
51k
1206
(443.75 1087.5)
R12A
1M
1206
(443.11 550)
R12B
1M
1206
(443.11 725)
R12C
1M
1206
(443.11 900)
R12D
820k
1206
(443.11 1075)
R13A
1M
1206
(343.11 550)
R13B
1M
1206
(343.11 725)
R13C
1M
1206
(343.11 900)
R13D
820k
1206
(343.11 1075)
R14
51k
1206
(318.75 1087.5)
R16
390k
1206
(981.26 968.75)
R23
33k
1206
(1556.25 312.5)
R24
22k
1206
(1118.75 950)
R25
10k
1206
(1121.87 950)
R26
33k
1206
(1714.98 987.5)
R27
51k
1206
(568.76 1087.5)
R32
1k
1206
(1150 312.5)
R35
1k
1206
(1121.87 775)
R82
10R
1206
(1043.75 531.26)
R83
4R7
1206
(256.25 940.63)
R84
68R
1206
(700 187.5)
R85
10R
1206
(787.5 187.5)
R86
68RR
1206
(956.25 187.5)
R87
10R
1206
(868.75 187.5)
R88
4R7
1206
(718.75 706.25)
R89
68R
1206
(878.13 531.25)
R90
10R
1206
(962.5 531.25)
R91
1k
1206
(1700.01 584.38)
R92
1k
1206
(1718.76 756.25)
R93
10R
1206
(2168.75 687.5)
R94
4R7
1206
(2293.75 459.38)
R95
68R
1206
(1781.25 100)
R96
10R
1206
(1700 100)
1X20/90I
(1205.61 400)
SVB_C_M
21 of 21
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V 1.0