TSP12N60M / TSF12N60M
600V N-Channel MOSFET
General Description
Features
This Power MOSFET is produced using Truesemi‘s
advanced planar stripe DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction based on half bridge
topology.
•
•
•
•
•
•
12.0A, 600V, RDS(on) = 0.650Ω @VGS = 10 V
Low gate charge ( typical 52nC)
High ruggedness
Fast switching
100% avalanche tested
Improved dv/dt capability
{
D
●
◀
{G
G DS
TO-220
▲
●
●
TO-220F
GD S
{S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°Cunless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
TSP12N60M
- Continuous (TC = 100°C)
IDM
Drain Current
- Pulsed
TSF12N60M
Units
V
12.0
12.0*
A
7.4
7.4*
A
48
48 *
A
600
(Note 1)
VGSS
Gate-Source Voltage
± 30
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
865
mJ
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 1)
23.1
4.5
-55 to +150
mJ
V/ns
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
231
1.85
54
0.43
* Drain current limited by maximum junction temperature.
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
TSP12N60M
0.54
TSF12N60M
2.33
Units
°C/W
RθCS
Thermal Resistance, Case-to-Sink Typ.
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
62.5
62.5
°C/W
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TSP12N60M / TSF12N60M
Electrical Characteristics
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
600
--
--
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
--
0.7
--
V/°C
1
µA
IDSS
Zero Gate Voltage Drain Current
VDS = 600 V, VGS = 0 V
--
--
VDS = 480 V, TC = 125°C
--
--
10
µA
IGSSF
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
IGSSR
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
2.0
--
4.0
V
0.65
Ω
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 6.0A
--
0.53
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
--
1850
--
pF
--
180
--
pF
--
20
--
pF
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 300 V, ID = 12.0A,
RG = 25 Ω
(Note 4, 5)
VDS = 480 V, ID = 12.0A,
VGS = 10 V
(Note 4, 5)
--
30
--
ns
--
90
--
ns
--
140
--
ns
--
90
--
ns
--
52
-
nC
--
8.5
--
nC
--
20.0
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
12.0
A
ISM
--
--
48.0
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 12.0 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
--
430
--
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 12.0 A,
dIF / dt = 100 A/µs
--
5.0
--
µC
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 11.0mH, IAS = 12.0 A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 12.0 A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
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Typical Characteristics
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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Typical Characteristics
(Continued)
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 9-1. Maximum Safe Operating Area
for TSP12N60M
Figure 8. On-Resistance Variation
vs Temperature
Figure 9-2. Maximum Safe Operating Area
for TSF12N60M
Figure 10. Maximum Drain Current
vs Case Temperature
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Typical Characteristics
(Continued)
Figure 11-1. Transient Thermal Response Curve
for TSP12N60M
Figure 11-2. Transient Thermal Response Curve
for TSF12N60M
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Gate Charge Test Circuit & Waveform
VGS
SameType
asDUT
50KΩ
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
V
D
S
R
L
V
D
S
9
0
%
V
D
D
V
G
S
R
G
1
0
%
V
G
S
D
U
T
1
0
V
td
(o
n
)
tr
td
(o
ff)
to
n
tf
to
ff
Unclamped Inductive Switching Test Circuit & Waveforms
B
V
D
S
S
1
E
IAS2 -------------------A
S=---- L
2
B
V
D
S
S-V
D
D
L
V
D
S
B
V
D
S
S
IAS
ID
R
G
V
D
D
D
U
T
1
0
V
tp
ID(t)
V
D
S(t)
V
D
D
tp
T
im
e
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Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
D U T
V
D S
_
I
S D
L
D r iv e r
R
V
V GS
( D r iv e r )
G S
G
S am e T ype
as D U T
V
D D
• d v / d t c o n t r o lle d b y R G
• I S D c o n t r o lle d b y p u ls e p e r io d
G a te P u ls e W id th
D = -------------------------G a t e P u ls e P e r io d
10V
IF M , B o d y D io d e F o r w a r d C u r r e n t
I
S D
d i/d t
( D U T )
IR
M
B o d y D io d e R e v e r s e C u r r e n t
V DS
( D U T )
B o d y D io d e R e c o v e r y d v / d t
V
S D
V
D D
B o d y D io d e
F o r w a r d V o lt a g e D r o p
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