深圳市美芯微电子有限公司麦肯单片机授权一级代理商 电话；０７５５－３６８５７６０９／２７９４５５５１／２９４９１８８２ 地址：深圳市宝安区宝源路名优产品采购中心Ｂ１区７２１室 MDT10P432 1. General Description This 8-bit Micro-controller with built-in carrier generator uses a fully static CMOS technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 512 words of ROM, and 28 bytes of static RAM. 2. Features Fully CMOS static design 8-bit data bus On chip ROM size : 512 words Internal RAM size : 28 bytes (24general purpose registers, 4 special registers) 34 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.0V ~ 5.0 V Addressing modes include direct, indirect and relative addressing modes Power-on Reset Internal RC 432K, 440K, 455K, 480KHz select in option. System clock : 455KHz crystal (OSC1 cap 50P; OSC2 cap 50P) Auto detect external crystal on board . PA0-7 : 8 input only pins with pull-high resistor and input low wakeup detect circuit. PB0 : CMOS output. PB1~7 : Seven open drain output pins. Built in remote control carrier synthesizer Fosc/8 (56.9K) or Fosc/12 (37.9K) by firmware setting. Option used PB0 NMOS without BJT. 4096 clocks for external oscillator start up time. 3. Applications Remote controller This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mx mcu.com.cn 1 of 13 2010.8 Ver. 1.5 MDT10P432 4. Pin Assignment ※ P – PDIP, S - PSOP MDT10P432P11 MDT10P432S11 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 MDT10P432P13 MDT10P432S13 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA5 PA4 PA1 PA0 VDD PB7 PB6 PB5 PB4 MDT10P432P21 MDT10P432S21 PA5 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4 MDT10P432P31 MDT10P432S31 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MDT10P432P35 MDT10P432S35 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PA2 PA1 PA0 VDD PB7 PB6 PB5 PB4 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 2 of 13 2010.8 Ver. 1.5 MDT10P432 5. Order Information ROM RAM (Words) (Bytes) MDT10P432P11 0.5K MDT10P432P13 MDT10P432P21 Device MDT10P432P31 I/O Package mil Remark 24 14 (6 input; 8 output) 18-DIP 300 18 pin ; 6 input (no PA 4~5) ; 8 output 0.5K 24 16 (8 input; 8 output) 18-DIP 300 18 pin ; 8 input ; 8 output; (no OSC1&2) 0.5K 24 16 (8 input; 8 output) 20-DIP 300 0.5K 24 12 (6 input; 6 output) 16-DIP 300 20 pin ; 8 input ; 8 output 16 pin ; 6 input (no PA 4&5) ; 6 output (no PB 3&4) 16 pin ; 6 input (no PA 4~5) ; 8 output; MDT10P432P35 0.5K 24 14 (6 input; 8 output) 16-DIP 300 MDT10P432S11 0.5K 24 14 (6 input; 8 output) 18-SOP 300 18 pin ; 6 input (no PA 4~5) ; 8 output MDT10P432S13 0.5K 24 16 (8 input; 8 output) 18-SOP 300 18 pin ; 8 input ; 8 output; (no OSC1&2) MDT10P432S21 0.5K 24 16 (8 input; 8 output) 20-SOP 300 MDT10P432S31 MDT10P432S35 0.5K 0.5K 24 24 12 (6 input; 6 output) 14 (6 input; 8 output) 16-SOP 16-SOP 150 150 (no OSC1&2) 20 pin ; 8 input ; 8 output 16 pin ; 6 input (no PA 4&5) ; 6 output (no PB 3&4) 16 pin ; 6 input (no PA 4~5) ; 8 output; (no OSC1&2) 6. Block Diagram Stack Tw o Levels RA M 24×8 RO M 512×14 Port A 9 bits Program C ounters 9 bits Port PA 0~PA 7 8 bits 14 bits Instruction R egister Special R egister Port PB0 D 0~D 7 Port B External X T Instruction D ecoder Internal R C Port PB1~PB7 C ontrol C ircuit D ata 8bit Pow er on R eset Pow er D ow n R eset W orking R egister Status R egister A LU This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 3 of 13 2010.8 Ver. 1.5 MDT10P432 7. Pin Function Description Pin Name I/O PA0~PA7 I Function Description Port A, TTL input level. Built in 50K ohm pull-high resistor. In sleep mode, a high-to-low change on any pin will cause chip reset. PB0 O CMOS output pin. Enable NMOS sink 250mA by option (replace BJT) PB1~PB7 O Port B open drain output pins, 50K ohm pull-high resistor. OSC1 I Crystal oscillation input pin OSC2 O Crystal oscillation output pin Vdd Power supply Vss Ground 8. Memory Map 8.1 Program memory : 000H Program memory 1FEH 1FFH Reset Vector 8.2 Register Map Address Description 00 Indirect Addressing Register 01 Unimplemented 02 PC 03 STATUS 04 MSR 05 Port A (Input Only) 06 Port B output register 07 Unimplemented 08~1F Internal RAM, General Purpose Register This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mx mcu.com.cn http://www.mdtic.com.tw 4 of 13 2010.8 Ver. 1.5 MDT10P432 (1) IAR ( Indirect Address Register) : R0 (2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK (3) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 /PF Power loss Flag bit 4 /LPT Low power detect =0 : Vdd is lower than 2.1 ~ 2.3V =1 : Vdd is higher than 2.1 ~ 2.3V 5 —— General purpose bit 7-6 —— Carrier frequency control bits =00 No carrier (default) =01 Fosc/8, 1/2 duty =10 Fosc/12, 1/2 duty =11 Fosc/12, 1/3 duty (1/3 – Hi ; 2/3 - Low) (4) MSR (Memory Select Register) : R4 (5) PORT A : R5 Bit 7-0 : Port A data input (6) PORT B : R6 Bit 7-1 : PB7-PB1 output register (open drain output) Bit 0 : PB0 output register (CMOS output) This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 5 of 13 2010.8 Ver. 1.5 MDT10P432 9. Reset Condition for all Registers Register Address Power-On Reset IAR 00h － PC 02h 1111 1111 STATUS 03h 0001 1xxx MSR 04h 111x xxxx PB Output data 06h 1111 111# Note : “ x “＝unknown, “ – “＝unimplemented, read as “0” “# “＝value depends on condition 10. Instruction Set 010000 00000000 Mnemonic Operands NOP No operation None 010000 00000010 SLEEP Sleep mode 010000 00000100 RET Return 0→WT, stop OSC Stack→PC 010000 00000rrr CPIO R Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register None 011001 trrrrrrr INCR R, t Increment register [R(0~3) ↔ R(4~7)]→t R + 1→t 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣W→t (R+/W+1→t) R ﹣1→t 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t None 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z Instruction Code Function Operating Status TF, PF None Z Z This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 6 of 13 2010.8 Ver. 1.5 MDT10P432 010110 trrrrrrr Mnemonic Operands RRR R, t Rotate right register 010101 trrrrrrr RLR Rotate left register 010000 1xxxxxxx CLRW 010001 0rrrrrrr CLRR 0000bb brrrrrrr BCR 0010bb brrrrrrr BSR 0001bb brrrrrrr Instruction Code Function Operating Status C Clear working register R(n) →R(n-1), C→R(7), R(0)→C R(n)→r(n+1), C→R(0), R(7)→C 0→W Clear register 0→R Z R, b Bit clear 0→R(b) None R, b Bit set 1→R(b) None BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine None 1010nn nnnnnnnn LJUMP n Long JUMP to address n→PC, PC+1→Stack n→PC 110000 nnnnnnnn CALL n Call subroutine None 110001 iiiiiiii RTIW i Return, place immediate to W 11001n nnnnnnnn JUMP n JUMP to address n→PC, PC+1→Stack Stack→PC, i→W n→PC R, t R C Z None None None Note : W CPIO HC Z C PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Control I/O port register Half carry Zero flag Carry flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : Bit position Target 0 : Working register 1 : General register R i n / x : : : : : General register address Immediate data ( 8 bits ) Immediate address Complement Don’t care This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 7 of 13 2010.8 Ver. 1.5 MDT10P432 11. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Max Unit 2.0 6.0 V Vdd=5V -0.6 1.0 V PA Vdd=5V 2.0 Vdd+0.6 V Input leakage current Vdd=5V +/-1 μA Vdd Operating voltage VIL IIL Typ Input Low Voltage PA VIH Min Input high Voltage VOL Output Low Voltage PB7~0 PB0 enable 250mA NMOS PB0 enable 250mA NMOS Vdd=5V, IOL=20mA 0.6 V Vdd=5V, IOL=5mA 0.2 V Vdd=5V, IOL=20mA 0.08 V Vdd=5V, IOL=20mA 0.03 V Vdd=3V, sink current 250 mA Vdd=2V, sink current 100 mA Vdd=5V, IOH= -20mA 2.8 V Vdd=5V, IOH= -5mA 4.2 V 1.8 V VOH Output High Voltage PB0 Vpr Power Edge-detector Reset Voltage This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 8 of 13 2010.8 Ver. 1.5 MDT10P432 12. PA0 ~ PA7 Equivalent Circuit Sleep Input low wake_up PA0~7: Pull_Hi 50K Data Bus TTL Input Resistor Read TTL Input Level Port Input Pad 13. (A) PB0 Equivalent Circuit 250mA NMOS enable IR Carrier D Q Set I/O C DFFRA Latch /Reset RB D1 s Q D0 Port Output Pad QB Replace BJT Data Bus Read This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 9 of 13 2010.8 Ver. 1.5 MDT10P432 (B) PB1~7 Equivalent Circuit D TRIS C Reset PB Q PB1~7: Pull_Hi 50K DFFPA Latch QB Port Output Pad Data Bus Read 14. Application circuit (reference) (A). Enable internal 455KHz & 250 mA NMOS (Without BJT) Note : Power Vdd & Vss must used metal line to IC Vdd & Vss with shortest distance IR must used metal line to Vdd & PB0 VCC U1 15 17 C3 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VDD OSC1 + 10u 1 16 2 C4 0.1u 6 18 19 2 3 20 1 4 5 7 8 9 10 11 12 13 14 MDT10P432P21/S21 C4 by-pass capacitor must closed the IC Vdd and Vss 1 1 1 1 1 1 1 1 S1 S9 S17 S25 S33 S41 S49 S57 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S2 S10 S18 S26 S34 S42 S50 S58 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S3 S11 S19 S27 S35 S43 S51 S59 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S4 S12 S20 S28 S36 S44 S52 S60 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S5 S13 S21 S29 S37 S45 S53 S61 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S6 S14 S22 S30 S38 S46 S54 S62 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S7 S15 S23 S31 S39 S47 S55 S63 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S8 S16 S24 S32 S40 S48 S56 S64 VCC R1 10 D1 IR This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 10 of 13 2010.8 Ver. 1.5 2 2 2 2 2 2 2 2 MDT10P432 VCC 14 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VDD C3 + 1 10u PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 C4 2 0.1u 5 VSS 15 16 1 2 17 18 3 4 6 7 8 9 10 11 12 13 1 1 S1 S9 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S2 S10 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S3 S11 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S4 S12 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S5 S13 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S6 S14 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S7 S15 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S8 2 S16 2 MDT10P432P13/S13 1 C4 by-pass capacitor must be closed to the IC Vdd and Vss 1 1 1 1 1 S17 S25 S33 S41 S49 S57 S18 S26 S34 S42 S50 S58 S19 S27 S35 S43 S51 S59 S20 S28 S36 S44 S52 S60 S21 S29 S37 S45 S53 S61 S22 S30 S38 S46 S54 S62 S23 S31 S39 S47 S55 S63 S24 2 S32 2 S40 2 S48 2 S56 2 S64 2 VCC R1 10 D1 IR VCC 13 VDD C3 + 1 10u C4 2 0.1u 4 VSS PA0 PA1 PA2 PA3 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 14 15 16 1 2 3 5 6 7 8 9 10 11 12 MDT10P432 P35/S35 C4 by-pass capacitor must be closed to the IC Vdd and Vss 1 1 1 1 1 1 1 1 S1 S9 S17 S25 S33 S41 S49 S57 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S2 S10 S18 S26 S34 S42 S50 S58 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S5 S13 S21 S29 S37 S45 S53 S61 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S6 S14 S22 S30 S38 S46 S54 S62 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S7 S15 S23 S31 S39 S47 S55 S63 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S8 S16 S24 S32 S40 S48 S56 S64 2 2 2 2 2 2 2 2 VCC R1 10 D1 IR This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 11 of 13 2010.8 Ver. 1.5 MDT10P432 (B). Enable internal 455KHz , disable 250 mA NMOS Note : Power Vdd & Vss must used metal line to IC Vdd & Vss with shortest distance VCC 14 VDD C3 + 2 1 10u C4 0.1u 5 VSS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 15 16 1 2 17 18 3 4 6 7 8 9 10 11 12 13 1 1 MDT10P432P13/S13 1 C4 by-pass capacitor must be closed to the IC Vdd and Vss 1 1 1 1 1 S1 S9 S17 S25 S33 S41 S49 S57 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S2 S10 S18 S26 S34 S42 S50 S58 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S3 S11 S19 S27 S35 S43 S51 S59 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S4 S12 S20 S28 S36 S44 S52 S60 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S5 S13 S21 S29 S37 S45 S53 S61 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S6 S14 S22 S30 S38 S46 S54 S62 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S7 S15 S23 S31 S39 S47 S55 S63 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S8 2 S16 2 S24 2 S32 2 S40 2 S48 2 S56 2 S64 2 VCC R1 10 D1 IR R2 1 Q1 3 NPN CBE 2 1K VCC 13 VDD C3 + 1 10u C4 2 0.1u 4 VSS PA0 PA1 PA2 PA3 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 14 15 16 1 2 3 5 6 7 8 9 10 11 12 MDT10P432P35/S35 C4 by-pass capacitor must be closed to the IC Vdd and Vss 1 1 1 1 1 1 1 1 S1 S9 S17 S25 S33 S41 S49 S57 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S2 S10 S18 S26 S34 S42 S50 S58 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S5 S13 S21 S29 S37 S45 S53 S61 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S6 S14 S22 S30 S38 S46 S54 S62 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S7 S15 S23 S31 S39 S47 S55 S63 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S8 S16 S24 S32 S40 S48 S56 S64 2 2 2 2 2 2 2 2 VCC R1 10 D1 IR R2 2 1K 1 Q1 3 NPN CBE This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mxmcu.com.cn http://www.mdtic.com.tw 12 of 13 2010.8 Ver. 1.5 MDT10P432 (C). Disable internal 455KHz & 250 mA NMOS Note : Power Vdd & Vss must used metal line to IC Vdd & Vss with shortest distance VCC C1 15 17 2 U1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VDD OSC1 2 1 50P Y1 455KHz C2 2 16 1 1 C3 1 50P + 0.1u 2 10u C4 6 18 19 2 3 20 1 4 5 7 8 9 10 11 12 13 14 S1 1 S9 1 MDT10P432P21/S21 C4 by-pass capacitor must closed the IC Vdd and Vss S17 1 S25 1 S33 1 S41 1 S49 1 S57 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S2 S10 S18 S26 S34 S42 S50 S58 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S3 S11 S19 S27 S35 S43 S51 S59 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S4 S12 S20 S28 S36 S44 S52 S60 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S5 S13 S21 S29 S37 S45 S53 S61 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S6 S14 S22 S30 S38 S46 S54 S62 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S7 S15 S23 S31 S39 S47 S55 S63 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S8 S16 S24 S32 S40 S48 S56 S64 VCC R1 10 D1 IR R2 2 1 Q1 3 NPN CBE 1K This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw http://www.mxmcu.com.cn 13 of 13 2010.8 Ver. 1.5 2 2 2 2 2 2 2 2