AD EVAL-AD1992EB

Audio Switching Amplifier
AD1992
FEATURES
GENERAL DESCRIPTION
Integrated stereo modulator and power stage
<0.002% THD + N
102 dB dynamic range (A-weighted)
2 × 10 W output power (4 Ω, <0.01% THD + N)
RDS-ON < 0.3 Ω (per transistor)
PSRR > 65 dB
On-off-mute pop noise suppression
EMI optimized modulator
Short-circuit protection
Overtemperature protection
Low cost DMOS process
The AD1992 is a 2-channel, bridge tied load (BTL), switching
audio power amplifier with integrated Σ-Δ modulator. The
modulator accepts a single-ended, analog input signal and
converts it to a switching waveform to drive speakers directly. A
digital, microprocessor-compatible interface provides control of
reset, mute, and PGA gain, as well as feedback signals for thermal
and overcurrent error conditions. The output stage can operate
over a power supply voltages range of 8 V to 20 V. The analog
modulator and digital logic operate from a 5 V supply.
APPLICATIONS
Advanced televisions
Compact multimedia systems
Minicomponents
FUNCTIONAL BLOCK DIAGRAM
PGA0
AVDD
NFL–
PGA1
NFL+
FEEDBACK
NETWORK
DVDD
PVDD
AD1992
AINL
A1
Σ-Δ
MODULATOR
PGA
OUTL+
A2
B1
LEVEL
SHIFTER
AND
DEAD TIME
CONTROL
AINR
Σ-Δ
MODULATOR
PGA
OUTL–
B2
H-BRIDGE
C1
OUTR+
C2
CLKI
CLKO
OSCILLATOR
REF_FILT
VOLTAGE
REFERENCE
MODE CONTROL
LOGIC AND
POP/CLICK
SUPPRESSION
D1
PGND
FEEDBACK
NETWORK
05776-001
DCTRL0
DCTRL1
DCTRL2
NFR–
NFR+
ERR0
ERR1
ERR2
MUTE
RESET
AGND
OUTR–
D2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD1992
TABLE OF CONTENTS
Features .............................................................................................. 1
Overview ..................................................................................... 13
Applications....................................................................................... 1
Σ-Δ Modulator............................................................................ 13
General Description ......................................................................... 1
MUTE and RESET ..................................................................... 13
Functional Block Diagram .............................................................. 1
Gain Structure............................................................................. 13
Revision History ............................................................................... 2
Power Stage ................................................................................. 14
Specifications..................................................................................... 3
Clocking....................................................................................... 15
Absolute Maximum Ratings............................................................ 5
Protection Circuits and Error Reporting ................................ 16
ESD Caution.................................................................................. 5
Application Circuits ....................................................................... 17
Pin Configuration and Function Descriptions............................. 6
Outline Dimensions ....................................................................... 18
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 18
Theory of Operation ...................................................................... 13
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD1992
SPECIFICATIONS
Test conditions, unless otherwise specified.
Table 1.
Parameter
SUPPLY VOLTAGES
AVDD
DVDD
PVDD
AMBIENT TEMPERATURE
LOAD IMPEDANCE
CLOCK FREQUENCY
PGA GAIN
MEASUREMENT BANDWIDTH
Ratings
5V
5V
12 V
25°C
6Ω
12.288 MHz
0 dB
20 Hz to 20 kHz
Table 2.
Parameter
RDS-ON
Per High-Side Transistor
Per Low-Side Transistor
MAXIMUM CURRENT THROUGH OUTx
THERMAL WARNING ACTIVE
THERMAL SHUTDOWN ACTIVE
RESTORE TEMPERATURE AFTER THERMAL SHUTDOWN
Min
Typ
Max
Unit
Test Conditions/Comments
260
210
5
135
150
120
355
265
mΩ
mΩ
A
°C
°C
°C
T = 25°C
T = 25°C
Peak
Die temperature
Die temperature
Die temperature
Table 3. Performance Specifications
Parameter
TOTAL HARMONIC DISTORTION AND NOISE (THD + N)
SIGNAL-TO-NOISE RATIO (SNR)
DYNAMIC RANGE (DNR)
CROSSTALK (LEFT-TO-RIGHT OR RIGHT-TO-LEFT)
Typ
0.003
0.006
0.01
0.02
102
102
−100
Unit
%
%
%
%
dB
dB
dB
Test Conditions/Comments
PGA = 0 dB, PO = 1 W, 1 kHz
PGA = 6 dB, PO = 1 W, 1 kHz
PGA = 12 dB, PO = 1 W, 1 kHz
PGA = 18 dB, PO = 1 W, 1 kHz
1 kHz, A-weighted, 0 dB referred to 1% THD + N output
1 kHz, A-weighted, −60 dB referred to 1% THD + N output
PGA = 0 dB, PO = 5 W, 1 kHz
Table 4. DC Specifications
Parameter
INPUT IMPEDANCE
OUTPUT DC OFFSET
Typ
20
±4
Unit
kΩ
mV
Rev. 0 | Page 3 of 20
Test Conditions/Comments
AINL, AINR input pins
Independent of PGA setting
AD1992
Table 5. Power Supplies
Parameter
ANALOG SUPPLY, AVDD
Min
4.5
Typ
5.0
Max
5.5
Unit
V
DIGITAL SUPPLY, DVDD
4.5
5.0
5.5
V
POWER TRANSISTOR SUPPLY, PVDD
6.5
8 to 20
22.5
V
0.6
7.5
19
1
11
40
μA
μA
μA
RESET/POWER-DOWN CURRENT
AVDD
DVDD
PVDD
QUIESCENT CURRENT
AVDD
DVDD
PVDD
OPERATING CURRENT
AVDD
DVDD
PVDD
20
5.5
30
mA
mA
mA
20
5.5
218
27
7
260
mA
mA
mA
Test Conditions/Comments
RESET held low
5V
5V
12 V
Inputs grounded, nonoverlap = minimum
5V
5V
12 V
VIN = 1 V rms, RL = 6 Ω, PO = 1 W
5V
5V
12 V
Table 6. Digital I/O
Parameter
INPUT LOGIC HIGH
INPUT LOGIC LOW
OUTPUT LOGIC HIGH
OUTPUT LOGIC LOW
LEAKAGE CURRENT ON DIGITAL OUTPUTS
Min
2.0
Typ
Max
0.8
2.4
0.4
10
Unit
V
V
V
V
μA
Test Conditions/Comments
@ 4 mA
@ 4 mA
Table 7. Digital Timing
Typ
10
34
Unit
μs
μs
Test Conditions/Comments
Delay after MUTE is asserted until output stops switching
Delay after MUTE is deasserted until output starts switching
tMD
tUD
MUTE
05776-002
Parameter
tMD
tUD
OUTx
Figure 2. Mute and Unmute Delay Timing
Rev. 0 | Page 4 of 20
AD1992
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
AVDD, DVDD to AGND, DGND
PVDDx to PGNDx 1
AGND to DGND to PGNDx
AVDD, to DVDD
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Thermal Resistance
θJA
θJC (at the Exposed Pad Surface)
θJB (on JEDEC Standard PCB)
1
Rating
−0.3 V to +6.5 V
−0.3 V to +30.0 V
−0.3 V to +0.3 V
−0.5 V to +0.5 V
–40°C to +85°C
–65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
19.2°C/W
0.9°C/W
9.7°C/W
Including any induced voltage due to inductive load.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
AD1992
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PGND1
NFL+
NFL–
NC
AINL
NC
MOD_FILT
AVDD
AGND
REF_FILT
NC
AINR
NC
NFR–
NFR+
PGND2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD1992
TOP VIEW
(Not to Scale)
ERR2
ERR1
ERR0
DCTRL2
DCTRL1
DCTRL0
DGND
DVDD
DVDD
DGND
CLKI
CLKO
MUTE
RESET
PGA1
PGA0
NC = NO CONNECT
PIN 1
INDICATOR
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGND2
PGND2
PGND2
OUTR+
OUTR+
OUTR+
PVDD2
PVDD2
PVDD2
PVDD2
OUTR–
OUTR–
OUTR–
PGND2
PGND2
PGND2
05776-003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGND1
PGND1
PGND1
OUTL+
OUTL+
OUTL+
PVDD1
PVDD1
PVDD1
PVDD1
OUTL–
OUTL–
OUTL–
PGND1
PGND1
PGND1
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1, 2, 3, 64
4, 5, 6
7, 8, 9, 10
11, 12, 13
14, 15, 16
17
18
19
20
21
22
23, 26
24, 25
27
28
29
30
31
32
33, 34, 35
36, 37, 38
39, 40, 41, 42
43, 44, 45
46, 47, 48, 49
50
51
Mnemonic
PGND1
OUTL+
PVDD1
OUTL−
PGND1
ERR2
ERR1
ERR0
DCTRL2
DCTRL1
DCTRL0
DGND
DVDD
CLKI
CLKO
MUTE
RESET
PGA1
PGA0
PGND2
OUTR−
PVDD2
OUTR+
PGND2
NFR+
NFR−
In/Out
O
O
O
O
O
I/O
I
I
I
O
I
I
I
I
O
O
I
I
Description
Negative Power Supply. Used for the A2 and B2 high power transistors.
Output of Transistor Pair A1 and A2.
Positive Power Supply. Used for the A1 and B1 high power transistors.
Output of Transistor Pair B1 and B2.
Negative Power Supply. Used for the A2 and B2 high power transistors.
Active Low Thermal Shutdown Error Output.
Active Low Thermal Warning Error Output.
Active Low Overcurrent Error Output.
Nonoverlap Time Setting MSB.
Nonoverlap Time Setting.
Nonoverlap Time Setting LSB.
Negative Power Supply for Low Power Digital Circuitry.
Positive Power Supply for Low Power Digital Circuitry.
Clock Input for 256 × fS Audio Modulator Clock.
Inverted Version of CLKI for Use with an External XTAL Oscillator.
Active Low Mute Input.
Active Low Reset Input.
PGA Gain Control MSB.
PGA Gain Control LSB.
Negative Power Supply for High Power Transistors C2 and D2.
Output of Transistor Pair D1 and D2.
Positive Power Supply for High Power Transistors C1 and D1.
Output of Transistor Pair C1 and C2.
Negative Power Supply for High Power Transistors C2 and D2.
Right Channel Negative Feedback—Noninverting Input.
Right Channel Negative Feedback—Inverting Input.
Rev. 0 | Page 6 of 20
AD1992
Pin No.
52, 54, 59, 61
53
55
56
57
58
60
62
63
Mnemonic
NC
AINR
REF_FILT
AGND
AVDD
MOD_FILT
AINL
NFL−
NFL+
In/Out
I
O
O
O
I
I
Description
No Connection—Should Be Left Floating.
Analog Input for Right Channel.
Filter Pin for Band Gap Reference—Should Be Bypassed to AGND.
Negative Power Supply for Low Power Analog Circuitry.
Positive Power Supply for Low Power Analog Circuitry.
Modulator Filter Pin—Used to Set Time Constant of Modulator Order Reduction Circuit.
Analog Input for Left Channel.
Left Channel Negative Feedback—Inverting Input.
Left Channel Negative Feedback—Noninverting Input.
Rev. 0 | Page 7 of 20
AD1992
0
–20
–20
–40
–60
–80
–100
–120
–140
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
–120
–140
–20
–20
POWER (dBFS: 0dB = Power at Which
THD = 1% (4.0W))
0
–40
–60
–80
–100
–120
–140
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
–80
–100
–120
14
16
18
FREQUENCY (kHz)
20
05776-006
–140
12
16
18
20
–140
0
2
4
6
8
10
12
14
16
18
20
20
FREQUENCY (kHz)
POWER (dBFS: 0dB = Power at Which
THD = 1% (3.0W))
–60
10
14
Figure 8. −60 dBFS Output Power into 6 Ω Load, PVDD = 12 V
–40
8
12
–120
–20
6
10
–100
–20
4
8
–80
0
2
6
–60
0
0
4
–40
–160
Figure 5. 1 W Output Power into 6 Ω Load, PVDD = 12 V
–160
2
Figure 7. −60 dBFS Output Power into 4 Ω Load, PVDD = 12 V
0
–160
0
FREQUENCY (kHz)
05776-005
POWER (dBFS: 0dB = Power at Which
THD = 1% (4.0W))
–100
–160
Figure 4. 1 W Output Power into 4 Ω Load, PVDD = 12 V
POWER (dBFS: 0dB = Power at Which
THD = 1% (3.0W))
–80
05776-008
0
–60
05776-009
–160
–40
05776-007
POWER (dBFS: 0dB = Power at Which
THD = 1% (5.9W))
0
05776-004
POWER (dBFS: 0dB = Power at Which
THD = 1% (5.9W))
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. 1 W Output Power into 8 Ω Load, PVDD = 12 V
–40
–60
–80
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
FREQUENCY (kHz)
Figure 9. −60 dBFS Output Power into 8 Ω Load, PVDD = 12 V
Rev. 0 | Page 8 of 20
AD1992
1
–40
–20
0.1
–60
–70
THD (%)
–40
–60
0.01
–80
–80
–90
–100
0.001
–100
–120
–110
10k
FREQUENCY (Hz)
Figure 10. IMD for 19 kHz/20 kHz Twin-Tone Stimulus with
500 mW Power in Each Tone
0.0001
1k
10k
Figure 13. THD vs. Frequency, 1 W Output Power into 4 Ω Load, PVDD = 12 V
1
PGA GAIN = 18dB
30
PGA GAIN = 12dB
25
PGA GAIN = 6dB
–40
–50
0.1
–60
–70
THD (%)
35
20
PGA GAIN = 0dB
0.01
–80
15
–90
10
0.001
–100
5
–110
1k
10k
FREQUENCY (Hz)
Figure 11. Amplifier Gain vs. Frequency, 6 Ω Load, PVDD = 12 V
0.0001
1k
10k
Figure 14. THD vs. Frequency, 1 W Output Power into 6 Ω Load, PVDD = 12 V
1
–40
0.1
–60
–40
THD (%)
–70
–60
0.01
–80
–90
L CHANNEL IDLE,
R CHANNEL DRIVEN
–80
0.001
–100
–100
–110
1k
10k
FREQUENCY (Hz)
Figure 12. Channel Separation vs. Frequency, Driven Channel Has
1 W Output Power into 6 Ω Load
05776-012
L CHANNEL DRIVEN,
R CHANNEL IDLE
100
THD (dB, Relative to Fundamental)
–50
–20
–120
–120
FREQUENCY (Hz)
0
SIGNAL IN IDLE CHANNEL (dB, Relative to
Driven Channel Signal)
100
05776-014
100
05776-011
0
–120
FREQUENCY (Hz)
40
AMPLIFIER GAIN (dB)
100
05776-013
1k
THD (dB, Relative to Fundamental)
100
05776-010
–140
THD (dB, Relative to Fundamental)
–50
0
0.0001
100
1k
FREQUENCY (Hz)
10k
–120
05776-015
POWER (dB, Relative to 500mW Output Power)
20
Figure 15. THD vs. Frequency, 1 W Output Power into 8 Ω Load, PVDD = 12 V
Rev. 0 | Page 9 of 20
AD1992
20
20
10
18
OUTPUT POWER PER CHANNEL (W)
0
–10
–20
–60
–70
–80
–90
–100
–110
–120
10
8
THD = 1%
6
4
100
200
500
1k
2k
5k
10k
20k
0
8
10
16
18
20
Figure 19. Maximum Output Power vs. PVDD, 4 Ω Load
20
250
P-TYPE 25°C
N-TYPE 25°C
P-TYPE 130°C
N-TYPE 130°C
18
OUTPUT POWER PER CHANNEL (W)
150
100
05776-017
50
0
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
16
14
12
THD = 10%
10
8
6
THD = 1%
4
2
0
8
10
12
14
16
18
20
05776-020
200
20
PVDD VOLTAGE (V)
MOSFET ON-RESISTANCE (mΩ)
Figure 17. Histogram Showing Manufacturing Variation of
RDS-ON of the Output MOSFETS at 25°C and 130°C
Figure 20. Maximum Output Power vs. PVDD, 6 Ω Load
100
20
R = 6Ω
90
18
OUTPUT POWER PER CHANNEL (W)
R = 8Ω
80
70
R = 4Ω
60
50
40
30
20
10
16
14
12
10
8
THD = 10%
6
THD = 1%
4
2
0
2
4
6
8
10
OUTPUT POWER (W)
12
05776-018
EFFICIENCY (%)
14
PVDD VOLTAGE (V)
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Frequency
0
12
05776-019
50
FREQUENCY (Hz)
COUNT
THD = 10%
12
2
05776-016
–130
–140
20
14
05776-021
PSRR (dB)
–30
–40
–50
16
0
8
10
12
14
16
18
PVDD VOLTAGE (V)
Figure 21. Maximum Output Power vs. PVDD, 8 Ω Load
Figure 18. Efficiency vs. Output Power, PVDD = 12 V
Rev. 0 | Page 10 of 20
AD1992
–70
THD + N
–80
0.01
–90
THD
0.001
0.1
1
10
–100
OUTPUT POWER (W)
–40
1
–50
–60
0.1
–70
THD + N
–80
0.01
–90
THD
0.001
0.1
1
10
–100
OUTPUT POWER (W)
THD OR THD + N (%)
–30
–40
1
–50
–60
0.1
–70
THD + N
0.01
–80
THD
–90
0.1
1
OUTPUT POWER (W)
10
–100
0
–20
–30
–40
1
–50
–60
0.1
–70
–80
0.01
–90
THD
0.001
0.1
1
10
–100
OUTPUT POWER (W)
Figure 26. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 15 V
100
0
–10
–20
10
–30
THD OR THD + N (%)
–20
–100
Figure 25. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 15 V
THD + N
THD OR THD + N (dB, Relative to Fundamental)
–10
10
OUTPUT POWER (W)
0
10
1
10
–40
1
–50
–60
0.1
–70
THD + N
–80
0.01
–90
THD
05776-024
100
0.1
–10
Figure 23. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 12 V
0.001
0.001
THD OR THD + N (%)
–30
–90
100
05776-023
THD OR THD + N (%)
10
–80
THD
THD OR THD + N (dB, Relative to Fundamental)
–20
–70
0.01
0
–10
–60
0.1
THD + N
Figure 22. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 12 V
100
–50
Figure 24. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 12 V
THD OR THD + N (dB, Relative to Fundamental)
–60
0.1
–40
1
05776-025
–50
–30
THD OR THD + N (dB, Relative to Fundamental)
1
–20
05776-026
–40
–10
10
0.001
0.1
1
OUTPUT POWER (W)
10
–100
THD OR THD + N (dB, Relative to Fundamental)
THD OR THD + N (%)
–30
0
05776-027
–20
THD OR THD + N (%)
–10
10
100
THD OR THD + N (dB, Relative to Fundamental)
0
05776-022
100
Figure 27. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 15 V
Rev. 0 | Page 11 of 20
AD1992
–70
THD + N
–80
0.01
–90
THD
0.001
0.1
1
10
–100
OUTPUT POWER (W)
–40
1
–50
–60
0.1
–70
THD + N
–80
0.01
–90
THD
0.1
1
10
–100
OUTPUT POWER (W)
–50
–60
0.1
–70
THD + N
–80
0.01
–90
0.001
THD
0.1
1
OUTPUT POWER (W)
10
–100
0
–20
–30
–40
1
–50
–60
0.1
–70
–80
0.01
–90
THD
0.001
0.1
1
10
–100
OUTPUT POWER (W)
Figure 32. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 20 V
100
0
–10
–20
10
–30
THD OR THD + N (%)
–40
1
–100
Figure 31. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 20 V
THD + N
THD OR THD + N (dB, Relative to Fundamental)
THD OR THD + N (%)
–30
10
10
–40
1
–50
–60
0.1
–70
THD + N
–80
0.01
–90
05776-030
–20
10
1
OUTPUT POWER (W)
0
–10
0.1
–10
Figure 29. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 18 V
100
–90
100
05776-029
THD OR THD + N (%)
–30
0.001
0.001
THD OR THD + N (%)
–20
–80
THD
THD OR THD + N (dB, Relative to Fundamental)
–10
–70
THD + N
0
10
–60
0.1
0.01
Figure 28. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 18 V
100
–50
Figure 30. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 18 V
THD OR THD + N (dB, Relative to Fundamental)
–60
0.1
–40
1
05776-033
–50
–30
THD OR THD + N (dB, Relative to Fundamental)
1
–20
05776-034
–40
–10
10
0.001
THD
0.1
1
OUTPUT POWER (W)
10
–100
THD OR THD + N (dB, Relative to Fundamental)
THD OR THD + N (%)
–30
0
05776-035
–20
THD OR THD + N (%)
–10
10
100
THD OR THD + N (dB, Relative to Fundamental)
0
05776-028
100
Figure 33. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 20 V
Rev. 0 | Page 12 of 20
AD1992
THEORY OF OPERATION
OVERVIEW
MUTE AND RESET
The AD1992 is a 2-channel, high performance, switching, audio
power amplifier. Each of the two Σ-Δ modulators converts a
single-ended analog input into a 2-level pulse stream that
controls the differential, full H-bridge, power output stage. The
combination of an Σ-Δ modulator and a switching power stage
provides an inherently linear and efficient means of amplifying
the entire range of audio frequencies. The AD1992 also offers
warning and protection circuits for overcurrent and overtemperature conditions, as well as silent turn-on and turn-off
transitions.
When power is applied and the RESET pin remains asserted,
the AD1992 is in its lowest power consumption mode. The
analog modulator is not running, and the power stage is tristated. On deasserting the RESET pin, the modulator begins a
start-up sequence that includes initialization of the modulator,
the protection circuits, and other functions.
Σ-Δ MODULATOR
The AD1992 is a switching type, also known as a Class-D, audio
power amplifier. This class of amplifiers maximizes efficiency
by only using its power output devices in full-on or full-off
states. While most Class-D amplifiers use some variation of
pulse-width modulation (PWM), the AD1992 uses Σ-Δ
modulation to determine the switching pattern of the output
devices. This provides a number of important benefits. Σ-Δ
modulators do not produce a sharp peak with many harmonics
in the AM frequency band as pulse-width modulators (PWM)
often do. In addition, the 1-bit quantizer produces excellent
linearity across the full amplitude range.
Σ-Δ modulators require feedback to generate an error signal
with respect to the input. The feedback voltages for the AD1992
modulators come from the outputs of the power devices and
before the passive low-pass filters (see Figure 35). This compensates
for nonlinear behavior in the power stage, such as nonoverlap
time, mismatched rise and fall times, and propagation delays. It
also reduces sensitivity to both dc and transient changes of the
power supply voltage.
Σ-Δ modulators operate in discrete time. As with all timequantized systems, the Nyquist frequency is equal to half of
the sampling frequency and input signals above that point
aliases back into the base band. The AD1992 sampling frequency
(master clock) is equal to half the frequency of the input clock,
approximately 6 MHz, so images only alias for input frequencies
above approximately 3 MHz. This is far enough above the audio
band that bandwidth and aliasing are not a problem in real
applications.
The modulator has a noise shaping effect, and SNR is increased
in the audio band by shifting the quantization noise upward in
frequency. For a nominal input clock frequency of 12.288 MHz,
the noise floor rises sharply above 20 kHz. The actual clock
frequency used in an application circuit can deviate from this
rate by as much as ±10%, and the corner frequency of the noise
scales proportionately. The frequency at which the quantization
noise dominates the output determines the amplifier’s practical
bandwidth.
Once the start-up sequence is complete, the amplifier is in a
state in which the modulator is running, but the output stage is
not driven. When MUTE is deasserted, the output is started
using a soft-start sequence that avoids any audible pop or click
noise in the output signal.
The output power transistors do not switch while MUTE
remains asserted. Unlike the analog mute circuits found on
some amplifiers that can be limited in their attenuation by the
control logic or crosstalk, the mute attenuation on the AD1992
is greater than its dynamic range. The noise floor of the output
signal also drops while in MUTE because the output transistors
are not switching.
Power-Up Sequencing
Careful power-up is necessary when using the AD1992 to
ensure correct operation and to avoid possible latch-up issues.
The AD1992 should be powered up with RESET and MUTE
held low until all the power supplies have stabilized. Once the
supplies have stabilized, bring the AD1992 out of RESET by
bringing RESET high.
Begin the soft unmute sequence by bringing MUTE high at
least 1 sec after the RESET rising edge. The amplifier produces
audio using a shorter start-up sequence (as shown in Table 7),
but the amplifier can produce an audible pop or click noise as
the output starts switching. This is because the ac coupling
capacitors at the analog input have a long time constant. If
MUTE is deasserted substantially less than 1 sec after deasserting
RESET, then these capacitors may not have charged to a steady
state. They need ample time to settle at a bias voltage of VREF,
the reference voltage for the single-ended inputs, or the
amplifier starts with a slight dc offset.
GAIN STRUCTURE
Analog Input Levels
The AD1992 has single-ended inputs for the left and right
channels. The analog input section uses an internal amplifier to
bias the input signal to the reference level, VREF, which is nominally
equal to AVDD/2. A dc-blocking capacitor, as shown in Figure 34,
prevents this bias voltage from affecting the signal source. In
combination with the nominal 20 kΩ input impedance, the value
of this capacitor should be large enough to produce a flat
frequency response at the lowest input frequency of interest.
Rev. 0 | Page 13 of 20
AD1992
Note that the amplifier is capable of dc-coupled operation if the
circuit includes some means to account for this bias voltage.
This fixed total resistance to ground eliminates the last free
variable and gives the following equations for the resistors:
R2 = R4 =
+
AINL/
AINR
R1 = R3 = 6000 − R2
05776-038
0V
Note that the gain previously mentioned applies to each side of
the differential output pair. Therefore, the total forward gain for
the modulator and output stage is twice that value. Recommended
resistor values for some common supply voltages are shown
in Table 10.
Figure 34. AC-Coupled Input Signal
Setting the Modulator Gain
The AD1992 modulator uses a combination of the input signal
and feedback from the power output stage to calculate its twostate output pattern. The feedback input nodes are part of the
internal analog circuit that operates from the AVDD (nominal
5 V) power supply. Because the voltage measured at the power
outputs is nominally between 0 V and PVDD, and thus beyond
the 0 V to AVDD range, a voltage divider is required to scale the
feedback to an appropriate level.
Table 10. Recommended Feedback Resistor Values
PVDD (V)
12
15
18
20
PVDD
PVDD
RL
D2
R1
C
D3
L
OUTx–
C
R3
D4
PGND
NFx+
R2
PGND
Table 11. PGA Gain Settings
NFx–
PGA1
0
0
1
1
R4
05776-039
L
Figure 35. H-Bridge Configuration
The resistor values should satisfy the following equation to
maintain modulator stability.
Gain =
R2 (kΩ)
1.82
1.45
1.21
1.09
Voltage
Divider Gain
3.30
4.13
4.95
5.50
Differential
System Gain
6.60 (16.4 dB)
8.25 (18.3 dB)
9.90 (19.9 dB)
11.0 (20.8 dB)
The Σ-Δ modulator itself requires a fixed gain for a given value
of PVDD to maintain optimal stability. This gain can be appropriate,
but many applications require more gain to account for low
source signal levels. The AD1992 includes a programmable gain
amplifier (PGA) to boost the overall amplifier gain. The total gain
for the amplifier is the product of the modulator gain and the
PGA gain. PGA1 (Pin 31) and PGA0 (Pin 32) select one of four
PGA gain values, as shown in Table 11.
EXTERNAL COMPONENTS
D1
R1 (kΩ)
4.18
4.55
4.79
4.91
Programmable Gain Amplifier (PGA)
Resistor voltage dividers should sense the voltage on each side
of the differential output and provide these feedback signals to
the modulator, as shown in Figure 35.
OUTx+
21810
PVDD
PGA0
0
1
0
1
PGA Gain
1 (0 dB)
2 (6 dB)
4 (12 dB)
8 (18 dB)
The AD1992 incorporates a single-ended-to-differential
converter for each channel in the analog front-end section.
The PGA is also part of this analog front-end, and it affects the
analog input signal before it enters the Σ-Δ modulator. The
PGA1 and PGA0 pins are continuously monitored and allow
the gain to be changed at any time.
R1 + R2 R3 + R 4 PVDD
=
=
3.635
R2
R4
Selecting a gain that meets this criterion ensures that the
modulator remains in a stable operating condition.
The ratio of the resistances sets the gain rather than the absolute
values. However, the dividers provide a path from the high
voltage supply to ground; therefore, the values should be large
enough to produce negligible loss due to quiescent current.
The chip contains a calibration circuit to minimize voltage
offsets at the speaker, which helps to minimize clicks and pops
when muting or unmuting. Optimal performance is achieved
for the offset calibration circuit when the feedback divider resistors
sum to 6 kΩ, that is, (R1 + R2) = 6 kΩ, and (R3 + R4) = 6 kΩ.
POWER STAGE
The H-Bridge
The output stage of the AD1992 includes four integrated
MOSFET devices arranged in a full H-bridge, as shown in
Figure 35. The P-Type, high-side transistor of one leg and the
N-Type, low-side transistor of the opposite leg switch on and off
as a pair producing a total voltage swing across the load of
−PVDD to +PVDD. The drive is floating and differential, and it is
important that neither output terminal be shorted to ground.
Rev. 0 | Page 14 of 20
AD1992
The power supply for the output stage of the AD1992, PVDD,
should be in the 8 V to 20 V range and should be capable of
supplying enough current to drive the load. Connect the power
supply across the PVDD and PGND pins. The feedback pins,
NFR+, NFR−, NFL+, and NFL−, supply negative feedback to the
modulator as described in the Setting the Modulator Gain section.
For reactive loads, the impedance can only be below the
recommended threshold over a small portion of the amplifier’s
bandwidth. In these cases, the amplifier can enter overcurrent
shutdown in response to even small input signals in those
frequency bands. When designing a system, use the minimum
load impedance over the entire range of amplified frequencies
when calculating current output rather than the average or
nominal load impedance ratings often cited by loudspeaker
driver manufacturers.
Output Transistor Nonoverlap Time
The AD1992 allows the user to select from one of eight different
nonoverlap times, as shown in Figure 36. Nonoverlap time
prevents or minimizes the period during which both the highside and low-side devices are on simultaneously due to propagation
delays and nonzero rise and fall times. If both the upper and
lower portions of a half-bridge conduct simultaneously, there is a
path directly from the power supply to ground and an induced
current flow known as shoot-through. However, introducing
this delay increases distortion by pushing the switching pattern
further from an ideal two-state waveform. Selecting the
nonoverlap delay requires a compromise between distortion
and efficiency. The logic levels on the three delay control pins,
DCTRL2, DCTRL1, and DCTRL0, set the nonoverlap time
according to Table 12. The state of DCTRL[2:0] is read on the
rising edge of RESET and should not be changed while RESET
is logic high.
Table 12. Nonoverlap Time Settings
DCTRL2
DCTRL1
DCTRL0
Nonoverlap Time (ns)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
62
49
37
24
15
13.5
12
9
CLOCKING
The AD1992 Σ-Δ modulator requires an external clock source
with a nominal frequency of 12.288 MHz. This clock can come
from a crystal or from an existing clock signal in the application
circuit. The discrete time portions of the modulator run internally
at 6.144 MHz, corresponding to 128 × fS, where fS = 48 kHz.
As mentioned in the Σ-Δ Modulator section, the modulator has
a noise-shaping effect such that SNR is increased within the
audio band by shifting modulator quantization noise upward in
frequency. For an external clock frequency of 12.288 MHz, the
modulator’s noise-shaping works in a manner that results in a
flat noise floor at the amplifier output for frequencies 20 kHz
and below. Above 20 kHz, the amplifier noise rises due to the
spectral shaping of the modulator quantization noise. At very high
frequencies, the noise floor levels off and decreases due to poles in
the modulator noise-transfer function and in the external LC filter.
The clock frequency does not have to be exactly equal to
12.288 kHz and can vary by up to ±10%. For other rates, the
noise corner scales linearly with frequency. When the modulator
runs at a rate lower than nominal, the average power stage
switching frequency decreases, the efficiency increases slightly,
and the noise floor begins to rise at a slightly lower frequency.
Likewise, a faster clock gives slightly increased bandwidth and
slightly lower efficiency.
Using a Crystal Oscillator
The AD1992 can use a crystal connected to the CLKI and
CLKO pins as a master clock source, as shown in Figure 37. The
CLKI and CLKO pins connect to an internal inverter to create a
full resonator. The typical values shown work in many applications,
but the crystal manufacturer should provide the exact type and
value of the capacitors and the resistor.
22pF
XTAL
22pF
HIGH-SIDE
GATE DRIVE
Figure 37. Crystal Connection
LOW-SIDE
GATE DRIVE
tNOL
tNOL
Figure 36. Half-Bridge Nonoverlap Delay Timing
Rev. 0 | Page 15 of 20
05776-041
Values are typical and are not production tested.
CLKO
CLKI
47Ω
05776-040
1
1
The shortest setting (DCTRL[2:0] = 111) or the second shortest
setting (DCTRL[2:0] = 111) is recommended for most applications.
These two settings allow a small trade-off between efficiency
and distortion. Longer nonoverlap times generally increase
distortion while providing little or no decrease in shootthrough current.
AD1992
Using an External Clock Source
PROTECTION CIRCUITS AND ERROR REPORTING
If a clock signal of the appropriate frequency already exists in
the application circuit, connect it directly to CLKI and leave
CLKO floating. The logic levels of the square wave should be
compatible with those defined in Specifications section.
Thermal Protection
Large amounts of jitter on the clock input degrade performance.
Whenever possible, avoid passing the clock signal through
programmable logic and other circuits with unknown or variable
propagation delay. In general, clock signals suitable for audio ADCs
or DACs are also appropriate for use with the AD1992.
The AD1992 features thermal protection. When the die
temperature exceeds approximately 135°C, the thermal warning
error output (ERR1) is asserted. If the die temperature exceeds
approximately 150°C, the thermal shutdown error output
(ERR2) is asserted. If this occurs, the part shuts down to
prevent damage to the part. When the die temperature drops
below approximately 120°C, the part returns to normal
operation automatically and negates both error outputs.
Clocking Multiple Amplifiers in Parallel
Overcurrent Protection
If there are multiple AD199x family amplifiers connected to the
same PVDD supply, use the same clock source (or synchronous
derivatives) for each amplifier as previously described. Avoid
clocking amplifiers from similar but asynchronous clocks if
they use the same power supply because this can result in beat
frequencies.
The AD1992 features over current or short-circuit protection. If
the current through any power transistors exceeds approximately
4 A, the part enters a mute state and the overcurrent error
output (ERR0) is asserted. This is a latched error and does not
clear automatically. Restore normal operation and clear the
error condition by either asserting and then negating RESET or
by asserting and then negating MUTE.
Rev. 0 | Page 16 of 20
AD1992
APPLICATION CIRCUITS
DVDD
PVDD
+
0.1µF
+
47µF
AVDD
PVDD
+
0.1µF
0.1µF
1000µF
+
0.1µF
47µF
+
PVDD2
PVDD1
10µF
DVDD
AVDD
1000µF
PVDD
L
AINL
OUTL+
C
R1
NFL+
10µF
+
R2
AINR
R2
NFL–
4.7µF
+
REF_FILT
PVDD
R1
0.1µF
OUTL–
L
AD1992
C
PVDD
L
PGA0
OUTR+
PGA1
NFR+
DCTRL2
DIGITAL
INPUTS
C
R1
R2
DCTRL1
DCTRL0
R2
MUTE
NFR–
RESET
R1
ERR2
ERR1
OVERCURRENT
ERR0
C
R1 = 4.2kΩ
R2 = 1.8kΩ
L = 18µH
C = 1µF
LOAD = 6Ω
PGND2
PGND1
DGND
CLKI
CLKO
L
Figure 38. Typical Application Circuit
Rev. 0 | Page 17 of 20
05776-042
THERMAL WARNING
OUTR–
AGND
THERMAL SHUTDOWN
PVDD
AD1992
OUTLINE DIMENSIONS
9.00
BSC SQ
0.30
0.25
0.18
0.60 MAX
0.60 MAX
64 1
48 49
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
TOP
VIEW
(BOTTOM VIEW)
0.45
0.40
0.35
12° MAX
SEATING
PLANE
33
17 16
32
7.50
REF
0.80 MAX
0.65 TYP
0.25 MIN
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
122105-0
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED PAD
Figure 39. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1992ACPZ 1
AD1992ACPZRL1
AD1992ACPZRL71
EVAL-AD1992EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ), 13” Tape and Reel
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ), 7” Tape and Reel
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 18 of 20
Package Option
CP-64-3
CP-64-3
CP-64-3
AD1992
NOTES
Rev. 0 | Page 19 of 20
AD1992
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05776-0-4/06(0)
Rev. 0 | Page 20 of 20