Freescale Semiconductor Advance Information Document Number: MPC17550 Rev. 2.0, 7/2006 Quad H-Bridge Micromotor Driver with DC/DC Boost Converter 17550 The 17550 is a monolithic quad H-Bridge power IC ideal for portable electronic applications containing tiny bipolar stepper motors and/or brush DC-motors powered by two-to-four cell NiCd/NiMH batteries. The 17550 operates from 2.5 V to 5.5 V, with independent control of each H-Bridge via parallel 3.0 V or 5.0 V logic-compatible I/O. The device features an on-board DC / DC boost converter that allows motor operation all the way down to 1.6 V (the boost converter supplies the gate-drive voltage for each of the four independent H-bridge output stages). Each output bridge has its own gate-drive and logic circuitry with built-in shoot-through current protection. The 17550 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17550 has a low total RDS(ON) of 1.2 Ω max @ 25°C. In addition, it can be set into a very low currentdrain standby mode. The H-Bridge outputs can be independently PWM’ed at up to 200 kHz for speed/torque and current control. The 17550 can efficiently drive many types of micromotors owing to its low output resistance and high output slew rates. Features • Low Total RDS(ON) 0.7 Ω (Typ), 1.2 Ω (Max) @ 25°C • Output Current 700 mA (Continuous per Output) • Shoot-Through Current Protection Circuit • PWM Control Input Frequency up to 200 kHz • Built-In DC / DC Boost Converter • Low Power Consumption Standby Mode • Undervoltage Detection and Shutdown Circuit • Pb-Free Packaging Designated by Suffix Code EV VM H-BRIDGE MOTOR DRIVER EV SUFFIX (Pb-FREE) 98ASA10591D 36-TERMINAL VMFP ORDERING INFORMATION Device Temperature Range (TA) Package MPC17550EV/EL -10°C to 60°C 36 VMFP VDD 17550 VM VDD LX OE PSB MCU VG INAF INAR HBAF HBAR INBF INBR HBBF HBBR INCF INCR HBCF HBCR INDF INDR HBDF HBDR GND Figure 1. 17550 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM GND LX VG VDD VDD VDD AGND DC/DC Converter PSB VDD VG HBA VMA HBAF INAF HBAR INAR PGND HBB INBF VMB INBR HBBF HBBR VDD OE Control Logic Gate Driver and Level Shifter PGND HBC VMC HBCF HBCR INCF PGND INCR HBD VMD INDF HBDF INDR HBDR PGND Figure 2. 17550 Simplified Internal Block Diagram 17550 2 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS AGND NC PSB OE VMA HBAF PGND HBAR VMA VMB HBBR PGND HBBF VMB INAR INAF INBF INBR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VG VDD LX GND VMC HBCF PGND HBCR VMC VMD HBDR PGND HBDF VMD INCR INCF INDF INDR Figure 3. 17550 Terminal Connections Table 1. Terminal Function Description Terminal Terminal Name Formal Name 1 AGND Analog Ground 2 NC No Connect 3 PSB Power Standby Power standby mode control terminal. 4 OE Output Enable Logic output Enable control of H-Bridges (Low = True). 5, 9 VMA 6 HBAF HBA Forward Output Forward output of H-Bridge A. 8 HBAR HBA Reverse Output Reverse output of H-Bridge A. 10, 14 VMB 11 HBBR HBB Reverse Output 7, 12, 25, 30 PGND Power Ground 13 HBBF HBB Forward Output 15 INAR Input Control HBA Reverse 16 INAF Input Control HBA Forward Control signal input for H-Bridge A forward. 17 INBF Input Control HBB Forward Control signal input for H-Bridge B forward. 18 INBR Input Control HBB Reverse Control signal input for H-Bridge B reverse. 19 INDR Input Control HBD Reverse Control signal input for H-Bridge D reverse. 20 INDF Input Control HBD Forward Control signal input for H-Bridge D forward. 21 INCF Input Control HBC Forward Control signal input for H-Bridge C forward. 22 INCR Input Control HBC Reverse 23, 27 VMD Motor Drive Power Supply D Power supply voltage connection for Motor “D” (top of HBD). 24 HBDF HBD Forward Output Forward output of H-Bridge D. 26 HBDR HBD Reverse Output Reverse output of H-Bridge D. 28, 32 VMC Definition Analog and logic signal ground reference terminal. No connection to this terminal. Motor Drive Power Supply A Power supply voltage connection for Motor “A” (top of HBA). Motor Drive Power Supply B Power supply voltage connection for Motor “B” (top of HBB). Reverse output of H-Bridge B. Power ground connection. Forward output of H-Bridge B. Control signal input for H-Bridge A reverse. Control signal input for H-Bridge C reverse. Motor Drive Power Supply C Power supply voltage connection for Motor “C” (top of HBC). 17550 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. Terminal Function Description (continued) Terminal Terminal Name Formal Name 29 HBCR HBC Reverse Output Reverse Output of H-Bridge C. 31 HBCF HCB Forward Output Forward Output of H-Bridge C. 33 GND Ground 34 LX 35 VDD Logic Supply 36 VG Gate-Driver Circuit Power Supply Definition Control circuit ground terminal for DC/DC circuit ground. DC/ DC Converter Switching Open-drain output of the internal DC/ DC converter circuit. Transistor Output Control circuit power supply terminal. Input terminal for the gate-drive voltage. 17550 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CONNECTIONS MAXIMUM RATINGS ELECTRICAL CONNECTIONS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit Motor Supply Voltage VM -0.5 to 9.0 V Gate-Driver Circuit Power Supply Voltage VG VDD - 0.5 to 14 V Logic Supply Voltage VDD -0.5 to 6.0 V VIN -0.5 to VDD + 0.5 V IO 0.7 IOPK 2.0 Signal Input Voltage (1) Driver Output Current Continuous A (2) Peak (3) ESD Voltage (4) V Human Body Model VESD1 ± 2000 Machine Model VESD2 ± 100 TSTG -65 to 150 °C Operating Ambient Temperature TA -10 to 60 °C Operating Junction Temperature TJ -10 to 150 °C RθJA TBD °C/W PD 1500 mW TSOLDER 260 °C Storage Temperature Range Thermal Resistance Power Dissipation (5) (6) Soldering Temperature (7) Notes 1. VIN is the voltage level applied to any input terminal. 2. IO is measured as the load current flowing through the H-bridge. 3. TA = 25°C, pulse width < 10 ms at intervals > 0.2 seconds. 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). Mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB). Maximum at TA = 25°C. 5. 6. 7. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 17550 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CONNECTIONS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 2.5 V, GND = 0 V, fIN = 176 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VM 1.6 2.5 5.5 V VDD 2.5 3.0 5.5 V I V I MSTBY VDDSTBY – – 1.0 – – 1.0 DD – 0.3 1.0 mA Standby (PSB = “L”) IDDC0 – – 1.0 µA No Signal Operating IDDCN – 1.0 3.0 µA Input Signal Operating (10) IDDC – 19 25 mA Driver Output ON Resistance (11) RDS(ON) – 0.7 1.2 Ω VG 10 11.5 13 V VIN 0 – VDD V High-Level Input Voltage VIH VDD x 0.7 – – V Low-Level Input Voltage VIL – – VDD x 0.3 V High-Level Input Current IIH – – 1.0 µA Low-Level Input Current IIL -1.0 – – µA POWER Motor Supply Voltage Logic Supply Voltage Standby Power Supply Current (8) Motor Supply Standby Current Logic Supply Standby Current Logic Supply Current IV µA Gate Driver Circuit Power Supply Current (9) GATE DRIVE Gate Driver Circuit Power Supply Voltage (12) CONTROL LOGIC Logic Input Voltage (13) Logic Input (F, R, PSB, OE) Notes 8. Applies individually to each H-Bridge. 9. Average inductor current for DC/ DC converter (connected between VDD and LX [L = 1.0 mH, C = 2.2 µF]). 10. 11. Full drive (input signal to all input control terminals). The total H-bridge ON resistance when VG is 11.5 V. 12. 13. When voltage is supplied externally without built-in DC/ DC. VIN is the voltage level applied to any input. 17550 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CONNECTIONS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 2.5 V, GND = 0 V, fIN = 176 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit f IN – – 200 kHz f OSC – 100 200 kHz t VGON – 10 20 ms Turn-ON Time t PLH – 0.2 1.0 Turn-OFF Time t PHL – 0.2 1.0 INPUT Pulse Input Frequency (14) Internal Oscillator Frequency OUTPUT Gate Driver Circuit Power Supply Wake-Up Time µs Propagation Delay Time Notes 14. fIN is the signal frequency applied to an input terminal (F, R). 17550 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CONNECTIONS TIMING DIAGRAMS TIMING DIAGRAMS VIH 2.1 V F, R, PSB VIL 10 V 50% FO, RO 50% VG tPLH tPHL tVGON Figure 4. DC/DC Converter Output Waveform Figure 5. H-Bridge Output Waveform Table 5. Truth Table PSB, OE INA / INB / INC / IND HBA / HBB / HBC / HBC PSB OE IN*F IN*R HB*F HB*R H L L L L L H L L H L H H L H L H L H L H H Z Z H H X X Z Z L X X X Z Z H = High. L = Low. Z = High impedance. X = Don’t care. * = A, B, C, or D. 17550 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 17550 is a monolithic quad H-Bridge ideal for portable electronic applications containing multiple bipolar stepper motors and / or brush DC motors. The device features an onboard DC / DC converter to provide gate-drive voltages, as well as level-shifting circuitry. The control logic translates the input signals to the gate-driver circuitry while providing crossconduction suppression. The 17550 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) ≤ 1.2 Ω. The 17550 can simultaneously drive four brush DC motors or two bipolar stepper motors. The drivers are designed to be PWM’ed at frequencies up to 200 kHz. FUNCTIONAL TERMINAL DESCRIPTION LOGIC SUPPLY (VDD) The VDD terminal carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input control terminals. CONTROL SIGNAL INPUT FOR H-BRIDGE, F=FORWARD, R= REVERSE (INAF, INAR, INBF, INBR, INCF, INCR, INDF, INDR) These logic input control terminals control each H-Bridge output; e.g., IN*F logic HIGH = HB*F HIGH; likewise, IN*R logic HIGH = HB*R HIGH. However, if both “F” and “R” inputs are taken HIGH, the associated bridge’s outputs are both tristated (refer to Table 5, Truth Table, page 8). POWER SUPPLY VOLTAGE CONNECTION FOR MOTORS A, B, C, D (VMA, VMB, VMC, VMD) The VM terminals carry the main supply voltage and current into the power sections of the 17550. This supply then becomes controlled and/or modulated by the 17550 as it delivers the power to the loads attached between the H-Bridge output terminals. All VM terminals must be connected together on the printed circuit board. DC/ DC CONVERTER SWITCHING TRANSISTOR OUTPUT (LX) The LX terminal is the open-drain output of the internal DC / DC converter circuit. It is the junction for the external inductor and the anode of the external Schottky diode. GATE-DRIVER CIRCUIT POWER SUPPLY (VG) The VG terminal is the input terminal for the gate-drive voltage. It can be supplied from the built-in DC / DC converter or from an external source. OUTPUT ENABLE (OE) OE terminal is a LOW = TRUE enable input. When OE = HIGH, all H-Bridge outputs are tri-stated (high GROUND TERMINALS (GND, AGND, PGND) All ground terminals must be tied together on the PCB. impedance) regardless of logic inputs states. POWER STANDBY MODE CONTROL (PSB) OUTPUT OF H-BRIDGE, R=REVERSE, F=FORWARD (HBAF, HBAR, HBBF, HBBR, HBCF, HBCR, HBDF, HBDR) These terminals provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17550 Simplified Internal Block Diagram, page 2). The PSB input controls the functioning of power output stages (the H-Bridges). When this input signal turns Low, the output stages and Internal DC/DC Converter which makes Gate Voltage are disabled and all the outputs are opened (High Impedance). When this input signal turns High, the output stages and Internal DC/DC Converter are enabled and the H-Bridges operate normally. 17550 Analog Integrated Circuit Device Data Freescale Semiconductor 9 TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION The 17550's built-in DC / DC converter must be connected to an external inductor, rectifier, and filter capacitor. This step-up converter generates the gate-drive voltage, VG, required by the internal gate driver circuits. Although there is some latitude in selecting the values for the external component, care must be taken that VG does not exceed 14 V. Additionally, too low an inductance will cause large instantaneous switching currents, which may damage the device. Important Do not use an inductance lower than 330 µH. To attain high-efficiency operation, the rectifier should be a Schottky diode, and the filter capacitor should be of the low VM = 2.5 V 47 µF Equivalent Series Resistance (ESR) type. Attention should be paid to proper switch mode power supply PCB layout practice. Some experimentation may be required to determine optimal external component values. The recommended starting values are L = 1.0 mH, C = 2.2 µF. The DC / DC converter includes its own internal oscillator and does not require an external clock input. TYPICAL APPLICATION Two typical application schematics are shown in Figure 6. and Figure 7. VDD = 3.0 V 17550 VM VDD 10 µF L = 1.0 mH LX OE PSB VG 2.2 µF INAF INAR HBAF HBAR N S MCU INBF HBBF INBR HBBR INCF HBCF INCR HBCR N S HBDF INDF INDR HBDR GND Figure 6. Typical 17550 Application - Controlling Stepper Motors 17550 10 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS INTRODUCTION VDD = 3.0 V VM = 2.5 V 47 µF 17550 VM VDD LX OE VG 11.5V PSB VG INAF INAR HBAF HBAR N S MCU INBF HBBF INBR HBBR INCF HBCF INCR HBCR N S HBDF INDF INDR HBDR GND Figure 7. Typical 17550 Application - No Internal DC-DC Used 17550 Analog Integrated Circuit Device Data Freescale Semiconductor 11 TYPICAL APPLICATIONS INTRODUCTION CEMF SNUBBING TECHNIQUES Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commuting currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the motor supply voltage terminal (VM) (see Figure 8). 5.0 V 5.0 V 175XX VDD VM 5.0 V 5.0 V 175XX VDD VM C1L C1L C1H C1H C2L C2H OUT C2L C2H OUT CRES CRES OUT GND OUT GND Figure 8. CEMF Snubbing Techniques 17550 12 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A number listed below. 1.90 1.70 1.20±0.10 5 36 19 B 1.35±0.10 NPJ IA 5.40 5.20 (JPN)/CAVITY #(A1) BOTTOM SIDE 3 4 1.20±0.10 4X R0.40±0.10 18 1 1.30±0.10 VIEW Y 12.70 12.50 3 VIEW K 4 A 12˚±1˚ 2X R0.15±0.10 12˚±1˚ 36X 0.10 C 0.25 1.90 1.70 GUAGE PLANE SEATING PLANE 14˚±1˚ 2X R0.15±0.10 0.20 0.00 C 0.27 36X 0.37 0.13 M 14˚±1˚ 0˚- 8˚ 0.60±0.20 C A B 0.69±0.20 4 0.37 0.27 0.13 M R VIEW K VIEW ROTATED 90˚ CW C A B R BASE METAL 0.325 0.27 (0.20) 0.15 34X 0.65 VIEW Y PLATING (0.30) NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.5 MM PER END. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.5 MM PER SIDE. 4. DIMENSIONS ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERNCE ONLY. SECTION R-R CASE 1522-01 ISSUE O EV (Pb-FREE) SUFFIX 36-LEAD VMFP PLASTIC PACKAGE CASE 1522-01 ISSUE O DATE 10/01/03 17550 Analog Integrated Circuit Device Data Freescale Semiconductor 13 REVISION HISTORY REVISION HISTORY REVISION 2.0 DATE 7/2006 DESCRIPTION OF CHANGES • Converted to Freescale format and updated to the prevailing form and style • Added typical Application for non DC/DC use • Added RoHS compliance 17550 14 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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