Final Electrical Specifications LTC4006 4A, High Efficiency, Standalone Li-Ion Battery Charger May 2003 U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Complete Charger Controller for 2-, 3- or 4-Cell Lithium-Ion Batteries High Conversion Efficiency: Up to 96% Output Currents Exceeding 4A ±0.8% Accurate Preset Voltages: 8.4V, 12.6V, 16.8V Built-In Charge Termination with Automatic Restart AC Adapter Current Limiting Maximizes Charge Rate* Automatic Conditioning of Deeply Discharged Batteries Thermistor Input for Temperature Qualified Charging Wide Input Voltage Range: 6V to 28V 0.5V Dropout Voltage; Maximum Duty Cycle: 98% Programmable Charge Current: ±5% Accuracy Indicator Outputs for Charging, C/10 Current Detection and AC Adapter Present Charging Current Monitor Output 16-Pin Narrow SSOP Package U APPLICATIO S ■ ■ ■ ■ Notebook Computers Portable Instruments Battery-Backup Systems Standalone Li-Ion Chargers The LTC®4006 is a complete constant-current/constantvoltage charger controller for 2-, 3- or 4-cell lithium batteries in a small package using few external components. The PWM controller is a synchronous, quasi-constant frequency, constant off-time architecture that will not generate audible noise even when using ceramic capacitors. The LTC4006 is available in 8.4V, 12.6V and 16.8V versions with ±0.8% accuracy. Charging current is programmable with a single sense resistor to ±4% typical accuracy. Charging current can be monitored as a representative voltage at the IMON pin. A timer, programmed by an external resistor, sets the total charge time or is reset to 25% of total charge time after C/10 charging current is reached. Charging automatically resumes when cell voltage falls below 3.9V/cell. Fully discharged cells are automatically trickle charged at 10% of the programmed current until the cell voltage exceeds 2.5V/cell. Charging terminates if the low-battery condition persists for more than 25% of the total charge time. LTC4006 includes a thermistor sensor input that suspends charging if an unsafe temperature condition is detected and automatically resumes charging when battery temperature returns to within safe limits. , LTC and LT are registered trademarks of Linear Technology Corporation. *U.S. Patent No. 5,723,970 U TYPICAL APPLICATIO 4A Li-Ion Battery Charger DCIN 0V TO 28V 3A INPUT SWITCH 0.1µF 5k VLOGIC DCIN 100k CHG CHG INFET LTC4006 CLP ACP/SHDN ACP CHARGING CURRENT MONITOR 32.4k 0.0047µF THERMISTOR 10k NTC 0.47µF 309k TIMING RESISTOR (~2 HOURS) 6k CLN IMON TGATE NTC BGATE RT PGND ITH CSP GND BAT 15nF 0.033Ω 20µF 10µH 0.12µF 0.025Ω BATTERY 20µF 4006 TA01 sn4006 4006is Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LTC4006 U U W W W Voltage from DCIN, CLP, CLN, TGATE, INFET, ACP/SHDN, CHG to GND ........................... + 32V/– 0.3V CSP, BAT to GND ....................................... +28V/– 0.3V RT to GND ..................................................... +7V/– 0.3V NTC ............................................................ +10V/– 0.3V Operating Ambient Temperature Range (Note 4) ............................................. – 40°C to 85°C Operating Junction Temperature ......... – 40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C W (Note 1) U ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION TOP VIEW DCIN 1 16 INFET CHG 2 15 BGATE ACP/SHDN 3 14 PGND RT 4 13 TGATE GND 5 12 CLN NTC 6 11 CLP ITH 7 10 BAT IMON 8 9 ORDER PART NUMBER LTC4006EGN-2 LTC4006EGN-4 LTC4006EGN-6 GN PART MARKING CSP 40062 40064 40066 GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN DCIN Operating Range 6 IDCIN DCIN Operating Current Sum of Current from CLP, CLN, DCIN VTOL Voltage Accuracy (Note 2) LTC4006-6 LTC4006-6 LTC4006-2 LTC4006-2 LTC4006-4 LTC4006-4 ITOL TTOL Current Accuracy (Note 3) TYP MAX UNITS 28 V 3 5 mA 8.4 8.4 12.6 12.6 16.8 16.8 8.467 8.484 12.700 12.726 16.935 16.968 V V V V V V ● 8.333 8.316 12.499 12.474 16.665 16.632 ● –4 –5 4 5 % % VBAT < 6V, VCSP – VBAT Target = 10mV – 60 60 % 6V ≤ VBAT ≤ VLOBAT, VCSP – VBAT Target = 10mV – 40 40 % –15 15 % 30 45 10 µA µA 5.5 V 2.5 V VCSP – VBAT Target = 100mV VBAT = 11.5V (LTC4006-2) VBAT = 7.6V (LTC4006-6) VBAT = 12V (LTC4006-4) ● ● Termination Timer Accuracy RRT = 270k ● Battery Leakage Current DCIN = 0V DCIN = 0V DCIN = 20V, VSHDN = 0V ● ● –10 15 20 0 DCIN Rising, VBAT = 0V ● 4.2 4.7 ● 1 Shutdown UVLO Undervoltage Lockout Threshold Shutdown Threshold at ACP/SHDN DCIN Current in Shutdown VSHDN = 0V, Sum of Current from CLP, CLN, DCIN 2 3 mA Current Sense Amplifier, CA1 Input Bias Current Into BAT Pin µA 11.67 CMSL CA1/I1 Input Common Mode Low ● CMSH CA1/I1 Input Common Mode High ● 0 V VCLN – 0.2 V sn4006 4006is 2 LTC4006 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 140 165 200 mV Current Comparators ICMP and IREV ITMAX Maximum Current Sense Threshold (VCSP – VBAT) ITREV Reverse Current Threshold (VCSP – VBAT) VITH = 2.5V ● – 30 mV Current Sense Amplifier, CA2 Transconductance 1 mmho Source Current Measured at ITH, VITH = 1.4V – 40 µA Sink Current Measured at ITH, VITH = 1.4V 40 µA 1.5 mmho Current Limit Amplifier Transconductance VCLP Current Limit Threshold ICLP CLP Input Bias Current ● 93 100 107 mV 100 nA Voltage Error Amplifier, EA Transconductance Sink Current OVSD Measured at ITH, VITH = 1.4V Overvoltage Shutdown Threshold as a Percent of Programmed Charger Voltage 1 mmho 36 µA ● 102 107 110 % ● 0 0.17 0.25 V 25 50 Input P-Channel FET Driver (INFET) DCIN Detection Threshold (VDCIN – VCLN) DCIN Voltage Ramping Up from VCLN – 0.1V Forward Regulation Voltage (VDCIN – VCLN) ● Reverse Voltage Turn-Off Voltage (VDCIN – VCLN) DCIN Voltage Ramping Down ● – 60 – 25 INFET “On” Clamping Voltage (VDCIN – VINFET) IINFET = 1µA ● 5 5.8 INFET “Off” Clamping Voltage (VDCIN – VINFET) IINFET = – 25µA mV mV 6.5 V 0.25 V Thermistor NTCVR Reference Voltage During Sample Time 4.5 V High Threshold VNTC Rising ● NTCVR • 0.48 NTCVR • 0.5 NTCVR • 0.52 V Low Threshold VNTC Falling ● NTCVR • 0.115 NTCVR • 0.125 NTCVR • 0.135 V Thermistor Disable Current VNTC ≤ 10V 10 µA Indicator Outputs (ACP/SHDN, CHG) C10TOL C/10 Indicator Accuracy Voltage Falling at PROG ● 0.375 0.400 0.425 V LBTOL LOBAT Threshold Accuracy LTC4006-6 LTC4006-2 LTC4006-4 ● ● ● 4.70 7.27 9.70 4.93 7.5 10 5.14 7.71 10.28 V V V RESTART Threshold Accuracy LTC4006-6 LTC4006-2 LTC4006-4 ● ● ● 7.5 11.35 15.15 7.7 11.7 15.6 7.96 11.94 15.92 V V V VOL Low Logic Level of ACP/SHDN, CHG IOL = 100µA ● 0.5 V VOH High Logic Level of ACP/SHDN IOH = –1µA ● 2.7 IPO Pull-Up Current on ACP/SHDN V = 0V IC10 C/10 Indicator Sink Current from CHG VOH = 3V ● 15 IOFF Off State Leakage Current of CHG VOH = 3V Timer Defeat Threshold at CHG V µA –10 –1 1 25 38 µA 1 µA V sn4006 4006is 3 LTC4006 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 255 300 345 kHz Oscillator fOSC Regulator Switching Frequency fMIN Regulator Switching Frequency in Drop Out Duty Cycle ≥ 98% 20 25 kHz DCMAX Regulator Maximum Duty Cycle VCSP = VBAT 98 99 % Gate Drivers (TGATE, BGATE) VTGATE High (VCLN – VTGATE) ITGATE = –1mA 50 mV VBGATE High CLOAD = 3000pF 4.5 VTGATE Low (VCLN – VTGATE) CLOAD = 3000pF 4.5 5.6 10 V 5.6 10 V VBGATE Low IBGATE = 1mA 50 mV TGTR TGTF TGATE Transition Time TGATE Rise Time TGATE Fall Time CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% 50 50 110 100 ns ns BGTR BGTF BGATE Transition Time BGATE Rise Time BGATE Fall Time CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% 40 40 90 80 ns ns VTGATE at Shutdown (VCLN – VTGATE) ITGATE = –1µA, DCIN = 0V, CLN = 12V 100 mV VBGATE at Shutdown IBGATE = 1µA, DCIN = 0V, CLN = 12V 100 mV Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: See Test Circuit Note 3: Does not include tolerance of current sense resistor. Note 4: The LTC4006E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. U U U PI FU CTIO S DCIN (Pin 1): External DC Power Source Input. Bypass this pin with at least 0.01µF. See Applications Information section. CHG (Pin 2): Open-Drain Charge Status Output. When the battery is being charged, the CHG pin is pulled low by an internal N-channel MOSFET. When the charge current drops below 10% of programmed current, the N-channel MOSFET turns off and a 25µA current source is connected from the CHG pin to GND. When the timer runs out or the input supply is removed, the current source will be disconnected and the CHG pin is forced into a high impedance state. A pull-up resistor is required. The timer function is defeated by forcing this pin below 1V (or connecting it to GND). ACP/SHDN (Pin 3): Open-Drain Output Used to Indicate if the AC Adapter Voltage is Adequate for Charging. Active high digital output. Internal 10µA pull-up to 3.5V. The charger can also be inhibited by pulling this pin below 1V. Reset the charger by pulsing the pin low for a minimum of 0.1µs. RT (Pin 4): Timer Resistor. The timer period is set by placing a resistor, RRT , to GND. The timer period is tTIMER = (1hour • RRT/154k) If this resistor is not present, the charger will not start. GND (Pin 5): Ground for Low Power Circuitry. sn4006 4006is 4 LTC4006 U U U PI FU CTIO S NTC (Pin 6): A thermistor network is connected from NTC to GND. This pin determines if the battery temperature is safe for charging. The charger and timer are suspended if the thermistor indicates a temperature that is unsafe for charging. The thermistor function may be disabled with a 300k to 500k resistor from DCIN to NTC. ITH (Pin 7): Control Signal of the Inner Loop of the Current Mode PWM. Higher ITH voltage corresponds to higher charging current in normal operation. A 6.04k resistor, in series with a capacitor of at least 0.1µF to GND, provides loop compensation. Typical full-scale output current is 40µA. Nominal voltage range for this pin is 0V to 3V. IMON (Pin 8): Current Monitoring Output. The voltage at this pin provides a linear indication of charging current. Peak current is equivalent to 1.19V. Zero current is approximately 0.309V. A capacitor from IMON to ground is required to filter higher frequency components. If VBAT < 2.5V/cell, then IMON = 1.19V when conditioning a depleted battery. CSP (Pin 9): Current Amplifier CA1 Input. This pin and the BAT pin measure the voltage across the sense resistor, RSENSE, to provide the instantaneous current signals required for both peak and average current mode operation. BAT (Pin 10): Battery Sense Input and the Negative Reference for the Current Sense Resistor. A precision internal resistor divider sets the final float potential on this pin. The resistor divider is disconnected during shutdown. CLP (Pin 11): Positive Input to the Supply Current Limiting Amplifier, CL1. The threshold is set at 100mV above the voltage at the CLN pin. When used to limit supply current, a filter is needed to filter out the switching noise. If no current limit function is desired, connect this pin to CLN. CLN (Pin 12): Negative Reference for the Input Current Limit Amplifier, CL1. This pin also serves as the power supply for the IC. A 10µF to 22µF bypass capacitor should be connected as close as possible to this pin. TGATE (Pin 13): Drives the top external P-channel MOSFET of the battery charger buck converter. PGND (Pin 14): High Current Ground Return for the BGATE Driver. BGATE (Pin 15): Drives the bottom external N-channel MOSFET of the battery charger buck converter. INFET (Pin 16): Drives the Gate of the External Input PFET. TEST CIRCUIT LTC4006 11.67µA + VREF – + EA 3k 35mV – 10 BAT 7 ITH + LT1055 – 0.6V 4006 TC sn4006 4006is 5 LTC4006 W BLOCK DIAGRA VIN DCIN 25µA 1 0.01µF INFET Q3 2 CHG 100k VLOGIC 5.8V 16 CLN ACP/SHDN 3 TIMER/CONTROLLER OSCILLATOR 4 THERMISTOR 6 RRT RT ICL TBAD RESTART 32.4k NTC 1.105V 10k NTC 0.47µF LOBAT 397mV C/10 35mV 708mV – 5 3k + GND 11.67µA 10 BAT RSENSE 9 gm = 1m – + 1.19V Ω 15nF CLN – 11 – Ω 9k CL1 100mV 12 gm = 1.5m + RCL CLP 3k CA1 EA 5.1k 20µF CSP + gm = 1m Ω – CA2 + DCIN OSCILLATOR WATCH DOG DETECT tOFF 7 OV 1.28V TGATE 13 Q S R Q2 BGATE PGND 15 PWM LOGIC CHARGE ICMP ITH 6.04k BUFFERED ITH 0.12µF –+ – Q1 ÷5 + 20µF 1.19V 14 IREV – 17mV L1 IMON + 8 RIMON1 26.44k 4.7nF RIMON2 52.87k 4006 BD U OPERATIO Overview The LTC4006 is a synchronous current mode PWM stepdown (buck) switcher battery charger controller. The charge current is programmed by the sense resistor (RSENSE) between the CSP and BAT pins. The final float voltage is internally programmed to 8.4V (LTC4006-6), 12.6V (LTC4006-2) or 16.8V (LTC4006-4) with better than ±0.8% accuracy. Charging begins when the potential at the DCIN pin rises above the voltage at CLN (and the UVLO voltage) and the ACP/SHDN pin is allowed to go high; the CHG pin is set low. At the beginning of the charge cycle, if the cell voltage is below 2.5V, the charger will trickle charge the battery with 10% of the maximum programmed current. sn4006 4006is 6 LTC4006 U OPERATIO If the cell voltage stays below 2.5V for 25% of the total charge time, the charge sequence will be terminated immediately and the CHG pin will be set to a high impedance. An external thermistor network is sampled at regular intervals. If the thermistor value exceeds design limits, charging is suspended. If the thermistor value returns to an acceptable value, charging resumes. An external resistor on the RT pin sets the total charge time. The timer can be defeated by forcing the CHG pin to a low voltage. As the battery approaches the final float voltage, the charge current will begin to decrease. When the current drops to 10% of the programmed charge current, an internal C/10 comparator will indicate this condition by sinking 25µA at the CHG pin. The charge timer is also reset to 25% of the total charge time. If this condition is caused by an input current limit condition, described below, then the C/10 comparator will be inhibited. When a time-out occurs, charging is terminated immediately and the CHG pin changes to a high impedance. The charger will automatically restart if the cell voltage is less than 3.9V. To restart the charge cycle manually, simply remove the input voltage and reapply it, or force the ACP/SHDN pin low momentarily. When the input voltage is not present, the charger goes into a sleep mode, dropping battery current drain to 15µA. This greatly reduces the current drain on the battery and increases the standby time. The charger can be inhibited at any time by forcing the ACP/SHDN pin to a low voltage. Input FET DCIN and CLN is ever less than – 25mV, then the input FET is turned off in less than 10µs to prevent significant reverse current from flowing in the input FET. In this condition, the ACP/SHDN pin is driven low and the charger is disabled. Battery Charger Controller The LTC4006 charger controller uses a constant off-time, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the SR latch and turned off when the main current comparator ICMP resets the SR latch. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current trips the current comparator IREV or the beginning of the next cycle. The oscillator uses the equation: tOFF = VDCIN – VBAT VDCIN • fOSC to set the bottom MOSFET on time. This activity is diagrammed in Figure 1. OFF TGATE ON ON tOFF BGATE OFF TRIP POINT SET BY ITH VOLTAGE INDUCTOR CURRENT 4006 F01 The input FET circuit performs two functions. It enables the charger if the input voltage is higher than the CLN pin and provides the logic indicator of AC present on the ACP/SHDN pin. It controls the gate of the input FET to keep a low forward voltage drop when charging and also prevents reverse current flow through the input FET. If the input voltage is less than VCLN, it must go at least 170mV higher than VCLN to activate the charger. When this occurs the ACP/SHDN pin is released and pulled up with an internal load to indicate that the adapter is present. The gate of the input FET is driven to a voltage sufficient to keep a low forward voltage drop from drain to source. If the voltage between DCIN and CLN drops to less than 25mV, the input FET is turned off slowly. If the voltage between Figure 1 The peak inductor current, at which ICMP resets the SR latch, is controlled by the voltage on ITH. ITH is in turn controlled by several loops, depending upon the situation at hand. The average current control loop converts the voltage between CSP and BAT to a representative current. Error amp CA2 compares this current against the desired current programmed by RIMON at the IMON pin and adjusts ITH until: VREF V –V + 11.67µA • 3kΩ = CSP BAT RIMON 3kΩ sn4006 4006is 7 LTC4006 U OPERATIO Table 1. Truth Table for LTC4006 Operation MODE DCIN BAT VOLTAGE BAT CURRENT ACP/SHDN TIMER STATE CHG* Shut Down by Low Adapter Voltage Conditioning a Depleted Battery <BAT >BAT >UVLO <2.5V/Cell LOW HIGH Reset Running HIGH LOW Normal Charging >BAT >2.5V/Cell HIGH Running LOW Input Current Limited Charging Charger Paused Due to Thermistor Out of Range >BAT >BAT >2.5V/Cell X Leakage 10% Programmed Current Programmed Current Unknown OFF HIGH HIGH Running Paused Shut Down by ACP/SHDN Pin Terminated by Low-Battery Fault (Note 1) >BAT >BAT X <2.5V/Cell OFF OFF Forced LOW HIGH Reset >T/4 Stopped Top-Off Charging. C/10 is Latched >BAT VFLOAT OFF HIGH Timer is Reset by C/10 Comparator (Latched), then Terminates After 1/4 T >BAT VFLOAT OFF HIGH Terminated by Expired Timer >BAT VFLOAT** OFF HIGH <T/4 After C/10 Comparator Trip. Running >T/4 After C/10 Comparator Trip. Stopped >T Stopped LOW LOW (Faulted) HIGH HIGH (Faulted) 25µA X X X X X HIGH (Waiting for Restart) HIGH (Waiting for Restart) Forced LOW >BAT and <UVL >BAT <UVL OFF HIGH Reset HIGH** 2.5V ≤ VBAT ≤3.9V (V/Cell) Programmed Current HIGH Running LOW Timer Defeated. (Low-Battery Conditioning Still Functional) Shut Down by Undervoltage Lockout Timer Defeated Until VBAT > 3.9V/Cell *Open Drain. High when used with pull-up resistor. **Most probable condition, X = Don’t care Note 1: If a depleted battery is inserted while the charger is in this state, the charger must be reset to initiate charging. therefore, will be inhibited if it is not already active. If the charging current decreases below 10% to 15% of programmed current, while engaged in input current limiting, BGATE will be forced low to prevent the charger from discharging the battery. Audible noise can occur in this mode of operation. V 3kΩ ICHARGE = REF – 11.67µA • RIMON RSENSE The voltage at BAT is divided down by an internal resistor divider and is used by error amp EA to decrease ITH if the divider voltage is above the 1.19V reference. When the charging current begins to decrease, the voltage at IMON will decrease in direct proportion. The voltage at IMON is then given by: VIMON = (ICHARGE • RSENSE + 11.67µA • 3kΩ) • RIMON 3kΩ VIMON is plotted in Figure 2. The amplifier CL1 monitors and limits the input current to a preset level (100mV/RCL). At input current limit, CL1 will decrease the ITH voltage, thereby reducing charging current. When this condition is detected, the C/10 indicator An overvoltage comparator guards against voltage transient overshoots (>7% of programmed value). In this case, both MOSFETs are turned off until the overvoltage condition is cleared. This feature is useful for batteries which “load dump” themselves by opening their protection switch to perform functions such as calibration or pulse mode charging. As the voltage at BAT increases to near the input voltage at DCIN, the converter will attempt to turn on the top MOSFET continuously (“dropout’’). A watchdog timer detects this condition and forces the top MOSFET to turn sn4006 4006is 8 LTC4006 U OPERATIO 1.2 LTC4006 1.19V CLK 1.0 R9 32.4k VPROG (V) 0.8 – 6 RTH 10k NTC 0.6 C7 0.47µF NTC S1 + ~4.5V 0.4 60k + 0.309V 0.2 – 0 0 20 40 60 80 ICHARGE (% OF MAXIMUM CURRENT) 100 – 4006 F02 45k Figure 2. IMON vs ICHARGE + 15k off for about 300ns at 40µs intervals. This is done to prevent audible noise when using ceramic capacitors at the input and output. D TBAD Q C 4006 F03 Charger Startup When the charger is enabled, it will not begin switching until the ITH voltage exceeds a threshold that assures initial current will be positive. This threshold is 5% to 15% of the maximum programmed current. After the charger begins switching, the various loops will control the current at a level that is higher or lower than the initial current. The duration of this transient condition depends upon the loop compensation but is typically less than 100µs. Thermistor Detection The thermistor detection circuit is shown in Figure 3. It requires an external resistor and capacitor in order to function properly. The thermistor detector performs a sample-and-hold function. An internal clock, whose frequency is determined by the timing resistor connected to RT, keeps switch S1 closed to sample the thermistor: tSAMPLE = 127.5 • 20 • RRT • 17.5pF = 13.8ms, Figure 3 This voltage is stored by C7. Then the switch is opened for a short period of time to read the voltage across the thermistor. tHOLD = 10 • RRT • 17.5pF = 54µs, for RRT = 309k When the tHOLD interval ends the result of the thermistor testing is stored in the D flip-flop (DFF). If the voltage at NTC is within the limits provided by the resistor divider feeding the comparators, then the NOR gate output will be low and the DFF will set TBAD to zero and charging will continue. If the voltage at NTC is outside of the resistor divider limits, then the DFF will set TBAD to one, the charger will be shut down, and the timer will be suspended until TBAD returns to zero (see Figure 4). CLK (NOT TO SCALE) for RRT = 309k tHOLD The external RC network is driven to approximately 4.5V and settles to a final value across the thermistor of: VRTH(FINAL) = 4.5V • RTH RTH + R9 VOLTAGE ACROSS THERMISTOR tSAMPLE COMPARATOR HIGH LIMIT VNTC COMPARATOR LOW LIMIT 4006 F04 Figure 4 sn4006 4006is 9 LTC4006 U W U U APPLICATIO S I FOR ATIO Alternatively, a normally closed switch can be used to detect when the battery is present (see Figure 8). Charger Current Programming The basic formula for charging current is: 200 180 160 Table 2. Recommended RSENSE Resistor Values tTIMER (MINUTES) ICHARGE(MAX) 100mV = RSENSE 140 120 IMAX (A) RSENSE (Ω) 1% RSENSE (W) 1.0 0.100 0.25 2.0 0.050 0.25 3.0 0.033 0.5 40 4.0 0.025 0.5 20 Setting the Timer Resistor 100 80 60 0 100 150 200 250 300 350 400 450 500 RRT (kΩ) 4006 F05 The charger termination timer is designed for a range of 1hour to 3 hour with a ±15% uncertainty. The timer is programmed by the resistor RRT using the following equation: tTIMER = 227 • RRT • 175pF (Refer to Figure 5) Figure 5. tTIMER vs RRT 3.3V LTC4006 33k It is important to keep the parasitic capacitance on the RT pin to a minimum. The trace connecting RT to RRT should be as short as possible. CHG Status Output Pin When the charge cycle starts, the CHG pin is pulled down to ground by an internal N-channel MOSFET that can drive more than 100µA. When the charge current drops to 10% of the full-scale current (C/10), the N-channel MOSFET is turned off and a weak 25µA current source to ground is connected to the CHG pin. After a time out occurs, the pin will go into a high impedance state. By using two different value pull-up resistors, a microprocessor can detect three states from this pin (charging, C/10 and stop charging). See Figure 6. Battery Detection It is generally not good practice to connect a battery while the charger is running. The timer is in an unknown state and the charger could provide a large surge current into the battery for a brief time. The circuit shown in Figure 7 keeps the charger shut down and the timer reset while a battery is not connected. 200k CHG VDD µP OUT IN 4006 F06 Figure 6. Microprocessor Interface LTC4006 ADAPTER POWER DCIN 470k ACP/SHDN 4006 F07 SWITCH CLOSED IF BATTERY CONNECTED Figure 7 LTC4006 ADAPTER POWER DCIN ACP/SHDN 4006 F08 SWITCH OPEN WHEN BATTERY CONNECTED Figure 8 sn4006 4006is 10 LTC4006 U W U U APPLICATIO S I FOR ATIO Soft-Start The LTC4006 is soft started by the 0.12µF capacitor on the ITH pin. On start-up, ITH pin voltage will rise quickly to 0.5V, then ramp up at a rate set by the internal 40µA pull-up current and the external capacitor. Battery charging current starts ramping up when ITH voltage reaches 0.8V and full current is achieved with ITH at 2V. With a 0.12µF capacitor, time to reach full charge current is about 2ms and it is assumed that input voltage to the charger will reach full value in less than 2ms. The capacitor can be increased up to 1µF if longer input start-up times are needed. Input and Output Capacitors The input capacitor (C2) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current. Actual capacitance value is not critical. Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass. High input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. Only Kemet T495 series of “Surge Robust” low ESR tantalums are rated for high surge conditions such as battery to ground. The relatively high ESR of an aluminum electrolytic for C1, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Refer to Application Note 88 for more information. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20µF) from Tokin, United Chemi-Con/Marcon, et al. Other alternative capacitors include OS-CON capacitors from Sanyo. The output capacitor (C3) is also assumed to absorb output switching current ripple. The general formula for capacitor current is: IRMS V 0.29(VBAT ) 1 – BAT VDCIN = (L1)( f) For example: VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and f = 300kHz, IRMS = 0.41A. EMI considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2Ω and the battery impedance is raised to 4Ω with a bead or inductor, only 5% of the current ripple will flow in the battery. Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition, the effect of inductor value on ripple current and low current operation must also be considered. The inductor ripple current ∆IL decreases with higher frequency and increases with higher VIN. ∆IL = V 1 VOUT 1– OUT ( f)(L) VIN Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.4(IMAX). In no case should ∆IL exceed 0.6(IMAX) due to limits imposed by IREV and CA1. Remember the maximum ∆IL occurs at the maximum input voltage. In practice 10µH is the lowest value recommended for use. Lower charger currents generally call for larger inductor values. Use Table 3 as a guide for selecting the correct inductor value for your application. sn4006 4006is 11 LTC4006 U W U U APPLICATIO S I FOR ATIO Table 3 MAXIMUM AVERAGE CURRENT (A) INPUT VOLTAGE (V) MINIMUM INDUCTOR VALUE (µH) 1 ≤ 20 40 ±20% 1 > 20 56 ±20% 2 ≤ 20 20 ±20% 2 > 20 30 ±20% 3 ≤ 20 15 ±20% 3 > 20 20 ±20% 4 ≤ 20 10 ±20% 4 > 20 15 ±20% Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the charger: a P-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set internally. This voltage is typically 6V. Consequently, logic-level threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), total gate capacitance QG, reverse transfer capacitance CRSS, input voltage and maximum output current. The charger is operating in continuous mode at moderate to high currents so the duty cycles for the top and bottom MOSFETs are given by: highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch in nearly 100%. The term (1 + δ∆T) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics; if not, then CRSS can be calculated using CRSS = QGD/∆VDS. The constant k␣ =␣ 2 can be used to estimate the contributions of the two terms in the main switch dissipation equation. If the charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside P-channel efficiency generally improves with a larger MOSFET. Using asymmetrical MOSFETs may achieve cost savings or efficiency gains. The Schottky diode D1, shown in the Typical Application on the back page, conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current. Larger diodes can result in additional transition losses due to their larger junction capacitance. Main Switch Duty Cycle = VOUT/VIN The diode may be omitted if the efficiency loss can be tolerated. Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN. Calculating IC Power Dissipation The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT/VIN(I2MAX)(1 + δ∆T)RDS(ON) + k(V2IN)(IMAX)(CRSS)(fOSC) PSYNC = (VIN – VOUT)/VIN(I2MAX)(1 + δ∆T)RDS(ON) Where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the PMAIN equation includes an additional term for transition losses, which are The power dissipation of the LTC4006 is dependent upon the gate charge of the top and bottom MOSFETs (QG1 and QG2 respectively) The gate charge is determined from the manufacturer’s data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the MOSFET. Use 6V for the gate voltage swing and VDCIN for the drain voltage swing. PD = VDCIN • (fOSC (QG1 + QG2) + IDCIN) sn4006 4006is 12 LTC4006 U W U U APPLICATIO S I FOR ATIO Table 5. Common RCL Resistor Values Example: VDCIN = 19V, fOSC = 345kHz, QG1 = QG2 = 15nC. PD = 292mW Adapter Limiting An important feature of the LTC4006 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being charged without complex load management algorithms. Additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. True analog control is used, with closed-loop feedback ensuring that adapter load current remains within limits. Amplifier CL1 in Figure 9 senses the voltage across RCL, connected between the CLP and DCIN pins. When this voltage exceeds 100mV, the amplifier will override programmed charging current to limit adapter current to 100mV/RCL. A lowpass filter formed by 5kΩ and 15nF is required to eliminate switching noise. If the current limit is not used, CLP should be connected to CLN. LTC4006 100mV – + CLP 18 15nF CL1 5k + RCL* CLN 19 *RCL = 100mV ADAPTER CURRENT LIMIT + AC ADAPTER INPUT VIN CIN 4006 F09 Figure 9. Adapter Current Limiting Setting Input Current Limit To set the input current limit, you need to know the minimum wall adapter current rating. Subtract 5% for the input current limit tolerance and use that current to determine the resistor value. RCL = 100mV/ILIM ILIM = Adapter Min Current – (Adapter Min Current • 5%) ADAPTER RATING (A) RCL VALUE* (Ω) 1% RCL POWER DISSIPATION (W) RCL POWER RATING (W) 1.5 0.06 0.135 0.25 1.8 0.05 0.162 0.25 2 0.045 0.18 0.25 2.3 0.039 0.206 0.25 2.5 0.036 0.225 0.5 2.7 0.033 0.241 0.5 3 0.03 0.27 0.5 * Values shown above are rounded to nearest standard value. As is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see Table 5). Designing the Thermistor Network There are several networks that will yield the desired function of voltage vs temperature needed for proper operation of the thermistor. The simplest of these is the voltage divider shown in Figure 10. Unfortunately, since the HIGH/LOW comparator thresholds are fixed internally, there is only one thermistor type that can be used in this network; the thermistor must have a HIGH/LOW resistance ratio of 1:7. If this happy circumstance is true for you, then simply set R9 = RTH(LOW) If you are using a thermistor that doesn’t have a 1:7 HIGH/ LOW ratio, or you wish to set the HIGH/LOW limits to different temperatures, then the more generic network in Figure 11 should work. Once the thermistor, RTH, has been selected and the thermistor value is known at the temperature limits, then resistors R9 and R9A are given by: For NTC thermistors: R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – RTH(HIGH)) R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – 7 • RTH(HIGH)) For PTC thermistors: R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – RTH(LOW)) R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – 7 • RTH(LOW)) sn4006 4006is 13 LTC4006 U W U U APPLICATIO S I FOR ATIO LTC4006 LTC4006 R9 NTC R9 NTC C7 RTH C7 4006 F10 Figure 10. Voltage Divider Thermistor Network Example #1: 10kΩ NTC with custom limits TLOW = 0°C, THIGH = 50°C RTH = 10k at 25°C, RTH(LOW) = 32.582k at 0°C RTH(HIGH) = 3.635k at 50°C R9 = 24.55k → 24.3k (nearest 1% value) R9A = 99.6k → 100k (nearest 1% value) Example #2: 100kΩ NTC TLOW = 5°C, THIGH = 50°C RTH = 100k at 25°C, RTH(LOW) = 272.05k at 5°C RTH(HIGH) = 33.195k at 50°C R9 = 226.9k → 226k (nearest 1% value) R9A = 1.365M → 1.37M (nearest 1% value) Example #3: 22kΩ PTC TLOW = 0°C, THIGH = 50°C RTH = 22k at 25°C, RTH(LOW) = 6.53k at 0°C RTH(HIGH) = 61.4k at 50°C R9 = 43.9k → 44.2k (nearest 1% value) R9A = 154k Sizing the Thermistor Hold Capacitor During the hold interval, C7 must hold the voltage across the thermistor relatively constant to avoid false readings. A reasonable amount of ripple on NTC during the hold interval is about 10mV to 15mV. Therefore, the value of C7 is given by: C7 = t HOLD /(R9/7 • –ln(1 – 8 • 15mV/4.5V)) = 10 • RRT • 17.5pF/(R9/7 • – ln(1 – 8 • 15mV/4.5V) Example: R9 = 24.3k RRT = 309k (~2 hour timer) C7 = 0.58µF → 0.56µF (nearest value) R9A RTH 4006 F11 Figure 11. General Thermistor Network Disabling the Thermistor Function If the thermistor is not needed, connecting a resistor between DCIN and NTC will disable it. The resistor should be sized to provide at least 10µA with the minimum voltage applied to DCIN and 10V at NTC. Do not exceed 30µA into NTC. Generally, a 301k resistor will work for DCIN less than 15V. A 499k resistor is recommended for DCIN between 15V and 24V. PCB Layout Considerations For maximum efficiency, the switch node rise and fall times should be minimized. To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential. (See Figure 12.) Here is a PCB layout priority list for proper layout. Layout the PCB using this specific order. 1. Input capacitors need to be placed as close as possible to switching FET’s supply and ground connections. Shortest copper trace connections possible. These parts must be on the same layer of copper. Vias must not be used to make this connection. 2. The control IC needs to be close to the switching FET’s gate terminals. Keep the gate drive signals short for a clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB relative to above. 3. Place inductor input as close as possible to switching FET’s output connection. Minimize the surface area of this trace. Make the trace width the minimum amount needed to support current—no copper fills or pours. Avoid running the connection using multiple layers in parallel. Minimize capacitance from this node to any other trace or plane. 4. Place the output current sense resistor right next to the inductor output but oriented such that the IC’s sn4006 4006is 14 LTC4006 U W U U APPLICATIO S I FOR ATIO current sense feedback traces going to resistor are not long. The feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. Locate any filter component on these traces next to the IC and not at the sense resistor location. 9. A good rule of thumb for via count for a given high current path is to use 0.5A per via. Be consistent. 5. Place output capacitors next to the sense resistor output and ground. 10. If possible, place all the parts listed above on the same PCB layer. 6. Output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. 11. Copper fills or pours are good for all power connections except as noted above in Rule 3. You can also use copper planes on multiple layers in parallel too—this helps with thermal management and lower trace inductance improving EMI performance further. General Rules 7. Connection of switching ground to system ground or internal ground plane should be single point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. Route analog ground as a trace tied back to IC ground (analog ground pin if present) before connecting to any other ground. Avoid using the system ground plane. CAD trick: make analog ground a separate ground net and use a 0Ω resistor to tie analog ground to system ground. 12. For best current programming accuracy provide a Kelvin connection from RSENSE to CSP and BAT. See Figure 12 as an example. It is important to keep the parasitic capacitance on the RT, CSP and BAT pins to a minimum. The traces connecting these pins to their respective resistors should be as short as possible. SWITCH NODE DIRECTION OF CHARGING CURRENT L1 VBAT VIN C2 RSNS HIGH FREQUENCY CIRCULATING PATH D1 C3 BAT 4006 F13 CSP BAT 4006 F12 Figure 12. High Speed Switching Path Figure 13. Kelvin Sensing of Charging Current U PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .053 – .068 (1.351 – 1.727) .004 – .0098 (0.102 – 0.249) 16 15 14 13 12 11 10 9 .009 (0.229) REF .045 ±.005 0° – 8° TYP .229 – .244 .0250 (5.817 – 6.198) (0.635) BSC NOTE: 1. CONTROLLING DIMENSION: INCHES *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 3. DRAWING NOT TO SCALE .016 – .050 (0.406 – 1.270) .150 – .157** (3.810 – 3.988) .008 – .012 (0.203 – 0.305) .254 MIN .150 – .165 GN16 (SSOP) 0502 1 2 3 4 5 6 7 8 .0165 ± .0015 .0250 TYP RECOMMENDED SOLDER PAD LAYOUT sn4006 4006is 15 LTC4006 U TYPICAL APPLICATIO 2A Li-Ion Battery Charger Q3 INPUT SWITCH DCIN 0V TO 20V 2.5A C1 0.1µF VLOGIC R3 100k DCIN CHG CHG ACP/SHDN ACP CHARGING CURRENT MONITOR THERMISTOR 10k NTC INFET LTC4006 CLP R9 32.4k C5 0.0047µF C7 0.47µF RT 309k TIMING RESISTOR (~2 HOURS) R4 6.04k C6 0.12µF D1: MBRM140T3 Q1, Q3: Si3457 Q2: Si3454 R1 5k C4 15nF RCL 0.04Ω TO LOAD C2 20µF CLN IMON TGATE NTC BGATE RT PGND ITH CSP GND BAT Q1 L1 22µH 2A RSENSE 0.05Ω BATTERY Q2 D1 C3 20µF 4006 TA02 RELATED PARTS PART NUMBER LT®1511 DESCRIPTION 3A Constant-Current/Constant-Voltage Battery Charger LT1513 LTC1729 Sepic Constant- or Programmable- Current/ConstantVoltage Battery Charger 1.5A Switching Charger 2-Phase, Dual Synchronous Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller with VID Li-Ion Battery Charger Termination Controller LT1769 2A Switching Battery Charger LTC1778 Wide Operating Range, No RSENSETM Synchronous Step-Down Controller Dual Battery Charger/Selector with SPI Interface LT1571 LTC1628-PG LTC1709 LTC1960 LTC3711 LTC4007 LTC4008 No RSENSE Synchronous Step-Down Controller with VID High Efficiency, Programmable Voltage, Battery Charger with Termination High Efficiency, Programmable Voltage/Current Battery Charger COMMENTS High Efficiency, Minimum External Components to Fast Charge Lithium, NIMH and NiCd Batteries Charger Input Voltage May be Higher, Equal to or Lower Than Battery Voltage, 500kHz Switching Frequency 1- or 2-Cell Li-Ion, 500kHz or 200kHz Switching Frequency, Termination Flag Minimizes CIN and COUT, Power Good Output, 3.5V ≤ VIN ≤ 36V Up to 42A Output, Minimum CIN and COUT, Uses Smallest Components for Intel and AMD Processors Trickle Charge Preconditioning, Temperature Charge Qualification, Time or Charge Current Termination, Automatic Charger and Battery Detection, and Status Output Constant-Current/Constant-Voltage Switching Regulator, Input Current Limiting Maximizes Charge Current 2% to 90% Duty Cycle at 200kHz, Stable with Ceramic COUT Simultaneous Charge or Discharge of Two Batteries, DAC Programmable Current and Voltage, Input Current Limiting Maximizes Charge Current 3.5V ≤ VIN ≤ 36V, 0.925V ≤ VOUT ≤ 2V, for Transmeta, AMD and Intel Mobile Processors Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit, Thermistor Sensor and Indicator Outputs Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage/ Current Programming, AC Adapter Current Limit and Thermistor Sensor and Indicator Outputs No RSENSE is a trademark of Linear Technology Corporation. sn4006 4006is 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT/TP 0503 1K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2003