SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993
•
•
•
•
•
•
DW PACKAGE
(TOP VIEW)
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
G
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
DIR
description
These devices consist of bus transceiver circuits,
3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of
data directly from the data bus or from the internal
storage registers. Data on the A or B bus will be
clocked into the registers on the low-to-high
transition of the appropriate clock pin (CAB or
CBA). Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the octal bus transceivers and registers.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CAB
SAB
B1
B2
B3
B4
VCC
VCC
B5
B6
B7
B8
CBA
SBA
Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode,
data present at the high-impedance port may be stored in either register or in both. The select controls (SAB
and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control will
eliminate the typical decoding glitch which occurs in a multiplexer during the transition between stored and
real-time data. The direction control determines which bus will receive data when enable G is active (low). In
the isolation mode (control G high), A data may be stored in one register and/or B data may be stored in the
other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT11646 is characterized for operation from − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
•
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•
2−1
1
14
28
16
27
15
1
14
28
16
27
15
G
DIR
CAB
CBA
SAB
SBA
G
DIR
CAB
CBA
SAB
SBA
L
X
X
X
L
L
H
X
X
L
X
REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
L
1
14
28
16
27
15
1
14
28
G
DIR
CAB
CBA
SAB
SBA
G
DIR
X
X
↑
X
X
X
L
L
X
X
X
↑
X
X
L
H
H
X
↑
↑
X
X
STORAGE FROM A, B, OR A AND B
16
27
15
CAB
CBA
SAB
SBA
X
H or L
X
H
H or L
X
H
X
TRANSFER STORED DATA TO A OR B
Figure 1. Bus-Management Functions
2−2
BUS B
BUS A
BUS B
BUS A
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993
•
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•
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993
FUNCTION TABLE
INPUTS
G
DIR
X
X
DATA I/O
CAB
CBA
SAB
X
↑
X
X
X
↑
H
X
↑
↑
X
X
H
X
H or L
H or L
X
X
L
L
X
X
X
L
L
L
X
H or L
X
H
L
H
X
X
L
X
L
H
H or L
X
H
X
OPERATION OR FUNCTION
SBA
A1 THRU A8
B1 THRU B8
X
X
X
X
Input
Unspecified†
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
Input
Input
Store A and B Data
Isolation, hold storage
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
† The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbol‡
1
G
14
DIR
16
CBA
15
SBA
28
CAB
27
SAB
A1
2
functional block diagram (positive logic)
G1
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
A2
A3
A4
A5
A6
A7
A8
3
1
SAB
14
16
15
28
27
26
≥1
6D
DIR
CBA
SBA
CAB
1
5
5
7
7
4D
1
≥1
1 of 8
Channels
B1
2
25
A1
B2
4
24
5
23
10
20
11
19
12
18
13
17
1D
C1
2
26
1D
C1
B1
B3
B4
B5
To Seven Other Channels
B6
B7
B8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
•
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•
2−3
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
Dt /Dv
TA
Operating free-air temperature
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
−24
mA
Low-level output current
24
mA
0
10
ns/ V
−40
85
°C
Input transition rise or fall rate
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = − 50 mA
A
VOH
IOZ
II
ICC
DICC¶
Ci
G or DIR
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
5.5 V
4.94
4.8
IOH = − 75 mA‡
5.5 V
IOL = 24 mA
A or B ports§
MIN
IOH = − 24 mA
IOL = 50 mA
A
VOL
TA = 25°C
MIN
TYP
MAX
UNIT
V
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
V
IOL = 75 mA‡
VO = VCC or GND
5.5 V
5.5 V
± 0.5
±5
mA
VI = VCC or GND
VI = VCC or GND, IO = 0
One input at 3.4 V, Other inputs at GND or VCC
5.5 V
± 0.1
±1
mA
5.5 V
8
80
mA
0.9
1
mA
VI = VCC or GND
VO = VCC or GND
1.65
5.5 V
5V
4.5
Co
5V
12
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
§ For I/O ports, the parameter IOZ includes the leakage current.
¶ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
2−4
MAX
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•
pF
pF
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
105
MIN
MAX
UNIT
0
105
MHz
fclock
tw
Clock frequency
Pulse duration, CAB or CBA high or low
4.8
4.8
ns
tsu
th
Setup time, A before CLK↑ or B before CBA↑
4.5
4.5
ns
Hold time, A after CAB↑ or B after CBA↑
2.5
2.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
105
A or B
B or A
tPZH
tPZL
G
A or B
tPHZ
tPLZ
G
A or B
tPLH
tPHL
CBA or CAB
A or B
tPZH
tPZL
DIR
A or B
tPHZ
tPLZ
DIR
A or B
tPLH
tPHL
SBA or SAB
( A or B high)
A or B
tPLH
tPHL
SBA or SAB
( A or B low)
A or B
MIN
MAX
105
UNIT
MHz
1.5
7.3
10.1
1.5
11.5
1.5
7.2
11
1.5
12
1.5
7.7
12.8
1.5
14.4
1.5
9.2
13.8
1.5
15.3
1.5
8.6
10.7
1.5
11.6
1.5
7.8
9.7
1.5
10.6
1.5
8.8
11.9
1.5
13.5
1.5
10
13.4
1.5
14.9
1.5
10.2
13.7
1.5
15.3
1.5
10.9
14.8
1.5
16.5
1.5
7.9
10.5
1.5
11.3
1.5
7.3
9.5
1.5
10.3
1.5
6.7
10.3
1.5
11.5
1.5
9.1
12.1
1.5
13.5
1.5
8
10.9
1.5
12.4
1.5
8.1
11.9
1.5
13.1
ns
ns
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
•
UNIT
63
CL = 50 pF,
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•
TYP
f = 1 MHz
14
pF
2−5
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
3V
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
2−6
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11646DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
74ACT11646DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
74ACT11646NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11646DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
74ACT11646DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
74ACT11646NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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