SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
•
•
•
•
•
•
•
•
DW OR N PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Parallel Registered Outputs
Internal Counters Have Direct Clear
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
QB
QC
QD
GND
GND
GND
GND
QE
QF
QG
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
QA
CCK
CCKEN
CCLR
VCC
VCC
OE
RCK
RCO
QH
description
The 74ACT11590 contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has
parallel outputs. Separate clocks are provided for both the binary counter and storage register.
The binary counter features a direct clear (CCLR) input and a count-enable (CCKEN) input. For cascading, a
ripple-carry (RCO) output is provided. Expansion is easily accomplished for two stages by connecting RCO of
the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by
connecting RCO of each stage to CCK of the following stage.
Both the register and the counter have individual positive-edge-triggered clocks. If both clocks are connected
together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from
the clock enable.
The 74ACT11590 is characterized for operation from − 40°C to 85°C.
logic symbol†
OE
RCK
14
13
18
CCKEN
CCK
19
17
CCLR
EN3
C2
G1
1+
CTR8
4
12
RCO
(CT = 255) Z4
CT = 0
2D
3
20
1
2
3
8
9
10
11
QA
QB
QC
QD
QE
QF
QG
QH
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
•
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•
2−1
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
logic diagram (positive logic)
OE
RCK
CCKEN
CCK
CCLR
14
13
18
12
19
17
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
R
R
R
R
R
R
R
R
2−2
RCO
20
1
2
3
8
9
10
11
•
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•
QA
QB
QC
QD
QE
QF
QH
QH
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
typical operating sequence
CCKEN
CCLR
255
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
CLK
RCK
OE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
QA
QB
QC
QD
QE
QF
QG
QH
RCO
0
1
2
3
Count
3
5
6
7
8
Inhibit
•
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•
9
Counter Clear
10
0
Count
1
2
Outputs
Disabled
2−3
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 225 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t /∆v
Low-level output current
High-level input voltage
2
High-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 2: Unused or floating inputs must be held high or low.
2−4
•
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•
UNIT
V
V
0.8
V
VCC
VCC
V
−24
mA
V
24
mA
0
10
ns/ V
−40
85
°C
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
IOH = − 24 mA
5.5 V
4.94
4.8
IOH = − 75 mA†
5.5 V
IOH = − 50 µA
A
VOH
IOL = 24 mA
IOL = 75 mA†
VI = VCC or GND
II
IOZ
MIN
MAX
UNIT
V
3.85
4.5 V
IOL = 50 µA
A
VOL
TA = 25°C
TYP
MAX
VCC
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
V
1.65
5.5 V
± 0.1
±1
µA
VO = VCC or GND
VI = VCC or GND,
5.5 V
± 0.5
±5
µA
ICC
IO = 0
5.5 V
8
80
µA
∆ICC‡
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
VO = VCC or GND
5V
3
pF
Co
5V
11
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency, CCK or RCK
tw
Pulse duration
tsu
Setup time
0
80
MIN
MAX
UNIT
0
80
MHz
CCK or RCK high or low
6.3
6.3
CCLR low
8.4
8.4
CCKEN low before CCK↑
5.1
5.1
CCLR high before CCK↑
CCK↑ before RCK↑§
1.6
1.6
5.5
5.5
ns
ns
th
Hold time
CCKEN low after CCK↑
0.6
0.6
ns
§ This setup time ensures that the register will see stable data from the counter outputs. The clocks may be tied together, in which case the register
will be one clock pulse behind the counter.
•
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•
2−5
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
TYP
MAX
MIN
4.5
8
11
4.5
13
5.1
9
13.8
5.1
16.4
3.5
7
11
3.5
13.1
4.6
8
11.1
4.6
13
3.9
7.6
11.8
3.9
13.9
4
8.3
13.2
4
15.6
3.8
8.2
13.9
3.8
16.2
5.3
8
10.3
5.3
11.5
6.1
9.1
11.5
6.1
13
3.8
6.8
9.7
3.8
11.2
2.8
7.6
11
2.8
12.8
MIN
CCK or RCK
80
CCK
RCO
CCLR
RCO
tPLH
tPHL
RCK
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
tPLH
tPHL
CCKEN
RCO
MAX
80
UNIT
MHz
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
2−6
Power dissipation capacitance
Outputs disabled
•
UNIT
66
CL = 50 pF,
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•
TYP
f = 1 MHz
42
pF
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
3V
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
≈ VCC
50% VCC
80% VCC
VOH
≈0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
•
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•
2−7
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993
2−8
•
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•
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11590DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
74ACT11590DWR
OBSOLETE
SOIC
DW
0
TBD
Call TI
Call TI
74ACT11590N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11590DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
74ACT11590DWR
OBSOLETE
SOIC
DW
0
TBD
Call TI
Call TI
74ACT11590N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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