a FEATURES Two 12-Bit CMOS DAC Channels with On-Chip Voltage Reference Output Amplifiers Three Selectable Output Ranges per Channel –5 V to +5 V, 0 V to +5 V, 0 V to +10 V Serial Interface 125 kHz DAC Update Rate Small Size: 16-Lead DIP or SOIC Low Power Dissipation APPLICATIONS Process Control Industrial Automation Digital Signal Processing Systems Input/Output Ports LC2MOS Dual 12-Bit Serial DACPORT® AD7249 FUNCTIONAL BLOCK DIAGRAM VDD VSS AD7249 REFOUT 2R ROFSA 2R 12-BIT DAC A REFIN A1 VOUTA 2R ROFSB 2R AGND 12-BIT DAC B A2 VOUTB DGND INPUT SHIFT REGISTER GENERAL DESCRIPTION The AD7249 DACPORT contains a pair of 12-bit, voltageoutput, digital-to-analog converters with output amplifiers and Zener voltage reference on a monolithic CMOS chip. No external trims are required to achieve full specified performance. The output amplifiers are capable of developing +10 V across a 2 kΩ load. The output voltage ranges with single supply operation are 0 V to +5 V or 0 V to +10 V, while an additional bipolar ± 5 V output range is available with dual supplies. The ranges are selected using the internal gain resistor. Interfacing to the AD7249 is serial, minimizing pin count and allowing a small package size. Standard control signals allow interfacing to most DSP processors and microcontrollers. The data stream consists of 16 bits, DB15 to DB13 are don’t care bits, the 13th bit (DB12) is used as the channel select bit and the remaining 12 bits (DB11 to DB0) contain the data to update the DAC. The 16-bit data word is clocked into the input register on each falling SCLK edge. The data format is natural binary in both unipolar ranges, while either offset binary or twos complement format may be selected in the bipolar range. A CLR function is provided which sets the output to 0 V in both unipolar ranges and in the twos complement bipolar range, while with offset binary data format, the output is set to –REFIN. This function is useful as a power-on reset as it allows the outputs to be set to a known voltage level. SCLK SDIN SYNC BIN/COMP CLR LDAC The AD7249 features a serial interface which allows easy connection to both microcomputers and 16-bit digital signal processors with serial ports. The serial data may be applied at rates up to 2 MHz allowing a DAC update rate of 125 kHz. The AD7249 is fabricated on linear compatible CMOS (LC2MOS), an advanced, mixed technology process. It is packaged in 16-lead DIP and 16-lead SOIC packages. PRODUCT HIGHLIGHTS 1. Two complete 12-bit DACPORTs The AD7249 contains two complete voltage output, 12-bit DACs in both 16-lead DIP and SOIC packages. 2. Single or dual supply operation 3. Minimum 3-wire interface to most DSP processors 4. DAC update rate—125 kHz DACPORT is a registered trademark of Analog Devices, Inc. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD7249–SPECIFICATIONS (V = +12 V to +15 V, V = O V or –12 V to –15 V, AGND = DGND = O V, REFIN = +5 V, R = 2 k⍀, C = 100 pF to AGND. All specifications T to T unless otherwise noted.) 1 DD L L MIN 1 SS MAX Parameter A Version2 B Version2 S Version2 Unit STATIC PERFORMANCE Resolution Relative Accuracy3 Differential Nonlinearity3 Unipolar Offset Error3 12 ±1 ± 0.9 ±5 12 ± 1/2 ± 0.9 ±5 12 ±1 ± 0.9 ±6 Bits LSB max LSB max LSB max Bipolar Zero Error3 ±6 ±5 ±7 LSB max Full-Scale Error3, 4 Full-Scale Temperature Coefficient ±6 ±5 ±6 ±5 ±7 ±5 LSB max ppm of FSR/°C typ 4.95/5.05 ± 25 4.95/5.05 ± 25 4.95/5.05 ± 30 V min/V max ppm/°C typ –1 –1 –1 mV max Reference Load Current (IL) Change (0 µA–100 µA) 4.95/5.05 5 4.95/5.05 5 4.95/5.05 5 V min/V max µA max 5 V ± 1% 2.4 0.8 2.4 0.8 2.4 0.8 V min V max ±1 8 ±1 8 ±1 8 µA max pF max VIN = 0 V to VDD 15/30 +5, +10 +5, +10, ± 5 0.5 15/30 +5, +10 +5, +10, ± 5 0.5 15/30 +5, +10 +5, +10, ± 5 0.5 kΩ min/ max V V Ω typ Single Supply; VSS = 0 V Dual Supply; VSS = –12 V or –15 V Settling Time to Within ± 1/2 LSB of Final Value Typically 3 µs Typically 5 µs 1 LSB Change Around Major Carry REFERENCE OUTPUT REFOUT Reference Temperature Coefficient Reference Load Change (∆VREFOUT vs. IL ) REFERENCE INPUT Reference Input Range, REFIN Input Current DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IIN Input Capacitance5 ANALOG OUTPUTS Output Range Resistor, ROFSA & ROFSB Output Voltage Ranges6 Output Voltage Ranges6 DC Output Impedance AC CHARACTERISTICS5 Voltage Output Settling-Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse3 10 10 30 10 10 30 10 10 30 µs max µs max nV secs typ Digital Feedthrough3 Digital Crosstalk3 10 10 10 10 10 10 nV secs typ nV secs typ +10.8/+16.5 +11.4/+15.75 +11.4/+15.75 V min/V max VSS Range (Dual Supplies) –10.8/–16.5 –11.4/–15.75 –11.4/–15.75 V min/V max IDD ISS (Dual Supplies) 15 5 15 5 15 5 mA max mA max POWER REQUIREMENTS VDD Range Test Conditions/Comments Guaranteed Monotonic VSS = 0 V or –12 V to –15 V1; DAC Latch Contents All 0s VSS = –12 V to –15 V1 DAC Latch Contents All 0s For Specified Performance Unless Otherwise Stated For Specified Performance Unless Otherwise Stated Output Unloaded; Typically 11 mA Output Unloaded; Typically 3 mA NOTES 1 Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%. 2 Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C. 3 See Terminology. 4 Measured with respect to REFIN and includes unipolar/bipolar offset error. 5 Guaranteed by design not production tested. 6 0 V to 10 V output range available only with V DD ≥ 14.25 V. Specifications subject to change without notice. –2– REV. C AD7249 3 3 1, 2 (VDD = +12 V to +15 V, VSS = 0 V or –12 V to –15 V, AGND = DGND = 0 V, RL = 2 k⍀, TIMING CHARACTERISTICS Parameter 4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.) Limit at TMIN to TMAX (All Versions) Unit Conditions/Comments 200 15 50 0 150 0 20 0 50 20 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min SCLK Cycle Time SYNC to SCLK Falling Edge Setup Time SYNC to SCLK Hold Time Data Setup Time Data Hold Time SYNC High to LDAC Low LDAC Pulsewidth LDAC High to SYNC Low CLR Pulsewidth SYNC High Time NOTES 1 Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 8. 3 Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%. 4 SCLK Mark/Space Ratio range is 45/55 to 55/45. ABSOLUTE MAXIMUM RATINGS 1 Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature (Soldering) Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C (TA = +25°C unless otherwise noted) VDD to AGND, DGND . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VSS to AGND, DGND . . . . . . . . . . . . . . . . . . +0.3 V to –17 V AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V VOUTA, B2 to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD REFIN to AGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +117°C/W Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any time. 2 The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7249 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– WARNING! ESD SENSITIVE DEVICE AD7249 PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS) Pin Mnemonic Description 11 REFOUT 12 REFIN 13 ROFSB 14 VOUTB 15 16 AGND CLR 17 BIN/COMP 18 19 10 DGND SDIN LDAC 11 12 SCLK SYNC 13 14 VDD VOUTA 15 VSS 16 ROFSA Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part using its internal reference, REFOUT should be connected to REFIN. Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal reference voltage for specified operation of the AD7249 is 5 V. Output Offset Resistor for the amplifier of DAC B. It is connected to VOUTB for the +5 V range, to AGND for the +10 V range and to REFIN for the –5 V to +5 V range. Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V. Analog Ground. Ground reference for all analog circuitry. Clear, Logic Input. Taking this input low clears both DACs. It sets VOUTA and VOUTB to 0 V in both unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar range. Logic Input. This input selects the data format to be either binary or twos complement. In both unipolar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement. Digital Ground. Ground reference for all digital circuitry. Serial Data In, Logic Input. The 16-bit serial data word is applied to this input. Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling edge of this signal or alternatively if this line is permanently low, an automatic update mode is selected whereby both DACs are updated on the 16th falling SCLK pulse. Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge. Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a new data word. Positive Power Supply. Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V. Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single supply operation or –12 V to –15 V for dual supplies. Output Offset Resistor for the amplifier of DAC A. It is connected to VOUTA for the +5 V range, to AGND for the +10 V range and to REFIN for the –5 V to +5 V range. PIN CONFIGURATIONS (DIP and SOIC) REFOUT 1 16 REFIN 2 15 ROFSA VSS ROFSB 3 14 VOUTA AD7249 13 VDD TOP VIEW AGND 5 (Not to Scale) 12 SYNC VOUTB 4 CLR 6 11 SCLK BIN/COMP 7 10 LDAC DGND 8 9 SDIN ORDERING GUIDE Model Temperature Range Relative Accuracy Package Option AD7249AN AD7249BN AD7249AR AD7249BR AD7249SQ1 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB N-16 N-16 R-16 R-16 Q-16 NOTE 1 Available to /883B processing only. Contact your local sales office for military data sheet. –4– REV. C AD7249 This “knee” is an offset effect, not a linearity error, and the transfer function would have followed the dotted line if the output voltage could have gone negative. TERMINOLOGY Bipolar Zero Error Bipolar Zero Error is the voltage measured at VOUT when the DAC is configured for bipolar output and loaded with all 0s (Twos Complement Coding) or with 1000 0000 0000 (Offset Binary Coding). It is due to a combination of offset errors in the DAC, amplifier and mismatch between the internal gain resistors around the amplifier. Full-Scale Error is a measure of the output error when the amplifier output is at full scale (for the bipolar output range full scale is either positive or negative full scale). It is measured with respect to the reference input voltage and includes the offset errors. Normally, linearity is measured between zero (all 0s input code) and full scale (all 1s input code) after offset and full scale have been adjusted out or allowed for, but this is not possible in single supply operation if the offset is negative, due to the knee in the transfer function. Instead, linearity of the AD7249 in the unipolar mode is measured between full scale and the lowest code which is guaranteed to produce a positive output voltage. This code is calculated from the maximum specification for negative offset. For the A and B versions, the linearity is measured between Codes 3 and 4095. For the S grade, linearity is measured between Code 5 and Code 4095. Digital-to-Analog Glitch Impulse Differential Nonlinearity This is the voltage spike that appears at VOUT when the digital code in the DAC Latch changes, before the output settles to its final value. It is normally specified as the area of the glitch in nV-secs and is measured when the digital code is changed by 1 LSB at the major carry transition (0111 1111 1111 to 1000 0000 0000 or 1000 0000 0000 to 0111 1111 1111). Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB or less over the operating temperature range ensures monotonicity. Full-Scale Error Unipolar Offset Error Unipolar Offset Error is the measured output voltage from VOUT with all zeros loaded into the DAC latch, when the DAC is configured for unipolar output. It is due to a combination of the offset errors in the DAC and output amplifier. Digital Feedthrough This is a measure of the voltage spike that appears on VOUT as a result of feedthrough from the digital inputs on the AD7249. It is measured with LDAC held high. CIRCUIT INFORMATION D/A Section Relative Accuracy (Linearity) Relative Accuracy, or endpoint linearity, is a measure of the maximum deviation of the DAC transfer function from a straight line passing through the endpoints of the transfer function. It is measured after allowing for zero and full-scale errors and is expressed in LSBs or as a percentage of full-scale reading. The AD7249 contains two 12-bit voltage-mode D/A converters consisting of highly stable thin film resistors and high-speed NMOS single-pole, double-throw switches. The simplified circuit diagram for the DAC section is shown in Figure 2. The output voltage from the converter has the same polarity as the reference voltage, REFIN, allowing single supply operation. Single Supply Linearity and Gain Error The output amplifier on the AD7249 can have true negative offsets even when the part is operated from a single +15 V supply. However, because the negative supply rail (VSS) is 0 V, the output cannot actually go negative. Instead, when the output offset voltage is negative, the output voltage sits at 0 V, resulting in the transfer function shown in Figure 1. ROFS R 2R 2R 2R R R 2R R 2R 2R VOUT R 2R SHOWN FOR ALL 1s ON DAC REFIN* AGND OUTPUT VOLTAGE 2R *BUFFERED REFIN VOLTAGE Figure 2. D/A Simplified Circuit Diagram 0V NEGATIVE OFFSET DAC CODE Figure 1. Effect of Negative Offset (Single Supply) REV. C –5– AD7249 Internal Reference Op Amp Section The AD7249 has an on-chip temperature compensated buried Zener reference which is factory trimmed to 5 V ± 50 mV. The reference voltage is provided at the REFOUT pin. This reference can be used to provide the reference voltage for the D/A converter by connecting the REFOUT pin to the REFIN pin. The output of the voltage-mode D/A converter is buffered by a noninverting CMOS amplifier. The ROFS input allows three output voltage ranges to be selected. The buffer amplifier is capable of developing +10 V across a 2 kΩ load to AGND. The output amplifier can be operated from a single +15 V supply by tying VSS = 0 V. The reference voltage can also be used as a reference for other components and is capable of providing up to 500 µA to an external load. The maximum recommended capacitance on REFOUT for normal operation is 50 pF. If the reference output is required to drive a capacitive load greater than 50 pF, then a 200 Ω resistor should be placed in series with the capacitive load. Figure 3 shows the suggested REF OUT decoupling scheme, a 200 Ω resistor and the parallel combination of a 10 µF tantalum and a 0.1 µF ceramic capacitor. This decoupling scheme reduces the noise spectral density of the reference. The amplifier can also be operated from dual supplies to allow an additional bipolar output range of –5 V to +5 V. Dual supplies are necessary for the bipolar output range but can also be used for the unipolar ranges to give faster settling time to voltages near 0 V, to allow full sink capability of 2.5 mA over the entire output range and to eliminate the effects of negative offsets on the transfer characteristic (outlined previously). A plot of the output sink capability of the amplifier is shown in Figure 5. 3 200⍀ REFOUT VSS = –15V EXT LOAD 0.1F 2 ISINK – mA 10F Figure 3. Reference Decoupling Scheme VSS = 0V 1 External Reference In some applications, the user may require a system reference or some other external reference to drive the AD7249. References such as the AD586 provide an ideal external reference source (See Figure 10). The REFIN voltage is internally buffered by a unity gain amplifier before being applied to the D/A converter. The D/A converter is scaled for a 5 V reference and the device is tested with 5 V applied to REFIN. Other reference voltages may be used with degraded performance. Figure 4 shows the degradation in linearity vs. REFIN. 0 2 4 6 OUTPUT VOLTAGE – Volts 8 10 Figure 5. Amplifier Sink Current 500 VDD = +15V VSS = 0V TA = +25ⴗC 200 1.0 REFERENCE (NO DECOUPLING) 0.8 nV/ Hz VDD = +15V VSS = –15V TA = +25ⴗC 0.9 LINEARITY ERROR – LSBs 0 0.7 100 REFERENCE (DECOUPLED*) 50 0.6 0.5 OUTPUT WITH ALL 0s ON DAC 20 0.4 INL 0.3 0 50 0.2 DNL 0.1 0.0 100 200 500 1k 2k 5k 10k FREQUENCY – Hz 20k 50k 100k * REFERENCE DECOUPLING COMPONENTS ARE A 200⍀ RESISTOR IN SERIES WITH A PARALLEL COMBINATION OF 10F AND 0.1F TO GND. 2 3 4 5 6 REFIN – Volts 7 8 9 Figure 6. Noise Spectral Density vs. Frequency Figure 4. Linearity vs. REFIN Voltage –6– REV. C AD7249 There are two ways in which a DAC latches and hence the analog outputs may be updated. The status of the LDAC input is examined after SYNC is taken low. Depending on its status, one of two update modes are selected. DIGITAL INTERFACE The AD7249 contains an input serial to parallel shift register and a DAC latch for both DAC A and DAC B. A simplified diagram of the input loading circuitry is shown in Figure 7. Serial data on the SDIN input is loaded to the input register under control of SYNC and SCLK. The SYNC input provides the frame synchronization signal which tells the AD7249 that valid serial data on the SDIN input will be available for the next 16 falling edges of SCLK. An internal counter/decoder circuit provides a low gating signal so that only 16 data bits are clocked into the input shift register. After 16 SCLK pulses the internal gating signal goes inactive (high) thus locking out any further clock pulses. Therefore either a continuous clock or a burst clock source may be used to clock in the data. The SYNC input is taken high after the complete 16-bit word is loaded in. If LDAC = 0, then the automatic update mode is selected. In this mode the DAC latch and analog output are updated automatically when the last bit in the serial data stream is clocked in. The update thus takes place on the sixteenth falling SCLK edge. If LDAC = 1, then the automatic update is disabled and both DAC latches are updated by taking LDAC low any time after the 16-bit data transfer is complete. The update now occurs on the falling edge of LDAC. Note that the LDAC input must be taken back high again before the next data transfer is initiated. When a complete word is held in the shift register it may then be loaded into the DAC latch under control of LDAC. DAC selection is accomplished using the thirteenth bit (DB12) of the serial data input stream. A zero in DB12 will select DAC A while a one in this position selects DAC B. Although 16 bits of data are clocked into the input register, only 12 bits get transferred into the DAC latch. The relevant DAC latch is determined by the value of the thirteenth bit and the first three bits in the 16-bit stream are don’t cares. Therefore, the data format is three don’t cares followed by the DAC selection bit and the 12-bit data word with the LSB as the last bit in the serial stream. Clear Function (CLR) The clear function clears the contents of the input shift register and loads both DAC latches with all 0s. It is activated by taking CLR low. In all ranges except the Offset Binary bipolar range (–5 V to +5 V) the output voltage is reset to 0 V. In the offset binary bipolar range the output is set to –REFIN. The clear function is especially useful at power-up as it enables the output to be reset to a known state. SYNC DAC LATCH A (12-BITS) RESET SCLK /16 COUNTER/ DECOUNTER GATING SIGNAL CLK A SHIFT REGISTER A DECODER SDATA SDIN CLK B SHIFT REGISTER B AUTO-UPDATE CIRCUITRY LDAC DAC LATCH B (12-BITS) CLR Figure 7. Simplified Loading Structure REV. C –7– AD7249 t1 SCLK t3 t2 t10 SYNC t5 t4 SDIN DB15 DB14 DON'T CARE DON'T DON'T DAC CARE CARE SELECT =0 DB13 DB12 DB11 DB0 DB15 MSB LSB DON'T CARE DB12 DB10 DB0 DON'T DON'T DAC CARE CARE SELECT =1 DB14 DB13 MSB LSB DAC A t6 DAC B t7 t8 LDAC t9 CLR Figure 8. Timing Diagram restricted to +15 V ± 10% for this range in order to maintain sufficient amplifier headroom. Dual supplies may be used to improve settling time and give increased current sink capability for the amplifier. Figure 9 shows the connection diagram for unipolar operation of the AD7249. Table I shows the digital code vs. analog output for this configuration. TRANSFER FUNCTION The internal scaling resistors provided on the AD7249 allow several output voltage ranges. The part can produce unipolar output ranges of 0 V to +5 V or 0 V to +10 V and a bipolar output range of ± 5 V. Connections for the various ranges are outlined below. Since each DAC has its own ROFS input the two DACs can be set up for different output ranges. Unipolar (0 V to +5 V) Configuration The 0 V to +5 V output voltage range is achieved by tying ROFSA to VOUTA or ROFSB to VOUTB. Once again, the AD7249 can be operated using either single or dual supplies. The table for output voltage versus digital code is as in Table I, with 2REFIN replaced by REFIN. Note, for this range, 1 LSB = REFIN × (2–12) = (REFIN/4096). Unipolar (0 V to +10 V) Configuration The first of the configurations provides an output voltage range of 0 V to +10 V. This is achieved by connecting the output offset resistor ROFSA, ROFSB (Pin 3, 16) to AGND. Natural Binary data format is selected by connecting BIN/COMP (Pin 7) to DGND. In this configuration, the AD7249 can be operated using either single or dual supplies. Note that the VDD supply is Table I. Unipolar Code Table (0 V to +10 V Range) VDD VDD 2R REFOUT ROFSA 2R 12-BIT DAC A VOUTA 0V TO 10V A1 ROFSB 2R REFIN 2R AD7249* 12-BIT DAC B Analog Output, VOUT XXXY 1111 1111 1111 XXXY 1000 0000 0001 +2REFIN × (4095/4096) +2REFIN × (2049/4096) XXXY 1000 0000 0000 XXXY 0111 1111 1111 +2REFIN × (2048/4096) = +REFIN +2REFIN × (2047/4096) XXXY 0000 0000 0001 XXXY 0000 0000 0000 +2REFIN × (1/4096) 0V X = Don’t Care. Y = DAC Select Bit, 0 = DAC A, 1= DAC B. Note: 1 LSB = 2REFIN/4096. VOUTB 0V TO 10V A2 Input Data Word MSB LSB BIN/COMP VSS 0V OR VSS AGND DGND *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 9. Unipolar (0 V to +10 V) Configuration –8– REV. C AD7249 Bipolar (ⴞ5 V) Configuration Bipolar Operation (Offset Binary Data Format) The bipolar configuration for the AD7249, which gives an output range of –5 V to +5 V, is achieved by connecting ROFSA, ROFSB to VREFIN. The AD7249 must be operated from dual supplies to achieve this output voltage range. Either offset binary or twos complement coding may be selected. Figure 10 shows the connection diagram for bipolar operation. An AD586 provides the reference voltage for the DAC but this could be provided by the on-chip reference by connecting REFOUT to REFIN. The AD7249 is configured for Offset Binary data format by connecting BIN/COMP (Pin 7) low. The analog output vs. digital code may be obtained by inverting the MSB in Table II. VDD VDD 2R AD7249* +VIN AD586 12-BIT DAC A VOUT ROFSA 2R REFIN A1 VOUTA –5V TO +5V 2R ROFSB 2R 12-BIT DAC B VSS AGND DGND A2 VOUTB –5V TO +5V BIN/COMP VDD VSS *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 10. Bipolar Configuration with External Reference Bipolar Operation (Twos Complement Data Format) The AD7249 is configured for twos complement data format by connecting BIN/COMP (Pin 7) high. The analog output vs. digital code is shown in Table II. Table II. Twos Complement Bipolar Code Table Input Data Word MSB LSB Analog Output, VOUT XXXY 0111 1111 1111 XXXY 0000 0000 0001 XXXY 0000 0000 0000 XXXY 1111 1111 1111 XXXY 1000 0000 0001 XXXY 1000 0000 0000 +REFIN × (2047/2048) +REFIN × (1/2048) 0V –REFIN × (1/2048) –REFIN × (2047/2048) –REFIN × (2048/2048) = –REFIN X = Don’t Care. Y = DAC Select Bit, 0 = DAC A, 1 = DAC B. Note: 1 LSB = REFIN/2048. REV. C APPLYING THE AD7249 Good printed circuit board layout is as important as the overall circuit design itself in achieving high speed converter performance. The AD7249 works on an LSB size of 2.44 mV for the unipolar 0 V to 10 V range and the bipolar ± 5 V range, when using the unipolar 0 V to 5 V range the LSB size is 1.22 mV. Therefore the designer must be conscious of minimizing noise in both the converter itself and in the surrounding circuitry. Switching mode power supplies are not recommended as switching spikes can feedthrough to the on-chip amplifier. Other causes of concern are ground loops and feedthrough from microprocessors. These are factors which influence any high performance converter, and proper printed circuit board layout which minimizes these effects is essential to obtain high performance. LAYOUT HINTS Ensure that the layout has the digital and analog tracks separated as much as possible. Take care not to run any digital track alongside an analog signal track. Establish a single point analog ground separate from the logic system ground. Place this star ground as close as possible to the AD7249. Connect all analog grounds to this star point and also connect the AD7249 DGND pin to this point. Do not connect any other digital grounds to this analog ground point. Low impedance analog and digital power supply common returns are essential for low noise operation of high performance converters. To accomplish this track widths should be kept a wide as possible and also the use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. NOISE Keep the signal leads on the VOUTA and VOUTB signals and the signal return leads to AGND as short as possible to minimize noise coupling. In applications where this is not possible use a shielded cable between the DAC outputs and their destination. Reduce the ground circuit impedance as much as possible since any potential difference in grounds between the DAC and its destination device appears as an error voltage in series with the DAC output. Power Supply Decoupling To achieve optimum performance when using the AD7249, the VDD and VSS lines should be decoupled to AGND using 0.1 µF capacitors. In noisy environments it is recommended that 10 µF capacitors be connected in parallel with the 0.1 µF capacitors. –9– AD7249 DSP56000 and applied to the AD7249 SCLK input. Data from the DSP56000 is valid on the falling edge of SCK. The SC2 output provides the framing pulse for valid data. This line must be inverted before being applied to the SYNC input of the AD7249. MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD7249 is via a serial bus which uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a three-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD7249 requires a 16-bit data word with data valid on the falling edge of SCLK. For all the interfaces, the DAC update may be done automatically when all the data is clocked in or it may be done under control of LDAC. TIMER AD7249* DSP56000 LDAC Figures 11 to 15 show the AD7249 configured for interfacing to a number of popular DSP processors and microcontrollers. SCK SCLK AD7249–ADSP-2101/ADSP-2102 Interface STD SDIN SC2 SYNC Figure 11 shows a serial interface between the AD7249 and the ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/ ADSP-2102 contains two serial ports and either port may be used in the interface. The data transfer is initiated by TFS going low. Data from the ADSP-2101/ADSP-2102 is clocked into the AD7249 on the falling edge of SCLK. DB12 of the 16-bit serial data stream selects the DAC to be updated. Both DACs can be updated by holding LDAC high while performing two write cycles to the DAC. TFS must be taken high after each 16 bit write cycle. LDAC is brought low at the end of the second cycle and both DAC outputs are updated together. In the interface shown the DAC is updated using an external timer which generates an LDAC pulse. This could also be done using a control or decoded address line from the processor. Alternatively, if the LDAC input is hardwired low the output update takes place automatically on the 16th falling edge of SCLK. TIMER ADSP-2101/ ADSP-2102* AD7249* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 12. AD7249–DSP56000 Interface In this interface an external LDAC pulse generated from an external timer is used to update the outputs of the DACs. This update can also be produced using a bit programmable control line from the DSP56000. AD7249–TMS32020 Interface Figure 13 shows a serial interface between the AD7249 and the TMS32020 DSP processor. In this interface, the CLKX and FSX signals for the TMS32020 should be generated using external clock/timer circuitry. The FSX pin of the TMS32020 must be configured as an input. Data from the TMS32020 is valid on the falling edge of CLKX. The clock/timer circuitry generates the LDAC signal for the AD7249 to synchronize the update of the output with the serial transmission. Alternatively, the automatic update mode may be selected by connecting LDAC to DGND. LDAC SCLK SCLK DT SDIN TFS SYNC CLOCK/ TIMER LDAC TMS32020 AD7249* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 11. AD7249–ADSP-2101/ADSP-2102 Interface AD7249–DSP56000 Interface A serial interface between the AD7249 and the DSP56000 is shown in Figure 12. The DSP56000 is configured for Normal Mode Asynchronous operation with Gated Clock. It is also set up for a 16-bit word with SCK and SC2 as outputs and the FSL control bit set to a “0.” SCK is internally generated on the FSX SYNC CLKX SCLK DX SDIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 13. AD7249–TMS32020 Interface –10– REV. C AD7249 AD7249–68HC11 Interface Figure 14 shows a serial interface between the AD7249 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the AD7249 while the MOSI output drives the serial data line of the AD7249. The SYNC signal is derived from a port line (PC0 shown). For correct operation of this interface, the 68HC11 should be configured such that its CPOL bit is a 0 and its CPHA bit is a 1. When data is to be transmitted to the part, PC0 is taken low. When the 68HC11 is configured like this, data on MOSI is valid on the falling edge of SCK. The 68HC11 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7249, PC0 is left low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7249. When the second serial transfer is complete, the PC0 line is taken high. Figure 14 shows the LDAC input of the AD7249 being driven from another bit programmable port line (PC1). As a result, both DACs can be updated simultaneously by taking LDAC low after both DACs latches have updated. AD7249* 68HC11* PC1 LDAC PC0 SYNC SCK SCLK MOSI SDIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 14. AD7249–68HC11 Interface AD7249–87C51 Interface A serial interface between the AD7249 and the 87C51 microcontroller is shown in Figure 15. TXD of the 87C51 drives SCLK of the AD7249 while RXD drives the serial data line of the part. The SYNC signal is derived from the port line P3.3 and the LDAC line is driven port line P3.2. The 87C51 provides the LSB of its SBUF register as the first bit in the serial data stream. Therefore, the user will have to ensure that the data in the SBUF register is arranged correctly so that the don’t care bits are the first to be transmitted to the AD7249 and the last bit to be sent is the LSB of the word to be loaded to the AD7249. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 87C51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7249, P3.3 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the AD7249 with DB12 used to select the appropriate DAC register. When the second serial transfer is complete, the P3.3 line is taken high and then taken low again to start the loading sequence to the second DAC (see timing diagram Figure 8). REV. C Figure 15 shows the LDAC input of the AD7249 driven from the bit programmable port line P3.2. As a result, both DAC outputs can be updated simultaneously by taking the LDAC line low following the completion of the write cycle to the second DAC. Alternatively LDAC could be hardwired low and the analog output will be updated on the sixteenth falling edge of TXD after the SYNC signal for the DAC has gone low. AD7249* 87C51* P3.2 LDAC P3.3 SYNC TXD SCLK RXD SDIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 15. AD7249–87C51 Interface APPLICATIONS OPTO-ISOLATED INTERFACE In many process control type applications it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kΩ. The serial loading structure of the AD7249 makes it ideal for opto-isolated interfaces as the number of interface lines is kept to a minimum. Figure 16 shows a 2-channel isolated interface using the AD7249. The sequence of events to program the output channels is as follows. 1. Take the SYNC line low. 2. Transmit the 16-bit word for DAC A (DB 12 of the 16-bit data word selects the DAC, DB12 = 0 to select DAC A) and bring the SYNC line high after the 16 bits have been transmitted. 3. Bring SYNC line low again and transmit 16 bits for DAC B, bring SYNC back high at end of transmission. 4. Pulse the LDAC line low. This updates both output channels simultaneously on the falling edge of LDAC. –11– AD7249 VDD DATA OUT VDD SDIN VDD VOUTA C00997a–0–6/00 (rev. C) VOUTA SCLK CLOCK OUT AD7249* CONTROLLER SYNC SYNC OUT VDD LDAC VOUTB VOUTB CONTROL OUT *ADDITIONAL PINS OMITTED FOR CLARITY. QUAD OPTO-COUPLER Figure 16. Opto-Isolated Interface OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 16 9 1 8 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) PIN 1 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) 0.195 (4.95) 0.115 (2.93) 0.150 (3.81) 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE (2.54) 0.014 (0.356) BSC 0.045 (1.15) 0.015 (0.381) 0.008 (0.204) Wide Body SOIC (R-16) Cerdip (Q-16) 16 16 0.299 (7.60) 0.291 (7.40) PIN 1 8 0.050 (1.27) BSC 0.010 (0.25) 0.004 (0.10) 0.271 (6.89) 0.240 (6.09) 1 9 1 9 0.107 (2.72) 0.089 (2.26) 0.018 (0.46) SEATING 0.015 (0.38) 0.014 (0.36) PLANE 0.007 (0.18) 8 PIN 1 0.780 (19.81) 0.419 (10.65) 0.404 (10.26) 0.125 (3.17) MIN 0.364 (9.246) 0.344 (8.738) 8ⴗ 0ⴗ PRINTED IN U.S.A. 0.413 (10.50) 0.348 (10.10) 0.300 (7.62) REF 0.163 (4.14) 0.133 (3.378) 0.21 (5.33) 0.15 (3.81) 0.02 (0.5) 0.11 (2.79) 0.06 (1.52) SEATING 0.016 (0.406) 0.099 (2.28) 0.05 (1.27) PLANE 15ⴗ 0ⴗ 0.012 (0.305) 0.008 (0.203) 0.045 (1.15) 0.020 (0.50) –12– REV. C