PHILIPS SAA7186

INTEGRATED CIRCUITS
DATA SHEET
SAA7186
Digital video scaler
Preliminary specification
File under Integrated Circuits, IC22
May 1993
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
8
OPERATION CYCLE
9
I2C-BUS FORMAT
10
LIMITING VALUES
11
DC CHARACTERISTICS
12
AC CHARACTERISTICS
13
PROCESSING DELAYS
14
PROGRAMMING EXAMPLE
15
PACKAGE OUTLINE
16
SOLDERING
17
DEFINITIONS
18
LIFE SUPPORT APPLICATIONS
19
PURCHASE OF PHILIPS I2C COMPONENTS
May 1993
2
Philips Semiconductors
Preliminary specification
Digital video scaler
1
SAA7186
FEATURES
2
• Scaling of video picture windows down to randomly
sized windows
GENERAL DESCRIPTION
The CMOS circuit SAA7186 scales and filters digital video
data to randomly sized picture windows. YUV input data in
4:2:2 format are required (SAA7191B source).
• Processes maximum 1023 pixels per line and 1023 lines
per field
• Two-dimensional data processing for improved signal
quality of scaled video data and for compression of
video data
• 16-bit YUV input data buffer
• Interlace/non-interlace video data processing and field
control
• Line memories in Y path and UV path to store two lines,
each with 2 × 768 × 8 bit capacity
• Vertical sync processing by scale control
• Non-scaled mode to get full picture or to gate videotext
lines
• UV input and output data binary/two’s complement
• Switchable RGB matrix and anti-gamma ROMs
• 16-word FIFO register for 32-bit output data
• Output formats: 5-bit and 8-bit RGB, 8-bit YUV or 8-bit
monochrome
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
4.5
5
5.5
V
IDD tot
total supply current (inputs LOW, without output load)
-
-
180
mA
VI
data input level
TTL-compatible
VO
data output level
TTL-compatible
LLC
input clock frequency
-
-
32
MHz
Tamb
operating ambient temperature range
0
-
70
°C
4
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA7186
May 1993
PACKAGE
PINS
100
PIN POSITION
QFP
MATERIAL
plastic
3
CODE
SOT317-2
May 1993
4
45
SCL
46
I C
CONTROL
2
INPUT
DATA
BUFFER
UV
Y
status
controls
CHROMA
DECIMATION
FILTER
LUMINANCE
DECIMATION
FILTER
35
36
CLOCK
GENERATION
V
U
Y
8
AP
7
SP
V
U
8
VSS1 to V
15
SS8
i.c.
4, 6,
49
48
47
50
51
2
output pins (1):
56 to 64
68 to 75, 77
80 to 88
92 to 100
1
OUTPUT
FIFO
REGISTER
OUTPUT
FORMATTER
9, 15, 21, 27, 29, 39, 34, 41, 52,
54, 60, 66, 72, 79, 84, 90, 96
CHROMA
KEYER
FOLLOWED 8
BY
ANTI-GAMMA 8
ROMs
RGB
MATRIX
3, 16, 28, 42,
53, 65, 78, 89
SAA7186
INTERPOLATOR
Fig.1 Block diagram.
Fig.1 Block diagram.
SCALE CONTROL
LINE
MEMORY
(2x8x768)
VERTICAL FILTER
LINE
MEMORY
(2x8x768)
5, 14, 26,40,
55, 67, 76, 91
VDD1 to VDD8
MEH422-1
n.c.
HREFD
LNQ
HFL
INCADR
32-bit VRAM
port output
RGB or YUV
VRO (31 to 0);
BTST
VOEN
VLCK
Digital video scaler
(1) without pins 60, 72, 84 and 96,
these pins are not connected
LLC
CREF
IICSA
44
43
RESN
SDA
38
VS
37
13
to 10
20
to 17
25
to 22
33
to 30
handbook, full pagewidth
HREF
UVIN
(7-0)
YIN
(7-0)
VERTICAL FILTER
ARITHMETIC
5
ARITHMETIC
+5 V
Philips Semiconductors
Preliminary specification
SAA7186
BLOCK DIAGRAM
Philips Semiconductors
Preliminary specification
Digital video scaler
6
SAA7186
PINNING
SYMBOL
PIN
STATUS
DESCRIPTION
LNQ
1
O
line qualifier signal; active polarity defined by QPL-bit in “10” (VCLK strobed)
HREFD
2
O
delay-compensated HREF output signal (VCLK strobed)
VSS1
3
−
GND1 (0 V)
i.c.
4
−
internally connected
VDD1
5
−
+5 V supply voltage 1
i.c.
6
−
internally connected
SP
7
I
connected to ground (shift pin for testing)
AP
8
I
connected to ground (action pin for testing)
n.c.
9
−
not connected
UVIN0
10
I
UVIN1
11
I
UVIN2
12
I
UVIN3
13
I
VDD2
14
−
+5 V supply voltage 2
n.c.
15
−
not connected
VSS2
16
−
GND2 (0 V)
UVIN4
17
I
UVIN5
18
I
UVIN6
19
I
UVIN7
20
I
n.c.
21
−
YIN0
22
I
YIN1
23
I
YIN2
24
I
YIN3
25
I
VDD3
26
−
+5 V supply voltage 3
time-multiplexed colour-difference input data (bits 0 to 3)
time-multiplexed colour-difference input data (bits 4 to 7)
not connected
luminance input data (bits 0 to 3)
n.c.
27
−
not connected
VSS3
28
−
GND3 (0 V)
n.c.
29
−
not connected
YIN4
30
I
YIN5
31
I
YIN6
32
I
YIN7
33
I
n.c.
34
−
not connected
CREF
35
I
clock reference, external sync signal
LLC
36
I
line-locked system clock input signal (twice of pixel rate)
HREF
37
I
horizontal reference, pixel data clock signal (also present during vertical blanking)
VS
38
I
vertical sync input signal (approximately 6 lines long)
n.c.
39
−
not connected
VDD4
40
−
+5 V supply voltage 4
May 1993
luminance input data (bits 4 to 7)
5
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
SYMBOL
PIN
STATUS
DESCRIPTION
n.c.
41
−
not connected
VSS4
42
−
GND4 (0 V)
RESN
43
I
reset input (active-LOW for at least 30LLC periods)
SDA
44
I/O
IIC-bus data line
SCL
45
I
IIC-bus clock line
IICSA
46
I
set module address input of IIC-bus (LOW = B8, HIGH = BC)
BTST
47
I
output disable input; HIGH sets all data outputs to high-impedance state
INCADR
48
O
line increment / vertical reset control output line
HFL
49
O
FIFO register half-full flag output
VOEN
50
I
VRAM port output enable input (active-LOW)
VCLK
51
I
FIFO register clock input signal
n.c.
52
−
not connected
VSS5
53
−
GND5 (0 V)
n.c.
54
−
not connected
VDD5
55
−
+5 V supply voltage 5
VRO31
56
O
VRO30
57
O
VRO29
58
O
VRO28
59
O
n.c.
60
−
VRO27
61
O
VRO26
62
O
VRO25
63
O
VRO24
64
O
VSS6
65
−
GND6 (0 V)
n.c.
66
−
not connected
VDD6
67
−
+5 V supply voltage 6
VRO23
68
O
VRO22
69
O
VRO21
70
O
VRO20
71
O
n.c.
72
−
VRO19
73
O
VRO18
74
O
VRO17
75
O
VDD7
76
−
+5 V supply voltage 7
VRO16
77
O
video output; 32-bit VRAM output port (bit16)
VSS7
78
−
GND7 (0 V)
n.c.
79
−
not connected
May 1993
video output; 32-bit VRAM output port (bits 31 to 28)
not connected
video output; 32-bit VRAM output port (bits 27 to 24)
video output; 32-bit VRAM output port (bits 23 to 22)
video output; 32-bit VRAM output port (bits 21 to 20)
not connected
video output; 32-bit VRAM output port (bits 19 to 17)
6
Philips Semiconductors
Preliminary specification
Digital video scaler
SYMBOL
PIN
STATUS
VRO15
80
O
VRO14
81
O
VRO13
82
O
VRO12
83
O
DESCRIPTION
video output; 32-bit VRAM output port (bits 15 to 12)
n.c.
84
−
VRO11
85
O
VRO10
86
O
VRO9
87
O
VRO8
88
O
VSS8
89
O
GND8 (0 V)
n.c.
90
−
not connected
+5 V supply voltage 8
VDD8
91
−
VRO7
92
O
VRO6
93
O
VRO5
94
O
VRO4
95
O
n.c.
96
−
VRO3
97
O
VRO2
98
O
VRO1
99
O
VRO0
100
O
May 1993
SAA7186
not connected
video output; 32-bit VRAM output port (bits 11 to 8)
video output; 32-bit VRAM output port (bits 7 to 4)
not connected
video output; 32-bit VRAM output port (bits 3 to 0)
7
Philips Semiconductors
Preliminary specification
Digital video scaler
LNQ
81 VRO14
82 VRO13
84 n.c.
83 VRO12
85 VRO11
86 VRO10
88 VRO8
87 VRO9
89 VSS8
91 V
DD8
90 n.c.
92 VRO7
94 VRO5
93 VRO6
95 VRO4
96 n.c.
98 VRO2
100 VRO0
handbook, full pagewidth
97 VRO3
Pin configuration
99 VRO1
6.1
SAA7186
80 VRO15
1
79 n.c.
HREFD. 2
VSS1
3
78 VSS7
i.c.
4
77 VRO16
VDD1
5
76 VDD7
i.c.
6
75 VRO17
SP.
7
74 VRO18
AP
8
73 VRO19
n.c.
9
72
UVIN0 10
UVIN1 11
70 VRO21
UVIN2 12
69 VRO22
UVIN3 13
68 VRO23
VDD2
14
67 V
DD6
n.c.
15
VSS2
16
66 n.c.
SAA7186
65 V
SS6
UVIN4 17
64 VRO24
UVIN5 18
63 VRO25
UVIN6 19
62 VRO26
UVIN7 20
61 VRO27
n.c.
21
60
YIN0
22
59 VRO28
YIN1
23
58 VRO29
YIN2
24
57 VRO30
YIN3
25
VDD3
26
n.c.
27
VSS3
28
n.c.
29
YIN4
30
n.c.
56 VRO31
55 V
DD5
54 n.c.
53 VSS5
52 n.c.
8
VOEN 50
49
HFL
INCADR 48
BTST 47
45
IICSA 46
42
VSS4
SCL
41
n.c.
44
40
VDD4
SDA
39
n.c.
RESN 43
38
VS
LLC
n.c.
HREF 37
34
YIN7
36
33
YIN6
CREF 35
31
32
YIN5
51 VCLK
Fig.2 Pin configuration.
May 1993
n.c.
71 VRO20
MEH421
Philips Semiconductors
Preliminary specification
Digital video scaler
7
SAA7186
7.2
FUNCTIONAL DESCRIPTION
The decimation filters perform accurate horizontal filtering
of the input data stream.
Signal characteristics are matched in front of the pixel
decimation stage, thus disturbing artifacts, caused by the
pixel dropping, are reduced. The signal bandwidth can be
reduced in steps of:
The input port is output of Philips digital video
multistandard decoders (SAA7151B, SAA7191B) or other
similar sources.
The SAA7186 input supports the 16-bit YUV 4:2:2 format.
The video data from the input port are converted into a
unique internal two’s complement data stream and are
processed in horizontal direction in two separate
decimation filters. Then they are processed in vertical
direction by the vertical processing unit (VPU).
Chrominance data are interpolated to a 4:4:4 format; a
chroma keying bit is generated.
The 4:4:4 YUV data are then converted from the YUV to
the RGB domain in a digital matrix. ROM tables in the RGB
data path can be used for anti-gamma correction of
gamma-corrected input signals.
Uncorrected RGB and YUV signals can be bypassed.
A scale control unit generates reference and gate signals
for scaling of the processed video data. After data
formatting to the various VRAM port formats, the scaled
video data are buffered in the 16 word × 32-bit output FIFO
register. The FIFO output is directly connected to the
VRAM output bus VRO(31-0). Specific reference signals
support an easy memory interfacing.
All functions of the SAA7186 are controlled via I2C-bus
using 17 subaddresses. The external microcontroller can
get information by reading the status register.
7.1
2-tap filter = −6 dB at 0.325 pixel rate
3-tap filter = −6 dB at 0.25 pixel rate
4-tap filter = −6 dB at 0.21 pixel rate
5-tap filter = −6 dB at 0.125 pixel rate
9-tap filter = −6 dB at 0.075 pixel rate
The different characteristics are chosen dependent on the
defined scaling parameters in an adaptive filter mode
(AFS-bit = 1).
The filter characteristics can also be selected
independently by control bits HF2 to HF0 at AFS-bit = 0.
7.3
Vertical filters
Y and UV data are handled in separate filters (Fig.1). Each
of the two line memories has a capacity of 2 × 768 × 8-bit.
Thus two complete video lines of 4:2:2 YUV data can be
stored. The VPU is split into two memory banks and one
arithmetic unit. The available processing modes,
respectively transfer functions, are selectable by the bits
VP1 and VP0 if AFS = 0.
An adaptive mode is selected by AFS = 1. Disturbing
artifacts, generated by line dropping, are reduced.
Video input port
The 16-bit YUV input data in 4:2:2 format (Table 1) consist
of 8-bit luminance data Y (pins YIN(7-0)) and 8-bit
time-multiplexed colour-difference data UV (pins
UVIN(7-0)).
The input data are clocked in by the signals LLC and
CREF (Fig.3). HREF and VS inputs define the video scan
pattern (window).
Adaptive filter selection (AFS = 1):
SCALING RATIO
Sequential input data
• are limited to maximum 768 active pixels per line if the
vertical filter is active
• UV can be processed in straight binary and two’s
complement representation (controlled by TCC)
May 1993
Decimation filters
9
FILTER FUNCTION
(REFER TO I2C SECTION)
XD/XS
horizontal
≤1
≤14/15
≤11/15
≤7/15
≤3/15
bypassed
filter 1
filter 6
filter 3
filter 4
YD/YS
vertical
≤1
≤13/15
≤4/15
bypassed
filter 1
filter 2
Philips Semiconductors
Preliminary specification
Digital video scaler
7.4
SAA7186
RGB matrix
7.5
The keyer generates an alpha signal to achieve a 5-5-5 +α
RGB alpha output signal. Therefore, the processed UV
data amplitudes are compared with thresholds set via
I2C-bus (subaddresses ”0C to 0F”). A logical “1” signal is
generated if the amplitude is inside the specified amplitude
range, otherwise a logical “0” is generated.
Keying can be switched off by setting the lower limit higher
than the upper limit (“0C or 0E” and “0D or 0F”).
Y data and UV data are converted after interpolation into
RGB data according to CCIR601 recommendation. Data
are bypassed in YUV or monochrome modes.
Table 1
4 : 2 : 2 format (pixels per line). The time frames
are controlled by the HREF signal.
INPUT
PIXEL BYTE SEQUENCE
YIN7
YIN6
YIN5
YIN4
YIN3
YIN2
YIN1
YIN0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
UVIN7
UVIN6
UVIN5
UVIN4
UVIN3
UVIN2
UVIN1
UVIN0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Y frame
0
1
2
3
UV frame
0
2
Chrominance signal keyer
7.6
Scale control and vertical regions
The scale control block SC includes vertical
address/sequence counters to define the current position
in the input field and to address the internal VPU
memories.
To perform scaling, XD of XS pixel selection in horizontal
direction and YD of YS line selection in vertical direction
are applied. The pixel and line dropping are controlled at
the input of the FIFO register. To control the decimation
filter function and the vertical data processing in the
adaptive mode (AFS = 1), the scaling ratio in horizontal
and vertical direction is estimated in the SC block.
The input field can be divided into two vertical regions
− the bypass region and the scaling region, which are
defined via I2C-bus by the parameters VS, VC, YO and
YS.
4
4
Vertical bypass region:
Note
Data are not scaled and independent of I2C-bits FS1, FS0
the output format is always 8-bit greyscale (monochrome).
The SAA7186 outputs all active pixels of a line, defined by
the HREF input signal if the vertical bypass region is
active. This can be used, for example, to store videotext
information in the field memory.
1. e = even pixel; o = odd pixel
The matrix equations are these considering the digital
quantization:
R = Y + 1.375 V
The start line of the bypass region is defined by VS; the
number of lines to be bypassed is defined by VC.
G = Y − 0.703125 V − 0.34375 U
B = Y + 1.734375 U.
Vertical scaling region:
Anti-gamma ROM tables:
ROM tables are implemented at the matrix output to
provide anti-gamma correction of the RGB data. A curve
for a gamma of 1.4 is implemented
Data is scaled with start at line YO and the output format
is selected when FS1, FS0 are valid.
This is the “normal operation” area.
The input/output screen dimensions in horizontal and
vertical direction are defined by the parameters
The tables can be used (RTB-bit = 0) to compensate
gamma correction for linear data representation of RGB
output data.
XO, XS and XD for horizontal
YO, YS and YD for vertical.
The circuit processes XS samples of a line. Remaining
pixels are ignored if a line is longer than XS. If a line is
May 1993
10
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
• the offsets XO and YO have to be set according to the
internal processing delays to ensure the complete
number of destination pixels and lines (Table 6).
shorter than XS, processing is aborted when the falling
edge of HREF is detected.
Vertical regions in Fig.4:
• the scaling parameters can be used to perform a
panning function over the video frame/field.
• the two regions can be programmed via I2C-bus,
whereby regions should not overlap (active region
overrides the bypass region).
• the start of a normal active picture depends on video
standard and has to be programmed to the correct
value.
handbook, full pagewidth
LLC
CREF
HREF
start of
active line
Byte numbers for pixles:
Y signal
U and V signal
0
1
2
3
4
5
6
7
U0
V0
U2
V2
U4
V4
U6
V6
MEH411
handbook, full pagewidth
LLC
CREF
HREF
end of
active line
Byte number for pixels:
Y signal
n–5
n–4
n–3
n–2
n–1
n
U and V signal
Un-5
Vn-5
Un-3
Vn-3
Un-1
Vn-1
MEH410
Fig.3 Horizontal and data multiplex timing.
May 1993
11
Philips Semiconductors
Preliminary specification
Digital video scaler
7.7
SAA7186
The signal levels of the RGB formats are limited in 8-bit to
“0” or “255”. For the 5-bit RGB formats a truncation from
8-bit to 5-bit is implemented.
Output data representation and levels
Output data representation of the YUV data can be
modified by bit MCT (subaddress 10).
The DC gain is 1 for YUV input data. The corresponding
RGB levels are defined by the matrix equations. The
luminance levels are limited according to CCIR 601
Fill values are inserted dependent on longword position
and destination size:
• “0”
handbook, full pagewidth
vertical sync
in RGB formats and for Y two’s complement U, V
• “128” for U, V (straight binary)
16 (239) = black
235 (20) = white
(..) = greyscale luminance levels
if the YUV or monochrome luminance output formats are
selected.
• “255” in 8-bit greyscale format
The unused output values of the YUV and greyscale
formats can be used for other purposes.
vertical
blanking
VS
first valid line
YO
vertical bypass start
bypass region
vertical bypass count
equals VS
scaling region
scaling region count
equals YS Y-size source
scaling region start
MEH357-1
Fig.4 Vertical regions.
May 1993
12
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 2
SAA7186
VRAM port output data formats at EFE-bit = 0 dependent on FS1 and FS0 bits (set via I2C-bus)
PIXEL
OUTPUT
BITS
FS1 = 0; FS0 = 0
RGB 5-5-5 + 1
32-BIT WORDS
FS1 = 0; FS0 = 1
YUV 4:2:2
32-BIT WORDS
FS1 = 1; FS0 = 0
YUV 4:2:2 TEST
16-BIT WORDS
FS1 = 1; FS0 = 1
8-BIT MONOCHROME
32-BIT WORDS
PIXEL
ORDER
n
n+2
n+4
n
n+2
n+4
n
n+1
n+2
n
n+1
n+4
n+5
n+8
n+9
VRO31
VRO30
VRO29
VRO28
α
R4
R3
R2
α
R4
R3
R2
α
R4
R3
R2
Ye7
Ye6
Ye5
Ye4
Ye7
Ye6
Ye5
Ye4
Ye7
Ye6
Ye5
Ye4
Ye7
Ye6
Ye5
Ye4
Yo7
Yo6
Yo5
Yo4
Ye7
Ye6
Ye5
Ye4
Ya7
Ya6
Ya5
Ya4
Ya7
Ya6
Ya5
Ya4
Ya7
Ya6
Ya5
Ya4
VRO27
VRO26
VRO25
VRO24
R1
R0
G4
G3
R1
R0
G4
G3
R1
R0
G4
G3
Ye3
Ye2
Ye1
Ye0
Ye3
Ye2
Ye1
Ye0
Ye3
Ye2
Ye1
Ye0
Ye3
Ye2
Ye1
Ye0
Yo3
Yo2
Yo1
Yo0
Ye3
Ye2
Ye1
Ye0
Ya3
Ya2
Ya1
Ya0
Ya3
Ya2
Ya1
Ya0
Ya3
Ya2
Ya1
Ya0
VRO23
VRO22
VRO21
VRO20
G2
G1
G0
B4
G2
G1
G0
B4
G2
G1
G0
B4
Ue7
Ue6
Ue5
Ue4
Ue7
Ue6
Ue5
Ue4
Ue7
Ue6
Ue5
Ue4
Ue7
Ue6
Ue5
Ue4
Ve7
Ve6
Ve5
Ve4
Ue7
Ue6
Ue5
Ue4
Yb7
Yb6
Yb5
Yb4
Yb7
Yb6
Yb5
Yb4
Yb7
Yb6
Yb5
Yb4
VRO19
VRO18
VRO17
VRO16
B3
B2
B1
B0
B3
B2
B1
B0
B3
B2
B1
B0
Ue3
Ue2
Ue1
Ue0
Ue3
Ue2
Ue1
Ue0
Ue3
Ue2
Ue1
Ue0
Ue3
Ue2
Ue1
Ue0
Ve3
Ve2
Ve1
Ve0
Ue3
Ue2
Ue1
Ue0
Yb3
Yb2
Yb1
Yb0
Yb3
Yb2
Yb1
Yb0
Yb3
Yb2
Yb1
Yb0
PIXEL
ORDER
n+1
n+3
n+5
n+1
n+3
n+5
OUTPUTS NOT USED
n+2
n+3
n+6
n+7
n+10
n+11
VRO15
VRO14
VRO13
VRO12
α
R4
R3
R2
α
R4
R3
R2
α
R4
R3
R2
Yo7
Yo6
Yo5
Yo4
Yo7
Yo6
Yo5
Yo4
Yo7
Yo6
Yo5
Yo4
X
X
X
X
X
X
X
X
X
X
X
X
Yc7
Yc6
Yc5
Yc4
Yc7
Yc6
Yc5
Yc4
Yc7
Yc6
Yc5
Yc4
VRO11
VRO10
VRO9
VRO8
R1
R0
G4
G3
R1
R0
G4
G3
R1
R0
G4
G3
Yo3
Yo2
Yo1
Yo0
Yo3
Yo2
Yo1
Yo0
Yo3
Yo2
Yo1
Yo0
X
X
X
X
X
X
X
X
X
X
X
X
Yc3
Yc2
Yc1
Yc0
Yc3
Yc2
Yc1
Yc0
Yc3
Yc2
Yc1
Yc0
VRO7
VRO6
VRO5
VRO4
G2
G1
G0
B4
G2
G1
G0
B4
G2
G1
G0
B4
Ve7
Ve6
Ve5
Ve4
Ve7
Ve6
Ve5
Ve4
Ve7
Ve6
Ve5
Ve4
X
X
X
X
X
X
X
X
X
X
X
X
Yd7
Yd6
Yd5
Yd4
Yd7
Yd6
Yd5
Yd4
Yd7
Yd6
Yd5
Yd4
VRO3
VRO2
VRO1
VRO0
B3
B2
B1
B0
B3
B2
B1
B0
B3
B2
B1
B0
Ve3
Ve2
Ve1
Ve0
Ve3
Ve2
Ve1
Ve0
Ve3
Ve2
Ve1
Ve0
X
X
X
X
X
X
X
X
X
X
X
X
Yd3
Yd2
Yd1
Yd0
Yd3
Yd2
Yd1
Yd0
Yd3
Yd2
Yd1
Yd0
Note
1. α = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number;
a b c d = consecutive pixels
May 1993
13
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 3
SAA7186
VRAM port output data formats at EFE-bit = 1 dependent on FS1 and FS0 bits (set via I2C-bus)
PIXEL
OUTPUT
BITS
FS1 = 0; FS0 = 0
RGB 5-5-5 + 1
16-BIT WORDS
FS1 = 0; FS0 = 1
YUV 4:2:2
16-BIT WORDS
FS1 = 1; FS0 = 0
RGB 8-8-8
24-BIT WORDS
FS1 = 1; FS0 = 1
8-BIT MONOCHROME
16-BIT WORDS
PIXEL
ORDER
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n+3
n+4
n+5
VRO31
VRO30
VRO29
VRO28
α
R4
R3
R2
α
R4
R3
R2
α
R4
R3
R2
Ye7
Ye6
Ye5
Ye4
Yo7
Yo6
Yo5
Yo4
Ye7
Ye6
Ye5
Ye4
R7
R6
R5
R4
R7
R6
R5
R4
R7
R6
R5
R4
Ya7
Ya6
Ya5
Ya4
Ya7
Ya6
Ya5
Ya4
Ya7
Ya6
Ya5
Ya4
VRO27
VRO26
VRO25
VRO24
R1
R0
G4
G3
R1
R0
G4
G3
R1
R0
G4
G3
Ye3
Ye2
Ye1
Ye0
Yo3
Yo2
Yo1
Yo0
Ye3
Ye2
Ye1
Ye0
R3
R2
R1
R0
R3
R2
R1
R0
R3
R2
R1
R0
Ya3
Ya2
Ya1
Ya0
Ya3
Ya2
Ya1
Ya0
Ya3
Ya2
Ya1
Ya0
VRO23
VRO22
VRO21
VRO20
G2
G1
G0
B4
G2
G1
G0
B4
G2
G1
G0
B4
Ue7
Ue6
Ue5
Ue4
Ve7
Ve6
Ve5
Ve4
Ue7
Ue6
Ue5
Ue4
G7
G6
G5
G4
G7
G6
G5
G4
G7
G6
G5
G4
Yb7
Yb6
Yb5
Yb4
Yb7
Yb6
Yb5
Yb4
Yb7
Yb6
Yb5
Yb4
VRO19
VRO18
VRO17
VRO16
B3
B2
B1
B0
B3
B2
B1
B0
B3
B2
B1
B0
Ue3
Ue2
Ue1
Ue0
Ve3
Ve2
Ve1
Ve0
Ue3
Ue2
Ue1
Ue0
G3
G2
G1
G0
G3
G2
G1
G0
G3
G2
G1
G0
Yb3
Yb2
Yb1
Yb0
Yb3
Yb2
Yb1
Yb0
Yb3
Yb2
Yb1
Yb0
PIXEL
ORDER
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n+3
n+4
n+5
VRO15
VRO14
VRO13
VRO12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B7
B6
B5
B4
B7
B6
B5
B4
B7
B6
B5
B4
X
X
X
X
X
X
X
X
X
X
X
X
VRO11
VRO10
VRO9
VRO8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B3
B2
B1
B0
B3
B2
B1
B0
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
VRO7 (2, 3)
VRO6 (3)
VRO5 (3)
VRO4 (3)
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
X
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
α
O/E
VGT
HGT
VRO3
VRO2 (3)
VRO1 (3)
VRO0 (3)
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
Notes
1. α = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number;
a b c d = consecutive pixels; O/E = odd/even flag
2. YUV 16-bit format: the keying signal α is defined only for YU time steps. The corresponding YV sample has also to
be keyed. The α signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case
Ya = Yb.
3. Data valid only when transparent mode active (TTR-bit = 1) and VCLK pin connected to LLC/2 clock rate.
May 1993
14
Philips Semiconductors
Preliminary specification
Digital video scaler
7.8
SAA7186
combination with INCADR to indicate the line
increments (Figures 6 and 7).
Output FIFO register and VRAM output port
The output FIFO register is the buffer between the video
data stream and the VRAM data input port. Resized video
data are buffered and formatted. 32-, 24- and 16-bit video
data modes are supported. The various formats are
selected by the bits EFE, FS1 and FS0. VRAM port
formats are shown in Tables 2 and 3. The FIFO register
capacity is 16 word × 32 bit (for 32-, 24-, or 16-bit video
data). The bits LW1 and LW0 can be used to define the
position of the first pixel each line in the 32-bit longword
formats or to shift the UV sequence to VU in the 16-bit YUV
formats (LW1 = 1).
• INCADR output signal is used in combination with HFL
to control horizontal and vertical address generation for
a memory controller. The pulse sequence depends on
field formats (interlace/ non-interlace or odd/even fields,
Figures 6 and 7) and control bits OF (subaddress 00).
HFL = 1 at the rising edge of INCADR:
the end of line is reached, request for line address
increment
HFL = 0 at the rising edge of INCADR:
the end of field/frame is reached, request for line and
pixel addresses reset
VRAM port inputs are:
VCLK to clock the FIFO register output data and VOEN to
enable output data.
(The distance from the last half-full request HFL to the
INCADR pulse may be longer than 64 × LLC. The HFL
state is defined for minimum 4 × LLC in front of the rising
edge of INCADR and minimum 2 × LLC afterwards.)
VRAM port outputs are:
the HFL flag (half-full flag), the signal INCADR (refer to
section “data burst transfer”) and the reference signals for
pixel and line selection on outputs VRO(7-0) (only for 24and 16-bit video data formats refer to “transparent data
transfer”).
7.9
• VCLK input signal to clock the FIFO register output data
VRO(n). New data are placed on the VRO(n) port with
the rising edge of VCLK (Fig.5).
• VOEN input enables output data VRO(n). The outputs
are in 3-state mode at VOEN = HIGH. VOEN changes
only when VCLK is LOW. If VCLK pulses are applied
during VOEN = HIGH, the outputs remain inactive, but
the FIFO register accepts the pulses.
VRAM port transfer procedures
Data transfer on the VRAM port can be done
asynchronously controlled by outputs HFL, INCADR and
input VCLK (data burst transfer with bit TTR = 0).
7.11
Data transfer on the VRAM port can be done
synchronously controlled by output reference signals on
outputs VRO(7-0) and a clock rate of LLC/2 on input VCLK
(transparent data transfer with bit TTR = 1 and EFE = 1).
The scaling capability of the SAA7186 can be used in
various applications.
7.10
Data transfer on the VRAM port can be achieved
synchronously (TTR = 1). With a continuous clock rate of
LLC/2 on input VCLK, the SAA7186 delivers a
continuously processed data stream. Therefore, the
extended formats of the VRAM output port have to be
selected (bit EFE = 1; Table 3). The reference and gate
signals on outputs VRO(6-1) and the LNQ signal are
delivered in each field (means scaled and ignored fields).
The PXO signal (also VRO0) is only delivered in active
fields. The output signals VRO(7-0) can be used to buffer
qualified pre-processed RGB or YUV video data (notice:
the YUV data are only valid in qualified time slots). Control
output signals in Table 3 are:
Data burst transfer mode
Data transfer on the VRAM port is asynchronously
(TTR = 0). This mode can be used for all output formats.
Four signals for communication with the external memory
are provided.
• HFL flag, the half-full flag of the FIFO output register is
raised when the FIFO contains at least 8 data words
(HFL = HIGH). By setting HFL = 1, the SAA7186
requests a data burst transfer by the external memory
controller, that has to start a transfer cycle within the
next 32 LLC cycles for 32-bit longword modes (16 LLC
cycles for 16- and 24-bit modes). If there are pixels in the
FIFO at the end of a line, which are not transferred, the
circuit fills up the FIFO register with “fill pixels” until it is
half-full and sets the HFL flag to request a data burst
transfer. After transfer is done, HFL is used in
May 1993
Transparent data transfer mode
15
Philips Semiconductors
Preliminary specification
Digital video scaler
α
keying signal of the chroma keyer
O/E
odd/even field bit according
to the internal field processing
VGT
vertical gate signal, “1”
marks the scaling window in vertical direction
from YO to (YO + YS) lines, cut by VS.
SAA7186
HGT horizontal gate signal, “1”
marks horizontal direction from XO to (XO + XS)
lines, cut by HREF.
HRF
delay compensated
horizontal reference signal.
LNQ
line qualifier signal, active polarity is defined by
QPL bit.
PXQ pixel qualifier signal, active polarity is defined by
QPP bit.
7.12
Power-on reset
• the FIFO register contents are undefined
• outputs VRO are set to high-impedance state
• output INCADR = HIGH
• output HFL = LOW until the VPE bit is set to “1”
• subaddress “10” is set to 00h and VPE-bit in subaddress
“00” is set to zero (Table 4).
May 1993
16
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
PIXCLK
(LLC/2)
FIFO memory
filling level
6
7
8
7
7
6
5
5
4
3
4
5
6
3
HFL
min. 8 samples
available in FIFO
max. 32LLC
(16 PIXCLK
VCLK
1 transfer cycle
(8 VCLK cycles)
VOEN
VRO(n)
7
1
0
2
3
7
MEH407
Fig.5
Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOEN = HIGH,
the FIFO register is unchanged, but the outputs VRO(31-0) remain in 3-state position.
handbook, full pagewidth
internal
signal
line n
line n+1
active
video
vertical blanking
last half-full request for line n
(1)
HFL
64LLC
INCADR
(1) pulse only at
interlace scan
min.
64LLC
min. set-up time
(1)
10LLC
line increment (VRAM) only in odd field
vertical reset
Fig.6 Vertical reset timing to the VRAM.
May 1993
17
MEH406
Philips Semiconductors
Preliminary specification
Digital video scaler
handbook, full pagewidth
internal
signal
line n
SAA7186
line n+1
active
video
horizontal blanking
active
video
first half-full request for line n+1
last half-full request for line n
(1)
HFL
6LLC
6LLC
INCADR
(1) pulse only at
interlace scan
min.
64LLC
min. set-up time
(1)
64LLC
2LLC
10LLC
line increment (VRAM)
Fig.7 Horizontal increment timing to the VRAM.
Fig.8 Reference signals for scaling window.
May 1993
18
MEH405-1
Philips Semiconductors
Preliminary specification
Digital video scaler
7.13
SAA7186
Field processing
8
The phase of the field sequence (odd/even dependent on
inputs HREF and VS) is detected by means of the falling
edge of VS. The current field phase is reported in the
status byte by the OEF bit (Table 5). OEF bit can be stable
0 or 1 for non-interlaced input frames or non standard input
signals VS and/or HREF (nominal condition for VS and
HREF − SAA7191 B with active vertical noise limiter). A
free-running odd/even flag is generated for internal field
processing if the detection reports a stable OEF bit.
The operation is synchronized by the input field. The cycle
is specified in the flow chart (Fig.9).
The circuit is inactive after power-on reset, VPO is 0 and
the FIFO control is set “empty”. The internal control
registers are updated with the falling edge of VS signal.
The circuit is switched active and waits for a transmission
of VS and a vertical reset sequence to the memory
controller. Afterwards, the circuit waits for the beginning of
a scaling or bypass region. The processing of a current line
is finished when a vertical sync pulse appears. The circuit
performs a coefficient update and generates a new vertical
reset (if it is still active).
The POE bit (subaddress 0B) can be used to change the
polarity of the internal flag (in case of non-standard VS and
HREF signals) to control the phase of the free-running flag,
and to compensate mis-detections. Thus, the SAA7186
can be used under various VS/HREF timing conditions.
Line processing starts when a line is decided to be active,
the circuit starts to scale it. Active pixels are loaded into the
FIFO register. An HFL flag is generated to initialize a data
transfer when eight words are completed. The line end is
reached when the programmed pixel number is processed
or when a horizontal sync pulse occurs. If there are pixels
in the FIFO register, it is filled up until it is half-full to cause
a data transfer. Horizontal increment pulses are
transmitted after this data transfer.
The SAA7186 operates on fields. To support progressive
displays and to avoid movement blurring and artifacts, the
circuit can process both or single fields of interlaced or
non-interlaced input data. Therefore the OF bits can be
used. The bits OF1 and OF0 (Table 6) determine the
INCADR/HFL generation in “data burst transfer mode”.
One of the fields (odd or even) is ignored when OF1 = 1;
then no line increment sequence (INCADR/HFL) is
generated, the vertical reset pulse is only generated.
Remarks:
The SAA7186 will always wait for the HREF/VS pulse
before the line increment/vertical reset sequence is
performed. After each line/field, the FIFO control is set to
empty when INCADR/HFL sequence is transmitted.
No additional actions are necessary if the memory
controller has ignored the HFL signal. There is no need to
handle overflow/underflow of the FIFO register.
With OF1 = OF0 = 0 the circuit supports correct interlaced
data storage. Two INCADR/HFL sequences are generated
in each qualified line; additionally an INCADR/HFL
sequence after the vertical reset sequence of an odd field
is generated. Thereby, the scaled lines are automatically
stored in the right sequence.
May 1993
OPERATION CYCLE
19
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
EXTERNAL RESET, VPE = 0
VERTICAL SYNC
DETECTED ?
NO
YES
COEFFICIENT UPDATE
VPE = 1 ?
NO
YES
DO VERTICAL RESET
YES
VERTICAL SYNC
DETECTED ?
NO
YES
CURRENT
LINE IN ACTIVE
REGION ?
NO
CURRENT
LINE IN BYPASS
REGION ?
NO
YES
SET SCALING ACTIVE
IN CONTROL STAGE
SET BYPASS MODE
IN CONTROL STAGE
PROCESS A LINE
MGL119
Fig.9 Operation cycle
May 1993
20
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
RGB/YUV
ADC
digital
DMSD
YUV
format 4.2:2
DVS
RAM
TDA8708A
CVBS
SAA7151B/91B
HREF / VS
SAA7186
VIDEO
GRAPHICS
CVBS
LLC / CREF
display data
control
HFL
INCADR
LFCO
address
VCLK
VOEN
SCGC
SAA7157/97
MEMORY
CONTROLLER
system
clock
BUFFER
data bus
CPU
SYSTEM
RAM
address / control bus
MEH554
Fig.10 SAA7186 system configuration in Data Burst Transfer Mode (TTR = , VCLK = continuous).
handbook, full pagewidth
CVBS
RGB/YUV
YUV
format 4.2:2
ADC
digital
DMSD
TDA8708A
CVBS
SAA7151B/91B
(VRO(31-8))
DVS
HREF / VS
qualifier
and
SAA7186 references
(VRO(7-0))
VIDEO
GRAPHICS
LLC / CREF
write
LFCO
display
data
RAM
FIFO
BUFFER
read
control
address
VOEN = 1
SCGC
SAA7157/97
LLC2
INV
VCLK = LLC2
MEMORY
CONTROLLER
MEH555
Fig.11 SAA7186 system configuration in Transparent Data Transfer Mode (TTR = 1, EFE = 1,
VCLK = continuous (_LLC2)).
May 1993
21
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
(a) 1st field
625
1
2
3
4
5
6
7
8
9
input CVBS
HREF
541 x 2/LLC
VS
313
(b) 2nd field
314
315
316
317
318
319
320
321
input CVBS
HREF
69 x 2/LLC
VS
50 Hz
handbook, full pagewidth
(a) 1st field
525
1
2
3
MEH412
4
5
6
7
8
9
input CVBS
HREF
449x 2/LLC
VS
ODD
(b) 2nd field
2 x 2/LLC
263
264
265
266
267
268
269
270
271
input CVBS
HREF
59 x 2/LLC
VS
2 x 2/LLC
ODD
60 Hz
Fig.12 VS timing for video input source SAA7191B.
May 1993
22
MEH225-1
Philips Semiconductors
Preliminary specification
Digital video scaler
9
SAA7186
I2C-BUS FORMAT
S
SLAVE ADDRESS
S
=
A
SUBADDRESS
A
DATA0
A
DATAn
start condition
SLAVE ADDRESS
=
1011 100X (IICSA = LOW) or 1011 110X (IICSA = HIGH)
A
=
acknowledge, generated by the slave
SUBADDRESS(1)
=
subaddress byte (Table 4)
DATA
=
data byte (Table 4)
P
=
stop condition
X
=
read/write control bit
X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)
Note
1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
May 1993
23
A
P
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
I2C-bus; subaddress and data bytes for writing (X in address byte = 0).
Table 4
DATA
FUNCTION
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Formats and sequence
00
RTB
OF1
OF0
VPE
LW1
LW0
FS1
FS0
Output data pixel/line
01
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
XD9
XD8
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
XS9
XS8
continued in
04
Input data pixel/line
02
continued in
04
Horizontal window start
03
XO7
XO6
XO5
XO4
XO3
XO2
XO1
XO0
Pixel decimation filter
04
HF2
HF1
HF0
XO8
XS9
XS8
XD9
XD8
Output data lines/field
05
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
YD9
YD8
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
YS9
YS8
continued in
Input data lines/field
continued in
09
06
09
Vertical window start
07
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
AFS/vertical processing
08
AFS
VP1
VP0
YO8
YS9
YS8
YD9
YD8
Vertical bypass start
09
VS7
VS6
VS5
VS4
VS3
VS2
VS1
VS0
continued in
Vertical bypass count
0B
VS8
0A
VC7
VC6
VC5
VC4
VC3
VC2
VC1
VC0
0B
TCC
0
0
VS8
0
VC8
0
POE
0C
0D
0E
0F
VL7
VU7
UL7
UU7
VL6
VU6
UL6
UU6
VL5
VU5
UL5
UU5
VL4
VU4
UL4
UU4
VL3
VU3
UL3
UU3
VL2
VU2
UL2
UU2
VL1
VU1
UL1
UU1
VL0
VU0
UL0
UU0
Byte 10(2)
10
0
0
0
MCT
QPL
QPP
TTR
EFE
Unused
11 to 1F
continued in
Chroma keying
lower limit for V
upper limit for V
lower limit for U
upper limit for U
Notes
1. Default register contents fill in by hand
2. Byte 10 is set to 00h after power-on reset.
May 1993
24
DF(1)
tbf
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 5
SAA7186
I2C-bus status byte (X in address byte = 1)
DATA
FUNCTION
status byte
D7
D6
D5
D4
D3
D2
D1
D0
ID3
ID2
ID1
ID0
0
0
OEF
SVP
Function of status bits:
ID3
to
ID0
Software version of SAA7186 compatible with
ID3
ID2
ID1
ID0
version
0
0
0
1
1
OEF
Identification of field sequence dependent on inputs HREF and VS:
0 = even field detected; 1 = odd field detected
SVP
State of VRAM port:
May 1993
0 = inputs HFL and INCADR inactive;
1 = inputs HFL and INCADR active.
25
Philips Semiconductors
Preliminary specification
Digital video scaler
Table 6
SAA7186
Function of the register bits of Table 4
“00”
RTB
ROM table bypass switch:
0 = anti-gamma ROM active
1 = table is bypassed
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅
OF1
to
OF0
Set output field mode:
OF1
0
0
1
1
OF0
field mode DVS process
0
1
0
1
both fields for interlaced storage
both fields for non-interlaced storage
odd fields only (even fields ignored) for non-interlaced storage
even fields only (odd fields ignored) for non-interlaced storage
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅
VPE
VRAM port outputs enable:
0 = HFL and INCADR inactive; VRO outputs in 3-state
position (HFL = LOW, INCADR = HIGH)
1 = HFL and INCADR enabled; VRO outputs dependent
on VOEN
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅
LW1
to
LW0
First pixel position in VRO data for FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV):
LW1
LW0
31 to 24
23 to 16
15 to 8
7 to 0
0
0
1
1
0
1
0
1
pixel 0
pixel 0
black
black
pixel 0
pixel 0
black
black
pixel 1
pixel 1
pixel 0
pixel 0
pixel 1
pixel 1
pixel 0
pixel 0
)
) EFE = 0, TRR = 0
)
)
First pixel position in VRO data for FS1 = 1; FS0 = 1 (monochrome):
May 1993
LW1
LW0
31 to 24
23 to 16
15 to 8
7 to 0
0
0
1
1
0
1
0
1
pixel 0
black
black
black
pixel 1
pixel 0
black
black
pixel 2
pixel 1
pixel 0
black
pixel 3
pixel 2
pixel 1
pixel 0
)
) EFE = 0, TRR = 0
)
)
0
0
1
1
0
1
0
1
pixel 0
black
pixel 0
black
pixel 1
pixel 0
pixel 1
pixel 0
X
X
X
X
X
X
X
X
) EFE = 1, TRR = 0;
) LW only effects
) greyscale format
)
26
Philips Semiconductors
Preliminary specification
Digital video scaler
FS1
to
FS0
SAA7186
FIFO output register format select (EFE-bit see “10”):
EFE
FS1 FS0
output format (Tables 2 and 3)
0
0
0
RGB 5-5-5 + alpa; 2×16-bit/pixel; 32-bit word length;
RGB matrix on, VRAM output format
0
0
1
YUV 4:2:2; 2×16-bit/pixel; 32-bit word length;
RGB matrix off, VRAM output format
0
1
0
YUV 4:2:2; video test mode; 1×16-bit/pixel; 16-bit word length;
RGB matrix off, optional output format
0
1
1
monochrome mode; 4×8-bit/pixel; 32-bit word length;
RGB matrix off, VRAM output format
1
0
0
RGB 5-5-5 + alpa; 1×16-bit/pixel; 16-bit word length;
RGB matrix on, VRAM output + transparent format
1
0
1
YUV 4:2:2 + alpa; 1×16-bit/pixel; 16-bit word length;
RGB matrix off, VRAM output + transparent format
1
1
0
RGB 8-8-8 + alpa; 1×24-bit/pixel; 24-bit word length;
RGB matrix on, VRAM output + transparent format
1
1
1
monochrome mode; 2×8-bit/pixel; 16-bit word length;
RGB matrix off, VRAM output + transparent format
“01 and 04”
XD9
to
XD0
Pixel number per line (straight binary) on output (VRO):
00 0000 0000 to 11 1111 1111 (number of XS pixels as a maximum)
to
XS0
Pixel number per line (straight binary) on inputs (YIN and UVIN):
00 0000 0000 to 11 1111 1111 (number of input pixels per line as maximum)
to
XO0
Horizontal start position (straight binary) of scaling window (take care of active pixel
number per line).
start with 1st pixel after HREF rise = 0 0001 0000 to 1 1111 1111 (010 to 1FF)
“02 and 04”
XS9
“03 and 04”
XO8
window start and window end may be cut by internal delay compensated HREF = 0
phase. XO has to be matched to the internal processing delay to get full scaling range
May 1993
27
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
“04”
HF2
to
HF0
Horizontal decimation filter (Figures 13 and 14):
HF2 HF1
HF0
taps filter
0
0
0
0
0
0
1
1
0
1
0
1
2
3
5
9
filter 1 (1/2 (1 + z−1))
filter 2 (1/4 (1 + 2z−1 + z−2))
filter 3 (1/8 (1 + 2z−1 + 2z−2 + 2z−3 + z−4))
filter 4 (1/16 (1 + 2z−1 + 2z−2 + 2z−3 + 2z−4 + 2z−5
+ 2z−6 + 2z−7 + z−8))
1
1
1
0
0
1
0
1
0
1
1
8
filter bypassed
filter bypassed + delay in Y channel of 1T
filter 5 (1/16 (1 + 3z−1 + 3z−2 + z−3 + z−4 + 3z−5
+ 3z−6 + z−7))
1
1
1
4
(1/8 (1 + 3z−1 + 3z−2 + z−3))
“05 and 08”
YD9
to
YD0
Line number per output field (straight binary):
00 0000 0000 to 11 1111 1111 (number of YS lines as a maximum)
to
YS0
Line number per input field (straight binary):
“06 and 08”
YS9
00 0000 0000
11 1111 1111
0 line
1023 lines (maximum = number of lines/field − 3)
“07 and 08”
YO8
to
YO0
“08”
AFS
Vertical start of scaling window. “0” equals 3rd line after rising slope of VS input signal.
Take care of active line number per field (straight binary).
0 0000 0000 start with 3rd line after the rising slope of VS
0 0000 0011 start with 1st line after the falling slope of nominal VS (SAA7151B/91B)
1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value)
Adaptive filter switch:
0 = off; use VP1, VP0 and HF2 to HF0 bits
1 = on; filter characteristics are selected by the scaler
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅
VP1
to
VP0
Vertical data processing
VP1 VP0
0
0
1
1
0
1
0
1
processing
bypassed
delay of one line H(z) = z−H
vertical filter 1: (H(z) = 1/2 (1 + z−H))
vertical filter 2: (H(z) = 1/4 (1 + 2z−H + z−2H))
“09 and 0B”
VS8
to
VS0
Vertical bypass start, sets begin of the bypass region (straight binary). Scaling region
overrides bypass region (YO bits):
0 0000 0000 start with 3rd line after the rising slope of VS
0 0000 0011 start with 1st line after the falling slope of nominal VS (SAA7151B/91B)
1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value)
May 1993
28
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
“0A and 0B”
VC8
to
VC0
Vertical bypass count, sets length of bypass region (straight binary):
00 0000 0000
11 1111 1111
0 line length
511 lines length (maximum = number of lines/field − 3)
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−
TCC
Two’s complement input data select (U, V):
0 = binary input data
1 = two’s complement input data
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−
POE
Polarity, internally detected odd/even flag O/E:
0 = flag unchanged;
1 = flag inverted
“0C”
VL7
to
VL0
Set lower limit for V colour-difference signal (8 bit; two’s complement):
1000 0000
0000 0000
0111 1111
as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level
“0D”
VU7
to
VU0
Set upper limit for V colour-difference signal (8 bit; two’s complement):
1000 0000
0000 0000
0111 1111
as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level
“0E”
UL7
to
UL0
Set lower limit for U colour-difference signal (8 bit; two’s complement):
1000 0000
0000 0000
0111 1111
as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level
“0F”
UU7
to
UU0
Set upper limit for U colour-difference signal (8 bit; two’s complement):
1000 0000
0000 0000
0111 1111
May 1993
as maximum negative value = −128 signal level
limit = 0
as maximum positive value = +127 signal level
29
Philips Semiconductors
Preliminary specification
Digital video scaler
“10”
MCT
SAA7186
Monochrome and two’s complement output data select:
0 = inverse greyscale luminance (if greyscale is selected by FS bits) or straight
binary U, V data output
1 = non-inverse monochrome luminance (if greyscale is selected by FS bits) or
two’s complement U, V data output
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−
QPL
Line qualifier polarity flag :
0 = LNQ is active-LOW (pin 1 and on VRO1, pin 99);
1 = LNQ is active-HIGH
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−
QPP
Pixel qualifier polarity flag :
0 = PXQ is active-LOW (VRO0, pin 100);
1 = PXQ is active-HIGH
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−
TTR
Transparent data transfer:
0 = normal operation (VRAM protocol valid,)
1 = FIFO register transparent
(output FIFO in shift register mode)
−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−
EFE
May 1993
Extended formats enable, FS-bits in subaddress “00”
30
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
MEH514
10
handbook, full pagewidth
(dB)
100, 101
0
010
−10
110
111
000
001
011
−20
−30
011
−40
110
−50
0
0.1
0.2
0.3
0.4
f / fClock
0.5
Fig.13 Horizontal frequency characteristic of luminance signal (Y) dependent on HF2 to HF0 bits
(subaddress 04).
MEH513
10
handbook, full pagewidth
(dB)
100, 101
0
000
−10
111
010
001
−20
011, 110
−30
−40
011, 110
−50
0
0.05
0.10
0.15
0.20
f / fClock
0.25
Fig.14 Horizontal frequency characteristic of chrominance signals (UV) without UV interpolation dependent on
HF2 to HF0 bits (subaddress 04).
May 1993
31
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage (pins 5, 14, 26, 40, 55, 67, 76 and 91)
−0.5
6.5
V
VI
DC input voltage on all pins
−0.5
VDD
V
IDD
supply current (pins 5, 14, 26, 40, 55, 67, 76 and 91)
−
70
mA
Ptot
total power dissipation
0
1
W
Tstg
storage temperature range
−65
150
°C
Tamb
operating ambient temperature range
0
70
°C
VESD
handling(1)
−
±2000
V
electrostatic
for all pins
Note
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
11 DC CHARACTERISTICS
VDD1 to VDD8 = 4.5 to 5.5 V; Tamb = 0 to 70 °C unless otherwise specified.
SYMBOL
PARAMETER
VDD
supply voltage range (pins 5, 14, 26, 40,
55, 67, 76 and 91)
IP
total supply current (IDD1 + IDD2 + IDD3 +
IDD4 + IDD5 + IDD6 + IDD7 + IDD8)
CONDITIONS
inputs LOW and
outputs without load
MIN.
TYP.
MAX.
UNIT
4.5
5
5.5
V
−
80
−
mA
0.8
V
Data and control inputs
VI L
input voltage LOW
−0.5
−
VI H
input voltage HIGH
2.0
−
ILI
input leakage current
VI L = 0
−
−
10
µA
CI
input capacitance
data
−
−
8
pF
clocks
−
−
10
pF
VDD+0.5
V
Data and control outputs
VO L
output voltage LOW
note 1
−
−
0.6
V
VO H
output voltage HIGH
note 1
2.4
−
−
V
3-state outputs
IO off
high-impedance output current
−
−
±5
µA
CO
high-impedance output capacitance
−
−
8
pF
I2C-bus, SDA and SCL (pins 44 and 45)
VI L
input voltage LOW
−0.5
−
1.5
V
VI H
input voltage HIGH
3
−
VDD+0.5
V
I44, 45
input current
−
−
±10
µA
IACK
output current on pin 44
acknowledge
3
−
−
mA
VO L
output voltage at acknowledge
I44 = 3 mA
−
−
0.4
V
May 1993
32
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
12 AC CHARACTERISTICS
VDD1 to VDD8 = 4.5 to 5.5 V; Tamb = 0 to 60 °C unless otherwise specified.
SYMBOL
PARAMETER
LLC timing (pin 36)
tLLC
cycle time
tp
pulse width (duty factor)
tr
rise time
tf
fall time
Input data and CREF timing
tSU
setup time
tHD
hold time
VCLK timing (pin 51)
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.11
tLLC H / tLLC
31
−
45
ns
40
50
60
%
−
−
5
ns
−
−
6
ns
11
−
−
ns
3
−
−
ns
50
−
200
ns
Fig.15
Fig.16
tVCLK
VRAM port clock cycle time
note 2
tp L, tp H
LOW and HIGH times
note 3
17
−
−
ns
tr
rise time
−
−
5
ns
tf
fall time
−
−
6
ns
Output data and reference signal timing
Figures 15 and 16
CL
VRO outputs
15
−
40
pF
other outputs
7.5
−
25
pF
−
load capacitance
CL = 10 pF; note 4
0
−
ns
tOHL
related to LLC (INCADR, HFL)
CL = 10 pF; note 5
0
−
ns
tOHV
related to VCLK (HFL)
CL = 10 pF; note 5
0
−
ns
tOH
VRO data hold time
CL = 40 pF; note 4
−
−
25
ns
tODL
related to LLC (INCADR, HFL)
CL = 25 pF; note 5
−
−
60
ns
tODV
related to VCLK (HFL)
CL = 25 pF; note 5
−
−
60
ns
CL = 40 pF; note 6
−
−
40
ns
tOD
VRO data delay time
tD
output disable time to 3-state
tE
output enable time from 3-state
CL = 40 pF; note 6
−
−
40
ns
tHFL VOE
HFL maximum response time
VRAM port enabled
−
−
810
ns
tHFL VCLK
HFL maximum response time
HFL set at beginning
of VCLK burst
−
−
840
ns
Notes
1. Levels are measured with load circuit. VRO outputs with 1.2 kΩ in parallel to 25 pF at 3 V (TTL load).
2. Maximum tVCLK = 200 ns for test mode only. The applicable maximum cycle time depends on data format,
horizontal scaling and input data rate.
3. Measured at 1,5 V level; tp L may be unlimited.
4. Timings of VRO refer to the rising edge of VLCK.
5. The timing of INCADR refers to LLC; the rising edge of HFL always refers to LLC. During a VRAM transfer is the
falling edge of HFL generated by VCLK. Both edges of HFL refer to LLC during horizontal increment and vertical
reset cycles.
6. Asynchronous signals with timing referring to the 1.5 V switching point of VOEN input signal (pin 50).
May 1993
33
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
t LLC
t LLC H
2.4 V
clock input LLC
1.5 V
0.6 V
tf
tr
t SU
t HD
2.0 V
inputs CREF
0.8 V
t SU
t HD
2.0 V
input data
not valid
0.8 V
t ODL
t OHL
2.4 V
output HFL
and INCADR
not valid
0.6 V
MEH408-1
Fig.15 Data input timing (LLC).
May 1993
34
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
handbook, full pagewidth
2.0 V
1.5 V
VOEN
0.8 V
t VCLK
tr
tf
2.0 V
VCLK
1.5 V
0.8 V
tp H
t OD
t EN
tp L
t OH
not valid
2.4 V
output VRO(n)
0.6 V
t ODV
t OHV
2.4 V
output HFL
0.6 V
MEH409
Fig.16 Data output timing (VCLK).
13 PROCESSING DELAYS
PORTS
YIN to VRO
UVIN to VRO
HREF to VRO
May 1993
DELAY IN LLC
58
58
58
REMARKS
in transparent mode only
in transparent mode only
in transparent mode only
35
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
14 PROGRAMMING EXAMPLE
Slave address byte is B8h at pin IICSA = 0 (or BCh at pin IICSA = +5 V).
This example shows the setting via I2C-bus for the processing of a picture segment at 1:1 horizontal and vertical scale.
Values in brackets [..]:
If no scaling or panning is wanted,
the parameters XD, XS, YD and YS should be set to the maximum value 3FFh.
the parameters XO and YO should be set to the minimum value 000h.
(in this case, HREF and VS from external define the SAA7186 processing window).
SUBADDR.
(HEX)
BITS
00
RTB, OF(1:0), VPE,
LW(1:0), FS(1:0),
01
02
03
04
FUNCTION
VALUE
(HEX)
COMMENT
XD(7:0)
XS(7:0)
XO(7:0)
ROM table control and field
sequence processing; VRAM port
enable; output format select
LSB’s output pixel/line
LSB’s input pixel/line
LSB’s for horizontal window start
11
80 [FF]
80 [FF]
10 [00]
(1)
384 pixels out
384 pixels in
1st pixel after HREF = 1
HF(2:0), XO(8),
XS(9, 8), XD(9, 8)
YD(7:0)
YS(7:0)
YO(7:0)
horizontal filter select and MSB’s
of subaddresses 01, 02, 03
LSB’s output lines/field
LSB’s input lines/field
LSB’s vertical window start
85 [8F]
90 [FF]
90 [FF]
03 [00]
horizontal filter bypassed
144 lines out
144 lines in
1st line after VS = 0; (2)
AFS, VP(1:0), YO(8),
YS(9, 8), YD(9, 8)
VS(7:0)
VC(7:0)
VS(8), VC(8), TCC,
POE
adaptive and vertical filter select;
MSB’s of subaddresses 05, 06, 07
LSB’s vertical bypass start position
LSB’s vertical bypass lines/field
MSB’s of subaddresses 09, 0A;
UV input data representation
and odd/even polarity switch
00 [FF]
00
00
no adaptive select
vertical filter bypassed
not bypassed
region
00
defined; (3) (4)
0C
0D
0E
0F
VL(7:0)
VU(7:0)
UL(7:0)
UU(7:0)
UV keyer: lower limit V (R-Y)
UV keyer: upper limit V (R-Y)
UV keyer: lower limit U (B-Y)
UV keyer: upper limit U (B-Y)
00
FF
00
00
) keying is switched off
) by VU < VL
-
10
MCT, QPP, QPL,
TTR, EFE
Y or UV output data representation,
output data transfer mode,
pixel/ line qualifier polarity.
00
(5)
05
06
07
08
09
0A
0B
Notes
1. RTB =
OF =
VPE =
LW =
FS =
0
00
1
00
01
ROM table is active (only for RGB formats)
SAA7186 processes the both fields for interlaced display
VRAM port is enabled
longword position of first pixel in each output line = 0
16-bit 4:2:2 YUV output format is selected
2. for nominal VS length of 6 × H-period (input SAA7191B respectively SAA7151B with active VNL)
3. TTC = 0
May 1993
straight binary UV input data expected
36
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
4. odd/even polarity unchanged - can be used to change the field sequence if phase relations between HREF and VS
are not according to SAA7191B respectively SAA7151B specification
5. MCT =
QPP =
QPL =
TTR =
EFE =
May 1993
0
0
0
0
0
when EFE, FS = 001h: UV output data are straight binary
the pixel qualifier PXQ is “0”-active (if TTR, EFE = 1)
line qualifier LNQ is “0”-active (if TTR, EFE = 1)
VRAM port is set to data burst transfer
32-bit longword formats selected.
37
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
15 PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y
X
80
A
51
81
50
ZE
Q
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.40
0.25
0.25
0.14
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.4
1.2
0.2
0.15
0.1
Z D (1) Z E(1)
0.8
0.4
1.0
0.6
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT317-2
May 1993
EUROPEAN
PROJECTION
38
o
7
0o
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
16 SOLDERING
16.3
16.1
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
16.2
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
16.4
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
May 1993
Wave soldering
39
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
May 1993
40
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
NOTES
May 1993
41
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
NOTES
May 1993
42
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
NOTES
May 1993
43
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657027/00/01/pp44
Date of release: May 1993
Document order number:
9397 750 02436