Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier ADL5812 Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and broadband receivers NC IFOP1 IFON1 NC IFGD1 V1LO4 V1LO3 V1LO2 39 38 37 36 35 34 33 32 31 30 V1LO1 RFCT1 2 29 NC 28 NC 27 NC 26 LOIP 25 LOIN NC 7 24 LE NC 8 23 DATA 22 CLK 21 V2LO1 ADL5812 NC 3 NC 4 NC 5 BIAS GEN NC 6 SERIAL PORT INTERFACE RFCT2 9 16 17 18 19 20 V2LO3 V2LO2 IFOP2 15 V2LO4 14 NC 13 IFGD2 12 IFON2 11 NC RF2 10 09913-001 IFGM1 40 RF1 1 IFGM2 APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VPIF1 RF frequency: 700 MHz to 2800 MHz continuous LO frequency: 250 MHz to 2800 MHz, high-side or low-side inject IF range: 30 MHz to 450 MHz Power conversion gain of 6.7 dB at 1900 MHz SSB noise figure of 11.6 dB at 1900 MHz Input IP3 of 27.2 dBm at 1900 MHz Input P1dB of 12.5 dBm at 1900 MHz Typical LO drive of 0 dBm Single-ended, 50 Ω RF port Single-ended or balanced LO input port Single-supply operation: 3.6 V to 5.0 V Serial port interface control on all functions Exposed paddle 6 mm × 6 mm, 40-lead LFCSP package VPIF2 FEATURES Figure 1. GENERAL DESCRIPTION The ADL5812 uses revolutionary new broadband, square wave limiting, local oscillator (LO) amplifiers to achieve an unprecedented radio frequency (RF) bandwidth of 700 MHz to 2800 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this permits the LO to be applied either above or below the RF input over an extremely wide bandwidth. Because energy storage elements are not used, the dc current consumption also decreases with decreasing LO frequency. The ADL5812 uses highly linear, doubly balanced, passive mixer cores along with integrated RF and LO balancing circuits to allow single-ended operation. The ADL5812 incorporates programmable RF baluns, allowing optimal performance over a 700 MHz to 2800 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO-to-RF and LO-to-IF leakages, excellent RF-to-IF isolation, and excellent intermodulation performance over the full RF bandwidth. The balanced mixer cores also provide extremely high input linearity, allowing the device to be used in demanding wideband applications where in-band blocking signals may otherwise result in the degradation of dynamic range. Blocker noise figure performance is comparable to narrow-band passive mixer designs. High linearity IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 6.7 dB, and can be used with a wide range of output impedances. For low voltage applications, the ADL5812 is capable of operation at voltages down to 3.6 V with substantially reduced current. Two logic bits are provided to individually power down (1.5 mA for both channels) the two channels as desired. All features of the ADL5812 are controlled via a 3-wire serial port interface, resulting in optimum performance and minimum external components. The ADL5812 is fabricated using a BiCMOS high performance IC process. The device is available in a 40-lead, 6mm × 6mm, LFCSP package and operates over a −40°C to +85°C temperature range. An evaluation board is also available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADL5812 TABLE OF CONTENTS Features .............................................................................................. 1 RF Subsystem.............................................................................. 20 Applications....................................................................................... 1 LO Subsystem ............................................................................. 21 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 22 General Description ......................................................................... 1 Basic Connections...................................................................... 22 Revision History ............................................................................... 2 IF Port .......................................................................................... 22 Specifications..................................................................................... 3 Bias Resistor Selection ............................................................... 22 Timing Characteristics ................................................................ 4 VGS Programming..................................................................... 23 Absolute Maximum Ratings............................................................ 5 Low-Pass Filter Programming.................................................. 23 ESD Caution.................................................................................. 5 RF Balun Programming ............................................................ 23 Pin Configuration and Function Descriptions............................. 6 Register Structure ........................................................................... 24 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 25 3.6 V Performance...................................................................... 16 Outline Dimensions ....................................................................... 27 Spurious Performance................................................................ 17 Ordering Guide .......................................................................... 27 Circuit Description......................................................................... 20 REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADL5812 SPECIFICATIONS VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 1200 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept Input Second-Order Intercept Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious IF/3 Spurious POWER INTERFACE Supply Voltage, VS Quiescent Current Power-Down Current 1 Test Conditions/Comments Min Tunable to >20 dB broadband via serial port Typ Max Unit 2800 dB Ω MHz 10 50 700 Differential impedance, f = 200 MHz 260||1.2 30 Externally generated 450 VS −6 Low-side or high-side LO 250 Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential 5 dBm blocker present ±10 MHz from wanted RF input, LO source filtered fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF tone at −10 dBm fRF1 = 1900 MHz, fRF2 = 2000 MHz, fLO = 1697 MHz, each RF tone at −10 dBm Unfiltered IF output −10 dBm input power −10 dBm input power 3.6 Resistor programmable IF current Supply voltage must be applied from external circuit through choke inductors. Rev. 0 | Page 3 of 28 0 13.3 50 +10 2800 Ω||pF MHz V dBm dB Ω MHz 6.7 13.1 11.6 21 dB dB dB dB 27.2 dBm 55 dBm 12.5 −37 −46 26 −70 −78 dBm dBm dBm dB dBc dBc 5 412 1.5 5.5 V mA mA ADL5812 TIMING CHARACTERISTICS Low logic level ≤ 0.4 V, and high logic level ≥ 1.4 V. Table 2. Serial Interface Timing Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns minimum ns minimum ns minimum ns minimum ns minimum ns minimum ns minimum Test Conditions/Comments LE setup time DATA-to-CLK setup time DATA-to-CLK hold time CLK high duration CLK low duration CLK-to-LE setup time LE pulse width Timing Diagram t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 t1 09913-002 t6 LE Figure 2. Timing Diagram Rev. 0 | Page 4 of 28 ADL5812 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage, VPOS CLK, DATA, LE IF Output Bias RF Input Power LO Input Power Internal Power Dissipation θJA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 5.5 V 6.0 V 20 dBm 13 dBm 2.5 W 30°C 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 5 of 28 ADL5812 40 39 38 37 36 35 34 33 32 31 VPIF1 IFGM1 NC IFOP1 IFON1 NC IFGD1 V1LO4 V1LO3 V1LO2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RF1 1 RFCT1 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 RFCT2 9 RF2 10 ADL5812 V1LO1 NC NC NC LOIP LOIN LE DATA CLK V2LO1 NOTES 1. NC = NO CONNECT. CAN BE GROUNDED. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND. 09913-003 VPIF2 IFGM2 NC IFOP2 IFON2 NC IFGD2 V2LO4 V2LO3 V2LO2 11 12 13 14 15 16 17 18 19 20 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 10 2, 9 3 to 8, 13, 16, 27 to 29, 35, 38 11, 40 12, 39 14, 15, 36, 37 Mnemonic RF1, RF2 RFCT1, RFCT2 NC VPIF1, VPIF2 IFGM1, IFGM2 IFOP1, IFOP2, IFON1, IFON2 17, 34 18 to 21, 30 to 33 IFGD1, IFGD2 V1LO1, V1LO2, V1LO3, V1LO4, V2LO1, V2LO2, V2LO3, V2LO4 CLK, DATA, LE LOIN LOIP EPAD 22, 23, 24 25 26 Description RF Input. Should be ac-coupled. RF Balun Center Tap (AC Ground). No Connect. Can be grounded. Supply Voltage for IF Amplifier. IF Amplifier Bias Control. Differential Open-Collector IF Outputs. Should be pulled up to VCC via external inductors. Supply Return for IF Amplifier. Must be grounded. Positive Supply Voltages for LO Amplifiers. Serial Port Interface Control. Ground Return for LO Input. Must be ac coupled. LO Input. Should be ac-coupled. Exposed pad must be connected to ground. Rev. 0 | Page 6 of 28 ADL5812 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 1200 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted. 450 70 TA = –40°C TA = +25°C TA = +85°C TA = –40°C TA = +25°C TA = +85°C 65 60 INPUT IP2 (dBm) SUPPLY CURRENT (mA) 400 350 300 55 50 45 40 250 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 30 700 09913-008 RF FREQUENCY (MHz) Figure 4. Supply Current vs. RF Frequency 11 10 Figure 7. Input IP2 vs. RF Frequency 20 TA = –40°C TA = +25°C TA = +85°C 19 18 17 CONVERSION GAIN (dB) 9 16 INPUT P1dB (dBm) 8 7 6 5 4 15 14 13 12 11 10 9 3 8 2 7 1 6 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 5 700 09913-011 0 700 31 30 Figure 8. Input P1dB vs. RF Frequency 16 TA = –40°C TA = +25°C TA = +85°C 15 SSB NOISE FIGURE (dB) 28 27 26 25 24 23 22 21 13 12 11 10 9 8 20 7 19 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 09913-019 INPUT IP3 (dBm) TA = –40°C TA = +25°C TA = +85°C 14 29 18 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 5. Power Conversion Gain vs. RF Frequency 32 TA = –40°C TA = +25°C TA = +85°C 09913-020 12 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 Figure 6. Input IP3 vs. RF Frequency 6 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 9. SSB Noise Figure vs. RF Frequency Rev. 0 | Page 7 of 28 09913-025 200 700 09913-016 35 ADL5812 450 65 VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V 63 61 400 59 INPUT IP2 (dBm) SUPPLY CURRENT (mA) VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V 350 300 57 55 53 51 250 49 40 60 80 TEMPERATURE (°C) 45 –40 15 40 60 80 60 80 80 VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V 14 7.0 INPUT P1dB (dBm) CONVERSION GAIN (dB) 16 6.5 6.0 13 12 11 5.5 10 –20 0 20 40 60 80 TEMPERATURE (°C) 9 –40 09913-027 5.0 –40 30 0 20 40 Figure 14. Input P1dB vs. Temperature 14 VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V 29 –20 TEMPERATURE (°C) Figure 11. Power Conversion Gain vs. Temperature 13 SSB NOISE FIGURE (dB) 28 27 26 25 24 23 22 VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V 12 11 10 9 21 20 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 8 –40 09913-028 INPUT IP3 (dBm) 20 Figure 13. Input IP2 vs. Temperature VPOS = 4.75V VPOS = 5.00V VPOS = 5.25V 7.5 0 TEMPERATURE (°C) Figure 10. Supply Current vs. Temperature 8.0 –20 09913-030 20 09913-031 0 09913-026 –20 09913-029 47 200 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 15. SSB Noise Figure vs. Temperature Figure 12. Input IP3 vs. Temperature Rev. 0 | Page 8 of 28 ADL5812 70 450 RF = 900MHz RF = 1900MHz RF = 2500MHz 65 60 350 INPUT IP2 (dBm) 300 50 45 40 250 RF = 900MHz RF = 1900MHz RF = 2500MHz 80 130 35 180 230 280 330 380 430 IF FREQUENCY (MHz) 30 30 09913-032 200 30 55 80 130 330 380 430 380 430 380 430 14 8 12 7 INPUT P1dB (dBm) CONVERSION GAIN (dB) 280 16 RF = 900MHz RF = 1900MHz RF = 2500MHz 9 230 Figure 19. Input IP2 vs. IF Frequency Figure 16. Supply Current vs. IF Frequency 10 180 IF FREQUENCY (MHz) 09913-035 SUPPLY CURRENT (mA) 400 6 5 4 3 10 8 6 4 2 2 30 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz) 0 09913-033 0 RF = 900MHz RF = 1900MHz RF = 2500MHz 30 180 230 280 330 Figure 20. Input P1dB vs. IF Frequency 16 RF = 900MHz RF = 1900MHz RF = 2500MHz 33 130 IF FREQUENCY (MHz) Figure 17. Power Conversion Gain vs. IF Frequency 35 80 09913-036 1 14 RF = 900MHz RF = 1900MHz RF = 2500MHz SSB NOISE FIGURE (dB) 31 27 25 23 21 12 10 8 6 4 19 15 30 80 130 180 230 280 330 IF FREQUENCY (MHz) 380 430 Figure 18. Input IP3 vs. IF Frequency 0 30 80 130 180 230 280 330 IF FREQUENCY (MHz) Figure 21. SSB Noise Figure vs. IF Frequency Rev. 0 | Page 9 of 28 09913-037 2 17 09913-034 INPUT IP3 (dBm) 29 ADL5812 7 6 5 4 14 13 12 –4 –2 0 2 4 6 8 10 LO POWER (dBm) 10 –6 –40 RF = 900MHz RF = 1900MHz RF = 2500MHz –45 IF/2 SPURIOUS (dB) INPUT IP3 (dBm) 27 26 25 24 –2 0 2 4 6 8 10 10 TA = –40°C TA = +25°C TA = +85°C –55 –60 –65 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) –50 RF = 900MHz RF = 1900MHz RF = 2500MHz –55 TA = –40°C TA = +25°C TA = +85°C –60 IF/3 SPURIOUS (dB) 65 60 55 50 –65 –70 –75 45 –80 40 –85 –4 –2 0 2 4 6 LO POWER (dBm) 8 10 09913-040 INPUT IP2 (dBm) 8 Figure 26. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm Figure 23. Input IP3 vs. LO Power 35 –6 6 –50 –75 700 09913-039 –4 LO POWER (dBm) 70 4 –70 23 75 2 Figure 25. Input P1dB vs. LO Power 28 22 –6 0 09913-012 29 –2 LO POWER (dBm) Figure 22. Power Conversion Gain vs. LO Power 30 –4 09913-041 11 09913-038 3 –6 RF = 900MHz RF = 1900MHz RF = 2500MHz 15 INPUT P1dB (dBm) CONVERSION GAIN (dB) 8 16 RF = 900MHz RF = 1900MHz RF = 2500MHz –90 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY(MHz) Figure 27. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm Figure 24. Input IP2 vs. LO Power Rev. 0 | Page 10 of 28 09913-013 9 ADL5812 RESISTANCE (Ω) PERCENTAGE (%) 60 40 20 7.2 7.4 7.6 7.8 CONVERSION GAIN (dBm) 8 300 6 200 4 100 2 0 30 09913-065 0 7.0 400 130 180 230 280 330 380 430 480 0 IF FREQUENCY (MHz) Figure 31. IF Output Impedance (R Parallel C Equivalent) Figure 28. Conversion Gain Distribution –5 MEAN: 26.43 SD: 0.55% –6 –7 –8 RF RETURN LOSS (dB) 80 PERCENTAGE (%) 80 CAPACITANCE (pF) RF = 900MHz RF = 1900MHz RF = 2500MHz 80 100 10 500 MEAN: 7.37 SD: 0.12% 09913-057 100 60 40 –9 –10 –11 –12 –13 –14 –15 –16 –17 20 –18 26 28 30 INPUT IP3 (dBm) –20 700 09913-066 24 900 RF FREQUENCY (MHz) Figure 32. RF Port Return Loss, Fixed IF Figure 29. Input IP3 Distribution 100 –5 MEAN: 11.82 SD: 0.30% –6 –7 –8 LO RETURN LOSS (dB) 80 60 40 20 –9 –10 –11 –12 –13 –14 –15 –16 –17 –18 11.3 11.8 12.3 INPUT P1dB (dBm) 12.8 –20 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz) Figure 33. LO Return Loss Figure 30. Input P1dB Distribution Rev. 0 | Page 11 of 28 09913-060 –19 0 10.8 09913-064 PERCENTAGE (%) 1100 1300 1500 1700 1900 2100 2300 2500 2700 09913-062 –19 0 22 ADL5812 –10 2 × LO TO RF 2 × LO TO IF –15 –20 2× LO LEAKAGE (dBm) RF-TO-IF ISOLATION (dB) –15 –10 TA = –40°C TA = +25°C TA = +85°C –20 –25 –25 –30 –35 –40 –45 –30 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) –55 500 09913-023 –15 Figure 37. 2XLO Leakage vs. LO Frequency –10 TA = –40°C TA = +25°C TA = +85°C –15 3× LO LEAKAGE (dBm) LO-TO-IF LEAKAGE (dBm) –25 –30 –35 –40 –45 –50 900 1100 1300 1500 1700 1900 2100 2300 2500 09913-021 700 TA = –40°C TA = +25°C TA = +85°C –20 –25 –30 –35 –40 –45 –50 –55 700 900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz) 09913-022 LO-TO-RF LEAKAGE (dBm) –35 –40 –45 –50 –55 –70 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz) Figure 38. 3XLO Leakage vs. LO Frequency Figure 35. LO-to-IF Leakage vs. LO Frequency –60 500 –30 –65 LO FREQUENCY (MHz) –15 –25 –60 –55 –10 3 × LO TO RF 3 × LO TO IF –20 –20 –60 500 900 1100 1300 1500 1700 1900 2100 2300 2500 LO FREQUENCY (MHz) Figure 34. RF-to-IF Isolation vs. RF Frequency –10 700 Figure 36. LO-to-RF Leakage vs. LO Frequency Rev. 0 | Page 12 of 28 09913-005 –35 700 09913-004 –50 ADL5812 VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 550 VGS = 6 VGS = 7 SUPPLY CURRENT (mA) NOISE FIGURE 12 10 8 450 400 350 300 6 600 20 15 10 5 0 700 VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = 7 INPUT P1dB 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 18 16 14 18 NOISE FIGURE 12 15 10 12 8 GAIN 10 5 –25 –20 –15 –10 –5 0 5 RF BLOCKER LEVEL (dBm) 10 9 6 6 4 3 2 500 CHANNEL-TO-CHANNEL ISOLATION (dB) 15 24 21 600 700 800 0 900 1000 1100 1200 1300 1400 1500 1600 70 RF = 956MHz RF = 1950MHz RF = 2583MHz 20 0 –30 27 INPUT IP3 IF BIAS RESISTOR VALUE (Ω) 09913-061 NOISE FIGURE (dB) 25 30 RF = 900MHz RF = 1900MHz RF = 2500MHz 20 Figure 43. Power Conversion Gain, Noise Figure, and Input IP3 vs. IF Bias Resistor Value Figure 40. Input IP3 and Input P1dB vs. RF Frequency for All VGS Settings, RFB and LPF Use Optimum Settings 30 22 CONVERSION GAIN (dB) AND NOISE FIGURE (dB) 25 900 1000 1100 1200 1300 1400 1500 1600 Figure 42. Supply Current vs. IF Bias Resistor Value 09913-043 INPUT IP3 (dBm), INPUT P1dB (dBm) INPUT IP3 800 IF BIAS RESISTOR VALUE (Ω) Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for All VGS Settings, RFB and LPF Use Optimum Settings 30 700 INPUT IP3 RF FREQUENCY (MHz) 250 500 09913-059 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 09913-058 GAIN TA = –40°C TA = +25°C TA = +85°C 60 50 40 30 20 10 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 44. IF Channel-to-Channel Isolation vs. RF Frequency Figure 41. SSB Noise Figure vs. 10 MHz Offset Blocker Level Rev. 0 | Page 13 of 28 09913-006 4 700 RF = 900MHz RF = 1900MHz RF = 2500MHz 500 14 09913-042 CONVERSION GAIN AND NOISE FIGURE (dB) 16 ADL5812 9 8 16 15 14 7 6 5 4 13 12 11 10 9 3 8 2 7 1 6 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 5 700 09913-049 CONVERSION GAIN (dB) 10 17 RFB = 0 RFB = 1 RFB = 2 RFB = 3 RFB = 4 RFB = 5 RFB = 6 RFB = 7 RFB = 0 RFB = 1 RFB = 2 RFB = 3 RFB = 4 RFB = 5 RFB = 6 RFB = 7 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 45. Conversion Gain vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings 09913-051 11 INPUT P1dB (dBm) 12 Figure 47. Input P1dB vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings 18 30 29 16 28 25 24 23 22 21 20 700 RFB = 0 RFB = 1 RFB = 2 RFB = 3 RFB = 4 RFB = 5 RFB = 6 RFB = 7 14 12 10 8 6 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 4 700 RFB = RFB = RFB = RFB = RFB = RFB = RFB = RFB = 0 1 2 3 4 5 6 7 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 48. Noise Figure vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings Figure 46. Input IP3 vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings Rev. 0 | Page 14 of 28 09913-052 NOISE FIGURE (dB) 26 09913-050 INPUT IP3 (dBm) 27 ADL5812 16 10 9 14 12 INPUT P1dB (dBm) 7 6 5 4 3 8 6 =0 =1 =2 =3 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 0 700 28 15 26 14 24 13 NOISE FIGURE (dB) 16 22 20 18 16 12 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) LPF LPF LPF LPF =0 =1 =2 =3 12 11 10 9 8 =0 =1 =2 =3 7 09913-054 LPF LPF LPF LPF 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 Figure 51. Input P1dB vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings 30 14 =0 =1 =2 =3 RF FREQUENCY (MHz) Figure 49. Conversion Gain vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings 10 700 LPF LPF LPF LPF 2 09913-055 0 700 LPF LPF LPF LPF 6 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 52. Noise Figure vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings. Figure 50. Input IP3 vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings Rev. 0 | Page 15 of 28 09913-056 1 INPUT IP3 (dBm) 10 4 2 09913-053 CONVERSION GAIN (dB) 8 ADL5812 3.6 V PERFORMANCE VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 800 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted. 285 70 TA = –40°C TA = +25°C TA = +85°C 60 275 50 INPUT IP2 (dBm) SUPPLY CURRENT (mA) 280 270 265 260 255 40 30 20 250 245 10 240 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 0 700 09913-044 235 700 TA = –40°C TA = +25°C TA = +85°C 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 09913-047 290 Figure 56. Input IP2 vs. RF Frequency at 3.6 V Figure 53. Supply Current vs. RF Frequency at 3.6 V 9 12 8 10 6 INPUT P1dB (dBm) CONVERSION GAIN (dB) 7 5 4 3 8 6 4 2 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 0 700 25 - 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 54. Power Conversion Gain vs. RF Frequency at 3.6 V 30 TA = –40°C TA = +25°C TA = +85°C 09913-048 0 700 2 TA = –40°C TA = +25°C TA = +85°C 09913-045 1 Figure 57. Input P1dB vs. RF Frequency at 3.6 V 24 TA = –40°C TA = +25°C TA = +85°C TA = –40°C TA = +25°C TA = +85°C 22 20 NOISE FIGURE (dB) 15 10 16 14 12 10 8 6 4 5 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 58. SSB Noise Figure vs. RF Frequency at 3.6 V Figure 55. Input IP3 vs. RF Frequency at 3.6 V Rev. 0 | Page 16 of 28 09913-063 2 09913-046 INPUT IP3 (dBm) 18 20 ADL5812 SPURIOUS PERFORMANCE (N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm. 5 V Performance VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 1200 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted. Table 5. RF = 900 MHz, LO = 697 MHz 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −30.4 −60.9 −86.0 −100.0 <−100 <−100 1 −38.6 0.0 −54.1 −81.3 <−100 <−100 <−100 <−100 2 −19.2 −36.3 −78.0 −97.8 −94.9 <−100 <−100 <−100 <−100 3 −37.5 −19.2 −54.1 −90.8 <−100 <−100 <−100 <−100 <−100 4 −22.2 −52.5 −67.2 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 −48.1 −41.5 −77.8 −90.2 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 −42.0 −60.6 −76.1 −98.0 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 M 7 −63.0 −53.8 −97.7 −99.3 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 4 5 6 7 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 8 −59.2 −78.7 −91.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 −64.8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 11 12 13 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 11 12 13 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Table 6. RF = 1900 MHz, LO = 1697 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −26.1 −70.8 <−100 1 −26.1 0.0 −68.3 −91.4 <−100 2 −25.2 −46.0 −71.9 −88.9 <−100 3 −55.4 −54.5 −66.0 −76.3 <−100 <−100 −78.8 −80.4 −97.8 <−100 <−100 <−100 −97.7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. 0 | Page 17 of 28 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 ADL5812 Table 7. RF = 2500 MHz, LO = 2297 MHz M N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 −26.2 −84.5 1 −29.3 0.0 −72.0 <−100 2 −41.2 −45.0 −57.9 −87.7 <−100 3 −46.1 −67.1 −83.4 <−100 <−100 4 5 −96.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 7 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 3.6 V Performance VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 800 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted. Table 8. RF = 900 MHz, LO = 697 MHz 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −30.9 −69.9 −84.9 <−100 <−100 <−100 1 −44.7 0.0 −56.7 −78.6 <−100 <−100 <−100 <−100 2 −24.2 −34.6 −79.4 −95.9 −94.6 <−100 <−100 <−100 <−100 3 −35.2 −19.9 −57.4 −82.8 <−100 <−100 <−100 <−100 <−100 4 −25.5 −57.5 −65.0 −96.0 <−100 <−100 <−100 <−100 <−100 <−100 5 −46.6 −39.2 −76.9 −80.8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 −45.9 −59.8 −77.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 M 7 −64.1 −50.8 −92.8 −96.7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. 0 | Page 18 of 28 8 −65.9 −76.1 −85.8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 10 11 12 −60.0 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 ADL5812 Table 9. RF = 1900 MHz, LO = 1697 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −34.0 −72.9 <−100 1 −32.6 0.0 −72.4 <−100 <−100 2 −29.0 −53.6 −82.0 <−100 <−100 3 −60.9 −56.6 −73.1 −73.5 <−100 <−100 4 −86.3 −76.8 −95.9 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 7 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 11 12 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 Table 10. RF = 2500 MHz, LO = 2297 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −30.5 −92.7 1 −24.9 0.0 −78.3 <−100 2 −49.5 −46.6 −60.1 −96.3 <−100 3 −52.0 −68.5 −71.2 <−100 <−100 4 5 −95.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 7 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. 0 | Page 19 of 28 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 ADL5812 CIRCUIT DESCRIPTION The ADL5812 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. The wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components. The RF subsystem consists of an integrated, tunable, low loss RF balun; a double balanced, passive MOSFET mixer; a tunable sum termination network; and an IF amplifier. IFGM1 NC IFOP1 IFON1 NC IFGD1 V1LO4 V1LO3 V1LO2 40 39 38 37 36 35 34 33 32 31 RF1 1 30 V1LO1 RFCT1 2 29 NC 28 NC 27 NC 26 LOIP 25 LOIN NC 7 24 LE NC 8 23 DATA 22 CLK 21 V2LO1 ADL5812 NC 3 NC 4 NC 5 BIAS GEN NC 6 SERIAL PORT INTERFACE RFCT2 9 16 17 18 19 20 NC V2LO4 V2LO3 V2LO2 15 IFGD2 14 IFOP2 IFGM2 13 IFON2 12 NC 11 VPIF2 RF2 10 09913-067 VPIF1 The LO subsystem consists of a multistage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 59. Figure 59. Simplified Schematic RF SUBSYSTEM The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a tunable, low loss, unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 700 MHz to 2800 MHz. This balun is tuned over the frequency range by SPI controlled switched capacitor networks at the input and output of the RF balun. The resulting balanced RF signal is applied to a passive mixer that commutates the RF input in accordance with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all idler (M × N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a programmable low-pass filter network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced open-collector output of the IF amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an analog-to-digital converter (ADC) input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer or an LC impedance matching network. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the low-pass filter between the mixer and the IF amplifier. Further optimization can be made by adjusting the IF current with an external resistor. Figure 42 and Figure 43 illustrate how various IF resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing the IF resistor. It is permissible to reduce the IF amplifier’s dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.) Because the mixer is bidirectional, the tuning of the RF and IF ports is linked, and it is possible for the user to optimize gain, noise figure, IP3, and impedance match via the SPI. This feature permits high performance operation and is achieved entirely using SPI control. Additionally, the performance of the mixer can be improved by setting the optimum gate voltage on the passive mixer, which is also controlled by the SPI to enable optimum performance of the part. See the Applications Information section for examples of this tuning. Rev. 0 | Page 20 of 28 ADL5812 LO SUBSYSTEM The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation and compression performance. The resulting LO amplifier provides very high performance over a wide range of LO input frequencies. The ideal waveshape for switching the passive mixer is a square wave at the LO frequency to cause the mixer to switch through its resistive region (from on to off and off to on) as rapidly as possible. While it has always been possible to generate such a square wave, the amount of dc current required to generate a large amplitude square wave at high frequencies has made it impractical to create such a mixer. Novel circuitry within the ADL5812 permits the generation of a near-square wave output at frequencies up to 2800 MHz with dc current that compares favorably with that employed by narrow-band passive mixers. The input stages of the LO amplifier provide common-mode rejection, permitting the LO input to be driven either single ended or balanced. For a single-ended input, either LOIP or LOIN can be grounded. It is desirable to dc block the LO inputs to avoid damaging the part by the accidental application of a large dc voltage to the part. In addition, the LO inputs are internally dc blocked. Because the LO amplifier is inherently wideband, the ADL5812 can be driven with either high-side or low-side LO by simply setting the optimum RF balun and LPF inputs to the SPI. The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. Blocking dynamic range can benefit from a higher level of LO drive, which pushes the LO amplifier stages harder into compression and causes them to switch harder and to limit the small signal gain of the chain. Both of these conditions are beneficial to low noise figure under blocking. NF under blocking can be improved several decibels for LO input power levels above 0 dBm. The LO amplifier topology inherently minimizes the dc current based on the LO operating voltage and the LO operating frequency. It is permissible to reduce the LO supply voltage down as low as 3.6 V, which drops the dc current rapidly. The mixer dynamic range varies accordingly with the LO supply voltage. No external biasing resistor is required for optimizing the LO amplifier. In addition, the ADL5812 has a power-down mode. This powerdown mode can be used with any supply voltage applied to the part. All of the SPI inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All pins, including the RF pins, are ESD protected and have been tested up to a level of 2000 V HBM and 1250 V CDM. The LO amplifier converts a variable level, single or balanced input signal (−6 dBm to +10 dBm) to a hard voltage limited, balanced signal internally to drive the mixer. Excellent performance can be obtained with a 0 dBm input level; however, the circuit continues to function at considerably lower levels of LO input power. Rev. 0 | Page 21 of 28 ADL5812 APPLICATIONS INFORMATION BASIC CONNECTIONS The ADL5812 mixer is designed to downconvert radio frequencies (RF) primarily between 700 MHz and 2800 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 60 depicts the basic connections of the mixer. It is recommended to ac couple RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. A RFIN capacitor value of 22 pF is recommended. The real part of the output impedance is approximately 200 Ω, as seen in Figure 31, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain. When a 50 Ω output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 60. IF PORT External resistors, R1 and R2, are used to adjust the bias current of the integrated amplifier at the IF terminal. It is necessary to have a sufficient amount of current to bias both the internal IF amplifier to optimize dc current vs. optimum input IP3 performance. Figure 42 and Figure 43 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and input IP3 performance. BIAS RESISTOR SELECTION The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. VCC C1 0.1µF L1 470nH C3 T1 120pF TC4-1W+ L2 470nH 3 4 2 1 R20 OPEN 6 C5 120pF C4 120pF C2 0.1µF IFOP VCC C11 10pF IFON R21 0Ω R1 910Ω VCC C12 10pF C8 0.1µF AGND VCC 40 39 38 37 36 35 34 33 V1LO3 32 31 V1LO2 C13 10pF PAD C6 22pF 1 2 3 C7 22pF C25 22pF V1LO1 NC NC NC LOIP LOIN LE DATA CLK V2LO1 ADL5812 30 29 28 27 26 25 24 23 22 21 C2.3 10pF RFIN2 C17 LE 22pF DATA CLK VCC C15 10pF 12 11 C24 22pF VCC C14 10pF VPIF2 IFGM2 13 NC 14 IFOP2 15 IFON2 16 NC 17 IFGD2 18 V2LO4 19 V2LO3 20 V2LO2 RFIN2 4 5 6 7 8 9 10 RF1 RFCT1 NC NC NC NC NC NC RFCT2 RF2 RED VCC VPIF1 IFGM1 NC IFOP1 IFON1 NC IFGD1 V1LO4 RFIN1 BLK VPOS C16 22pF VCC C18 10pF R2 910Ω VCC C19 10pF VCC VCC C26 0.1µF C3 T1 120pF TC4-1W+ L4 470nH C27 0.1µF C4 120pF 3 4 2 1 6 IFOP R23 OPEN C30 120pF IFON R22 0Ω Figure 60. Evaluation Board Schematic Rev. 0 | Page 22 of 28 C20 10pF 09913-070 L3 470nH ADL5812 VGS PROGRAMMING RF BALUN PROGRAMMING The ADL5812 allows programmability for internal gate-to-source voltages for optimizing mixer performance over the desired frequency bands. The ADL5812 defaults the VGS setting to 0. Both channels of the ADL5812 are programmed together using the same VGS setting. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 39 and Figure 40. The ADL5812 allows programmability for the RF balun by allowing capacitance to be switched into both the input and the output, which allows the balun to be tuned to cover the entire frequency band (700 MHz to 2800 MHz). Under most circumstances, the input and output can be tuned together though sometimes it may be advantageous for matching reasons to tune them separately. The ADL5812 defaults the RFB setting to 0. Both channels of the ADL5812 are programmed together using the same RFB settings. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 45 and Figure 48. LOW-PASS FILTER PROGRAMMING The ADL5812 allows programmability for the low-pass filter terminating the mixer output. This filter helps to block sum term mixing products at the expense of some noise figure and gain and can significantly increase input IP3. The ADL5812 defaults the LPF setting to 0. Both channels of the ADL5812 are programmed together using the same LPF settings. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 49 to Figure 52. Rev. 0 | Page 23 of 28 ADL5812 REGISTER STRUCTURE output of the RF balun separately and that ability is provided. The LPF bits control the low-pass filter settings at the IF output. The ability to tune the low-pass filter allows some trade-off between gain, noise figure, and input IP3 with higher settings, 3, providing higher input IP3 at the cost of some gain and noise figure and lower settings, 0, providing higher gain and lower NF at the cost of lower input IP3. The VGS bits control the VGS settings of the mixer core and allow further tuning of the device. Figure 61 illustrates the register map of the ADL5812. The ADL5812 uses only Register 5. Because of this, set all of the control bits to five. When set to 0, the MAIN ENB and DIV ENB bits, DB7 and DB6, respectively, enable the part. By setting one of these bits to 1, its channel is powered down. Either channel can be powered down independently of the other. The RFB IN CAP DAC and RFB OUT CAP DAC bits are used to tune the RF balun. In most cases, they are tuned together with the higher settings, 7, tuning for the low frequencies, and with the lower settings, 0, tuning for the high frequencies. There are times where it becomes advantageous to tune the input and RESERVED VGS LPF RFB OUT CAP DAC Table 11 lists the optimum settings characterized for each frequency band. All register bits default to 0. RFB IN CAP DAC DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 0 VGS2 VGS1 VGS0 LPF1 LPF0 0 CDO2 DCDO1 CDO0 0 CDI2 CDI1 CDI0 VGS2 VGS1 VGS0 0 0 0 ' ' ' 1 1 1 DB8 0 MAIN ENB DIV ENB DB7 MEN DB6 DEN RESERVED DB5 0 DB4 0 CONTROL BITS DB3 0 DB2 DB1 C3(1) C2(0) DB0 C1(1) DEN DIVERSITY ENABLE 0 DEVICE ENABLED 1 DEVICE DISABLED VGS SETTING 0 ' 7 LPF1 LPF0 LOW PASS FILTER SETTING 0 0 0 ' ' ' 1 1 3 MEN 0 1 MAIN ENABLE DEVICE ENABLED DEVICE DISABLED CDI2 CDI1 CDI0 RF BALUN INTPUT TUNING 0 0 0 0 ' ' ' ' 1 1 1 7 09913-024 CDO2 CDO1 CDO0 RF BALUN OUTPUT TUNING 0 0 0 0 ' ' ' ' 1 1 1 7 Figure 61. ADL5812 Register Maps Table 11. Optimum Settings RF Frequency (MHz) 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 LO Frequency (MHz) 497 597 697 797 897 997 1097 1197 1297 1397 1497 1597 1697 1797 1897 1997 2097 2197 2297 2397 2497 2597 VGS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LPF 3 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 1 1 3 1 1 2 Rev. 0 | Page 24 of 28 RFB OUT CAP DAC 7 7 4 3 7 7 7 7 5 6 5 5 5 4 4 3 3 3 2 2 2 1 RFB IN CAP DAC 7 7 4 3 7 7 7 7 5 6 5 5 5 4 4 3 3 3 2 2 2 1 ADL5812 EVALUATION BOARD The evaluation board is fabricated using Rogers® 3003 material. Table 12 details the configuration for the mixer characterization. The evaluation board software is available on www.analog.com. An evaluation board is available for the ADL5812. The standard evaluation board schematic is presented in Figure 62. The USB interface circuitry schematic is presented in Figure 65. The evaluation board layout is shown in Figure 63 and Figure 64. VCC C1 0.1µF L1 470nH C3 T1 120pF TC4-1W+ L2 470nH 3 4 2 1 R20 OPEN 6 C5 120pF C4 120pF C2 0.1µF IFOP VCC C11 10pF IFON R21 0Ω R1 910Ω VCC C12 10pF C8 0.1µF AGND VCC 40 39 38 37 36 35 34 33 32 31 C13 10pF VPIF1 C6 22pF 1 2 3 C7 22pF C25 22pF V1LO1 NC NC NC LOIP LOIN LE DATA CLK V2LO1 ADL5812 C2.3 10pF 30 29 28 27 26 25 24 23 22 21 RFIN2 C17 LE 22pF DATA CLK VCC C15 10pF C16 22pF 16 17 18 19 20 13 14 15 12 11 C24 22pF VCC C14 10pF VPIF2 IFGM2 NC IFOP2 IFON2 NC IFGD2 V2LO4 V2LO3 V2LO2 RFIN2 4 5 6 7 8 9 10 RF1 RFCT1 NC NC NC NC NC NC RFCT2 RF2 RED VCC IFGM1 NC IFOP1 IFON1 NC IFGD1 V1LO4 V1LO3 V1LO2 PAD RFIN1 BLK VPOS VCC C18 10pF R2 910Ω VCC C19 10pF VCC VCC C26 0.1µF C3 T1 120pF TC4-1W+ L4 470nH C27 0.1µF C4 120pF 3 4 2 1 6 IFOP R23 OPEN C30 120pF C20 10pF IFON R22 0Ω 09913-072 L3 470nH Figure 62. Evaluation Board Schematic Table 12. Evaluation Board Configuration Components C1, C2, C8, C11, C12, C13, C14, C15, C18, C19, C20, C23, C26, C27 C6, C7, C24, C25 C3, C4, C5, C28, C29, C30, L1, L2, L3, L4, R20, R21, R22, R23, T1, T2 C17 R1, R2 Description Power supply decoupling. Nominal supply decoupling consists of a 0.1 μF capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. Default Conditions C1, C2, C26, C27 = 0.1 μF (size 0402), C8, C11, C12, C13, C14, C15, C18, C19, C20, C23 = 10 pF (size 0402) RF input interface. The input channels are ac-coupled through C6 and C24. C7 and C25 provide bypassing for the center tap of the RF input baluns. IF output interface. The open-collector IF output interfaces are biased through pull-up choke inductors L1, L2, L3, and L4. T1 and T2 are 4:1 impedance transformers used to provide single-ended IF output interfaces, with C5 and C30 providing center-tap bypassing. Remove R21 and R22 for balanced output operation. LO interface. C17 provides ac coupling for the LOIP local oscillator input. Bias control. R1and R2 set the bias point for the internal IF amplifier. C6, C24 = 22 pF (size 0402), C7, C25 = 22 pF (size 0402) Rev. 0 | Page 25 of 28 C3, C4, C5, C28, C29, C30 = 120 pF (size 0402), L1, L2, L3, L4 = 470 nH (size 0603), R20, R23 = open, R21, R22 = 0 Ω (size 0402), T1, T2 = TC4-1W+ (Mini-Circuits®) C17 = 22 pF (size 0402) R1, R2 = 910 Ω (size 0402) 09913-069 09913-068 ADL5812 Figure 63. Evaluation Board Top Layer Figure 64. Evaluation Board Bottom Layer Y2 24.000000MHZ 3 1 5V_USB C41 22PF CASE C40 2 4 22PF DGND DGND DGND J6 C34 1 10PF C35 2 3 4 5 3V3_USB 10PF C37 5 DGND 0.1UF WC_N GND 24LC64-I-SN 4 AVCC 55 SDA 43 SCL 17 A2 G1 G2 G3 G4 3V3_USB 11 VCC A0 A1 32 2 3 6 7 27 1 R8 2K 3 R7 2K 3V3_USB C36 DGND 0.1UF 7 U7 8 VCC XTALOUT DPLUS DMINUS IFCLK DGND CLKOUT CTL0_FLAGA CTL1_FLAGB 15 16 R9 3V3_USB 100K PA0_INT0_N SDA PA1_INT1_N R10 PA2_SLOE PA3_WU2 100K C38 0.1UF CTL2_FLAGC SCL 5 42 C39 0.1UF PA4_FIFOADR0 XTALIN PA5_FIFOADR1 RESET_N PA6_PKTEND PA7_FLAGD_SLCS_N PB0_FD0 44 14 DGND PB1_FD1 WAKEUP PB2_FD2 PB3_FD3 RESERVED PB4_FD4 PB5_FD5 1 2 PB6_FD6 PB7_FD7 RDY0_SLRD RDY1_SLWR PD0_FD8 DGND PD1_FD9 PD2_FD10 PD3_FD11 PD4_FD12 PD5_FD13 PD6_FD14 PAD 56 53 41 28 26 6 10 PD7_FD15 PAD GND 12 AGND DGND U6 GND PINS 897-43-005-00-100001 P1 4 8 9 13 54 29 30 31 1 2 3 SAMTECTSW10608GS3PIN 33 34 35 36 37 38 39 40 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52 R11 R17 0 0 R12 R18 0 0 R13 R19 0 0 R14 1K DNI DGND C49 TBD0402 330PF DNI DGND R15 1K DNI DGND C50 TBD0402 330PF DNI DGND R16 1K C51 TBD0402 DNI 330PF DGND LE DATA CLK DNI DGND DGND CY7C68013A-56LTXC DGND 3V3_USB 5V_USB 1 3P3V ORG 3V3_USB DNI SML-210MTT86 C DGND D1 DGND U5 7 8 6 IN1 OUT1 IN2 OUT2 SD_N PAD PAD FB GND DECOUPLING FOR U6 C33 1.0UF R6 140K DGND C42 0.1UF 5 R5 78.7K DGND ADP3334ACPZ C32 1000PF 1 2 3 DGND 1 C43 0.1UF DGND BLK DNI DGND Figure 65. USB Interface Circuitry on the Evaluation Board Rev. 0 | Page 26 of 28 DGND C44 0.1UF C45 0.1UF C46 0.1UF C47 0.1UF C48 0.1UF 09913-071 DGND A AGND C31 1.0UF R4 2K R3 0 ADL5812 OUTLINE DIMENSIONS 0.30 0.25 0.20 PIN 1 INDICATOR 40 1 31 30 0.50 BSC PIN 1 INDEX AREA 21 TOP VIEW 0.90 0.85 0.80 0.45 0.40 0.35 10 11 20 BOTTOM VIEW 0.21 MAX 0.19 MIN SEATING PLANE *4.19 4.14 SQ 4.09 EXPOSED PAD 0.02 REF 0.58 0.53 0.48 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-208 EXCEPT FOR EXPOSED PAD DIMENSION 04-24-2008-A 6.00 BSC SQ Figure 66. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-6) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5812ACPZ-R7 ADL5812-EVALZ 1 Temperature Range −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option CP-40-6 Quantity 750 ADL5812 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09913-0-7/11(0) Rev. 0 | Page 28 of 28