3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module HYS64V8000GU-10 HYS72V8000GU-10 168 pin unbuffered DIMM Modules • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications • 1 bank 8M x 64, 8M x 72 organisation • Optimized for byte-write non-parity or ECC applications • Fully PC66 layout compatible • JEDEC standard Synchronous DRAMs (SDRAM) • Performance: -10 fCK Max. Clock frequency tAC Max. access time from clock 66 MHz @ CL=2 100 MHz @ CL=3 8 ns @ CL=2 7 ns @ CL=3 • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E 2PROM • Utilizes eight / nine 8M x 8 SDRAMs in TSOPII-54 packages • 4096 refresh cycles every 64 ms • Gold contact pad • Card Size: 133,35mm x 25,40mm x 4,00 mm Semiconductor Group 1 2.98 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module The HYS64(72)V8000GU-10 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 8M x 64 and 8M x 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use eight 8M x 8 SDRAMs for the 8M x 64 organisation and an additional SDRAM for the 8M x 72 organisation. Decoupling capacitors are mounted on the PC board. The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I 2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint. Ordering Information Type Ordering Code Package Descriptions HYS 64V8000GU-10 L-DIM-168-23 PC66 8M x 64 SDRAM module HYS 72V8000GU-10 L-DIM-168-23 PC66 8M x 72 SDRAM module Pin Names A0-A11 BA0,BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 CLK0, CLK1 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. Address Inputs( RA0 ~ RA11 / CA0 ~ CA8) Bank Selects Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection Address Format: 8M x 64 8M x 72 Part Number HYS 64V8000GU HYS 72V8000GU Semiconductor Group Rows 12 12 Columns 9 9 2 Bank Select 2 2 Refresh 4k 4k Period 64 ms 64 ms Interval 15,6 µs 15,6 µs HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Note : Pinnames in brackets are for the x72 ECC versions Semiconductor Group 3 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 NC RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 NC DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module WE CS0 CS WE DQMB0 DQM DQ0-DQ7 DQ0-DQ7 CS WE DQMB4 DQM DQ32-DQ39 DQ0-DQ7 D4 D0 CS WE DQMB1 DQM DQ8-DQ15 DQ0-DQ7 CS WE DQM DQMB5 DQ0-DQ7 DQ40-DQ47 D1 D5 CS WE DQM CB0-CB7 DQ0-DQ7 D8 CS2 DQMB2 DQ16-DQ23 CS WE CS WE DQM DQ0-DQ7 D2 DQMB6 DQM DQ48-DQ55 DQ0-DQ7 DQMB7 DQM DQ56-DQ63 DQ0-DQ7 D6 CS WE DQMB3 DQ24-DQ31 DQ0-DQ7 D3 VSS Note: D7 D0 - D7,(D8) A0-A11,BA0,BA1 VCC CS WE DQM D0 - D7,(D8) C0-C15,(C16,C17) D0 - D7,(D8) E2PROM (256wordx8bit) SA0 SA1 SA2 RAS D0 - D7,(D8) CAS D0 - D7,(D8) CLK0 CKE0 D0 - D7,(D8) CLK1 1. D8 is only used in the x72 ECC version 2. All resistor values are 10 Ohms,except R3,R4=4,7 Ohm for the x72 version CLK2,CLK3 Block Diagram for 8M x 64/72 SDRAM DIMM modules Semiconductor Group SA0 SA1 SA2 4 SCL SDA 2 SDRAM 2 SDRAM R3 R4 2 or 3 SDRAM 2 SDRAM 10 pF HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 Vcc+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage ( IOUT = – 2.0 mA) VOH 2.4 – V Output low voltage ( IOUT = 2.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 40 40 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 40 40 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit min. (x64) max. (x72) CI1 45 55 pF Input capacitance ( CS0 - CS3) CI2 20 25 pF Input capacitance (CLK0 - CLK3) CI3 38 38 pF Input capacitance (DQMB0 - DQMB7) CI4 13 13 pF Input / Output capacitance (DQ0-DQ63,CB0-CB7) CIO 12 12 pF Input Capacitance (SCL,SA0-2) Csc 8 8 pF Input/Output Capacitance Csd 10 10 pF Input capacitance (A0 to A11, BS0, BS1 RAS, CAS, WE) Semiconductor Group 5 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module Operating Currents (TA = 0 to 70 oC, VCC = 3.3V ± 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. x64 x72 Note max. ICC1 880 990 mA 7 ICC2P 24 27 mA 7 ICC2PS 16 18 mA ICC2 400 450 mA ICC2S 40 45 mA ICC3 560 630 mA ICC3P 64 72 mA BURST OPERATING CURRENT tck = min., Read/Write command cycling ICC4 1240 1395 mA 7,8 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling ICC5 1040 1170 mA 7 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V ICC6 16 18 mA OPERATING CURRENT 1 bank operation trc=trcmin., tck=tckmin. Active-precharge command cycling, without burst operation PRECHARGE STANDBY CURRENT in Power Down Mode tck = min. CS =VIH (min.), CKE<=Vil(max) tck = Infinity PRECHARGE STANDBY CURRENT in Non-Power Down Mode tck = min. tck = Infinity 7 CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) CKE>=VIh(min.) CKE<=VIl(max.) (Power down mode) Notes: 7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the .......minimum value of tck and trc. Input signals are changed one time during tck. 8. These parameter depend on output loading. Specified values are obtained with output open. Semiconductor Group 6 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module AC Characteristics 1)2)3) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values Unit -10 min max Clock and Clock Enable Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 10 15 – – ns ns CAS Latency = 3 tCK CAS Latency = 2 – – 100 66 MHz MHz Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 – – 7 8 ns ns Clock High Pulse Width tCH 3 – ns Clock Low Pulse Width tCL 3 – ns Transition time tT 0.5 10 ns Command Setup Time tCS 2.5 – ns 5 Address Setup Time tAS 2.5 – ns 5 Data In Setup Time tDS 2.5 – ns 5 CKE Setup Time tCKS 2.5 – ns 5 Command Hold Time tCH 1 – ns 5 Address Hold Time tAH 1 – ns 5 Data In Hold Time tDH 1 – ns 5 CKE Hold Time tCKH 1 – ns 5 Row to Column Delay Time tRCD 30 – ns 6 Row Active Time tRAS 60 100k ns 6 Row Cycle Time tRC 90 – ns 6 Row Precharge Time tRP 30 – ns 6 Clock Frequency 4 Setup and Hold Times Common Parameters Semiconductor Group 7 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module Parameter Symbol Limit Values Unit -10 min max Activate(a) to Activate(b) Command period tRRD 20 – ns CAS(a) to CAS(b) Command period tCCD 1 – CLK Mode Register Set-up time tRSC 20 – ns Power Down Mode Entry Time tSB 0 10 ns Refresh Period (4096 cycles) tREF – 64 ms Self Refresh Exit Time tSREX 10 Data Out Hold Time tOH 3 – ns Data Out to Low Impedance Time tLZ 0 – ns Data Out to High Impedance Time tHZ 3 10 ns DQM Data Out Disable Latency tDQZ 2 – CLK CAS Latency = 3 tWR CAS Latency = 2 10 15 – – ns ns 0 – CLK 6 Refresh Cycle Read Cycle Write Cycle Write Recovery Time DQM Write Mask Latency Semiconductor Group tDQW 8 8 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit shown. tCH 2.4 V CLOCK 0.4 V tCL tSETUP tT + 1.4 V tHOLD 50 Ohm 1.4V INPUT Z=50 Ohm I/O tAC tAC tLZ 50 pF tOH 1.4V OUTPUT fig.1 tHZ 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. If tT is longer than 1 ns, a time (t T -1) ns has to be added to this parameter. 7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up“the device. 8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 9. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. Semiconductor Group 9 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus) SPD-Table: Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Description SPD Entry Value Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x 8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of internal SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Acces TIme from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Acces TIme from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD Semiconductor Group 10 128 256 SDRAM 12 9 Hex x64 -10 80 08 04 0C 09 x72 -10 80 08 04 0C 09 1 64 / 72 0 LVTTL 10 ns 7.0 ns none / ECC Self-Refresh, 15.6µs x8 n/a / x8 tccd = 1 CLK 01 40 00 01 A0 70 00 80 08 00 01 01 48 00 01 A0 70 02 80 08 08 01 1, 2, 4, 8 & full page 4 CAS latencies = 2,3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 15 ns 8.0 ns 8F 04 06 01 01 00 06 F0 80 8F 04 06 01 01 00 06 F0 80 not supported not supported 30 ns 20 ns FF FF 1E 14 FF FF 1E 14 HYS64(72)V8000GU-10 8M x 64/72 SDRAM-Module SPD-Table ( cont’d) Byte# Description SPD Entry Value 29 30 31 32-61 Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures’s information (optional) 127 (FFh if not used) 128+ Unused storage locations Hex x64 x72 -10 -10 1E 1E 2D 2D 10 10 FF FF 30 ns 45 ns 64 MByte Revision 1.2a 12 7A FF 12 8C FF FF FF L-DIM-168-23 SDRAM DIMM Module package 133,35 3,0 3,0 1 10 11 17,78 *) 84 40 41 124 125 25,40 127,35 42,18 66,68 85 94 95 A 168 B C +) CB's on x72 only 6,35 6,35 2,0 Detail A 1,0 + - 0.5 2,54 min. 3,125 3,125 1,27 2,0 Detail B 0,2 +- 0,15 Detail C DM168-23.WMF 8M x 64/72 SDRAM preliminary drawing Semiconductor Group 11