FEATURES FUNCTIONAL BLOCK DIAGRAM 133 dB SPL acoustic overload point Small and thin 4 mm × 3 mm × 1 mm surface-mount package Omnidirectional response Very high signal-to-noise ratio (SNR): 65 dBA Sensitivity of −46 dBFS Extended frequency response from 45 Hz to >20 kHz Low current consumption: 1.2 mA Sleep mode for extended battery life: 5.5 µA consumption High power supply rejection (PSR): −100 dBFS Fourth-order Σ-Δ modulator Digital pulse density modulation (PDM) output Compatible with Sn/Pb and Pb-free solder processes RoHS/WEEE compliant ADMP621 CLK DATA CHANNEL SELECT 11609-001 VDD POWER MANAGEMENT PDM MODULATOR L/R SELECT ADC GND Data Sheet Wide Dynamic Range Microphone with PDM Digital Output ADMP621 Figure 1. Smartphones and feature phones Tablet computers Teleconferencing systems Digital still and video cameras Bluetooth headsets Notebook PCs Security and surveillance BOTTOM TOP 11609-011 APPLICATIONS Figure 2. Isometric Views of ADMP621 Microphone Package GENERAL DESCRIPTION The ADMP6211 is a high sound pressure level (SPL), ultralow noise, low power, digital output, bottom ported omnidirectional MEMS microphone. This microphone clips at 133 dB SPL, which is useful for clearly capturing audio in loud environments. The ADMP621 consists of a MEMS microphone element and an impedance converter amplifier followed by a fourth-order Σ-Δ modulator. The digital interface allows the pulse density modulated (PDM) output of two microphones to be time multiplexed on a single data line using a single clock. The ADMP621 is pin compatible with the ADMP421 and ADMP521 microphones, providing an easy upgrade path. 1 The ADMP621 has a high SNR of 65 dBA and sensitivity of −46 dBFS. The ADMP621 has an extended wideband frequency response, resulting in natural sound with high intelligibility. Low current consumption and a sleep mode with less than 5.5 µA of current consumption enables long battery life for portable applications. The ADMP621 is available in a thin 4 mm × 3 mm × 1 mm surface-mount package. It is reflow solder compatible with no sensitivity degradation. Protected by U.S. Patents 7,449,356; 7,825,484; 7,885,423; and 7,961,897. Other patents are pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADMP621 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Connecting PDM Microphones ..................................................9 Applications ....................................................................................... 1 Sleep Mode .................................................................................. 10 Functional Block Diagram .............................................................. 1 Start-Up Time ............................................................................. 10 General Description ......................................................................... 1 Applications Information .............................................................. 11 Revision History ............................................................................... 2 Interfacing with Analog Devices Codecs ................................ 11 Specifications..................................................................................... 3 Supporting Documents ............................................................. 11 Timing Characteristics ................................................................ 4 PCB Design and Layout ................................................................. 12 Absolute Maximum Ratings ............................................................ 5 Alternative PCB Land Patterns................................................. 13 ESD Caution .................................................................................. 5 PCB Material and Thickness .................................................... 13 Pin Configuration and Function Descriptions ............................. 6 Handling Instructions .................................................................... 14 Typical Performance Characteristics ............................................. 7 Pick-and-Place Equipment ....................................................... 14 Theory of Operation ........................................................................ 8 Reflow Solder .............................................................................. 14 PDM Data Format ........................................................................ 8 Board Wash ................................................................................. 14 PDM Microphone Sensitivity ..................................................... 8 Outline Dimensions ....................................................................... 15 Dynamic Range Considerations ................................................. 9 Ordering Guide .......................................................................... 15 REVISION HISTORY 7/13—Revision 0: Initial Revision Rev. 0 | Page 2 of 16 Data Sheet ADMP621 SPECIFICATIONS TA = 25°C, VDD = 1.8 V, CLK = 3.072 MHz, CLOAD = 30 pF, unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. Table 1. Parameter PERFORMANCE Directionality Output Polarity Sensitivity 1, 2 Signal-to-Noise Ratio (SNR) Equivalent Input Noise (EIN) Acoustic Dynamic Range Digital Dynamic Range Frequency Response 3 Total Harmonic Distortion (THD) Power Supply Rejection (PSR) Power Supply Rejection—Swept Sine Acoustic Overload Point Full-Scale Acoustic Level POWER SUPPLY Supply Voltage (VDD) Supply Current (IS) Normal Mode Sleep Mode 4 DIGITAL INPUT/OUTPUT CHARACTERISTICS Input Voltage High (VIH) Input Voltage Low (VIL) Output Voltage High (VOH) Output Voltage Low (VOL) Output DC Offset Latency Noise Floor Test Conditions/Comments Input acoustic pressure vs. output data 1 kHz, 94 dB SPL 20 Hz to 20 kHz, A-weighted 20 Hz to 20 kHz, A-weighted Derived from EIN and acoustic overload point Derived from EIN and full-scale acoustic level Low frequency −3 dB point High frequency −3 dB point 105 dB SPL 217 Hz, 100 mV p-p square wave superimposed on VDD = 1.8 V, A-weighted 1 kHz sine wave 10% THD 0 dBFS output Min −48 Typ Omni Inverted −46 65 29 104 111 45 >20 0.35 −100 Max Unit −44 dBFS dBA dBA SPL dB dB Hz kHz % dBFS 1 −113 133 140 1.62 VDD = 1.8 V VDD = 3.3 V VDD = 1.8 V VDD = 3.3 V 1.2 1.3 dB dB SPL dB SPL 3.63 V 1.5 1.6 5.5 8 mA mA µA µA 0.65 × VDD 0.35 × VDD ILOAD = 0.5 mA ILOAD = 0.5 mA Percent of full scale 20 Hz to 20 kHz, A-weighted 0.7 × VDD VDD 0 3 <30 −111 0.3 × VDD V V V V % µs dBFS Sensitivity is relative to the rms level of a sine wave with positive amplitude equal to 100% 1s density and negative amplitude equal to 0% 1s density. The ±2 dB sensitivity specification is valid for CLK = 3.072 MHz. At lower clock frequencies, the minimum and maximum specifications are −49 dBFS and −43 dBFS, respectively. 3 See Figure 6 and Figure 7. 4 The microphone enters sleep mode when the clock frequency is less than 1 kHz. 1 2 Rev. 0 | Page 3 of 16 ADMP621 Data Sheet TIMING CHARACTERISTICS Table 2. Parameter SLEEP MODE Sleep Time Wake-Up Time INPUT tCLKIN Clock Frequency (CLK) Clock Duty Ratio OUTPUT t1OUTEN t1OUTDIS t2OUTEN t2OUTDIS 1 Description Min Time from CLK falling < 1 kHz Time from CLK rising > 1 kHz to output within 3 dB of final sensitivity, power on Input clock period Max 1 25 270 1.0 40 DATA1 (right) driven after falling clock edge DATA1 (right) disabled after rising clock edge DATA2 (left) driven after rising clock edge DATA2 (left) disabled after falling clock edge Typ Unit ms ms 1000 3.6 60 3.072 1 31 5 31 5 23 26 ns MHz % ns ns ns ns The microphone operates at any clock frequency between 1.0 MHz and 3.6 MHz. Some specifications may not be guaranteed at frequencies other than 3.072 MHz. Timing Diagram tCLKIN CLK t1OUTEN t1OUTDIS DATA1 t2OUTDIS 11609-002 DATA2 t2OUTEN Figure 3. Pulse Density Modulated Output Timing Rev. 0 | Page 4 of 16 Data Sheet ADMP621 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Digital Pin Input Voltage Sound Pressure Level Mechanical Shock Vibration Operating Temperature Range Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +3.63 V −0.3 V to VDD + 0.3 V or +3.63 V, whichever is less 160 dB 10,000 g Per MIL-STD-883 Method 2007, Test Condition B −40°C to +85°C −55°C to +150°C ESD CAUTION CRITICAL ZONE TL TO TP tP TP tL TSMAX TSMIN tS RAMP-DOWN PREHEAT t25°C TO PEAK TEMPERATURE TIME 11609-003 TEMPERATURE RAMP-UP TL Figure 4. Recommended Soldering Profile Limits Table 4. Recommended Soldering Profile Limits Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX), tS Ramp-Up Rate (TSMAX to TL) Time Maintained Above Liquidous (tL) Liquidous Temperature (TL) Peak Temperature (TP) Time Within 5°C of Actual Peak Temperature (tP) Ramp-Down Rate Time 25°C (t25°C) to Peak Temperature Sn63/Pb37 1.25°C/sec maximum Pb-Free 1.25°C/sec maximum 100°C 150°C 60 sec to 75 sec 1.25°C/sec 45 sec to 75 sec 183°C 215°C +3°C/−3°C 20 sec to 30 sec 3°C/sec maximum 5 minute maximum 100°C 200°C 60 sec to 75 sec 1.25°C/sec ~50 sec 217°C 260°C + 0°C/−5°C 20 sec to 30 sec 3°C/sec maximum 5 minute maximum Rev. 0 | Page 5 of 16 ADMP621 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DATA 5 1 CLK VDD 4 2 L/R SELECT GND 11609-004 3 Figure 5. Pin Configuration (Bottom View) Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic CLK L/R SELECT 3 4 GND VDD 5 DATA Description Clock Input to Microphone. Left Channel or Right Channel Select. DATA1 (right): L/R SELECT tied to GND. DATA2 (left): L/R SELECT tied to VDD. Ground. Power Supply. To avoid potential parasitic artifacts and for best performance, placing a 0.1 µF (100 nF) ceramic type, X7R capacitor between Pin 4 (VDD) and ground is strongly recommended. Place the capacitor as close to Pin 4 as possible. Digital Output Signal (DATA1, DATA2). Rev. 0 | Page 6 of 16 Data Sheet ADMP621 TYPICAL PERFORMANCE CHARACTERISTICS 20 10 10 5 THD + N (%) NORMALIZED AMPLITUDE (dB) 15 0 1 –5 –10 10 100 1k 0.1 90 11609-106 –20 10k FREQUENCY (Hz) 100 105 110 115 120 125 130 140 Figure 9. Total Harmonic Distortion + Noise (THD + N) vs. Input SPL 20 0 –5 15 –10 OUTPUT LEVEL (dBFS) 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –15 100 1k –50 11609-107 10 10k FREQUENCY (Hz) 90 100 110 120 130 140 INPUT LEVEL (dB SPL) 11609-110 –45 –20 Figure 10. Linearity Figure 7. Typical Frequency Response (Measured) 1.0 0 130dB SPL 132dB SPL 134dB SPL 136dB SPL 138dB SPL 0.8 –20 0.6 OUTPUT LEVEL (D) –40 –60 –80 0.4 0.2 0 –0.2 –100 –0.4 –120 1k FREQUENCY (Hz) 10k –0.8 0 0.0002 0.0004 0.0006 0.0008 TIME (Seconds) Figure 11. Clipping Characteristics Figure 8. PSR vs. Frequency, 100 mV p-p Swept Sine Wave Rev. 0 | Page 7 of 16 0.0010 11609-111 –140 100 –0.6 11609-108 PSR (dBFS) 135 INPUT LEVEL (dB SPL) Figure 6. Frequency Response Mask NORMALIZED AMPLITUDE (dB) 95 11609-109 –15 ADMP621 Data Sheet THEORY OF OPERATION PDM DATA FORMAT PDM MICROPHONE SENSITIVITY The output from the DATA pin of the ADMP621 is in pulse density modulated (PDM) format. This data is the 1-bit output of a fourth-order Σ-Δ modulator. The data is encoded so that the left channel is clocked on the falling edge of CLK, and the right channel is clocked on the rising edge of CLK. After driving the DATA signal high or low in the appropriate half frame of the CLK signal, the DATA driver of the microphone tristates. In this way, two microphones, one set to the left channel and the other to the right, can drive a single DATA line. See Figure 3 for a timing diagram of the PDM data format; the DATA1 and DATA2 lines shown in this figure are two halves of the single physical DATA signal. Figure 12 shows a diagram of the two stereo channels sharing a common DATA line. The sensitivity of a PDM output microphone is specified with the unit dBFS (decibels relative to digital full scale). A 0 dBFS sine wave is defined as a signal whose peak just touches the fullscale code of the digital word (see Figure 14). This measurement convention also means that signals with a different crest factor may have an rms level higher than 0 dBFS. For example, a full-scale square wave has an rms level of 3 dBFS. This definition of a 0 dBFS signal must be understood when measuring the sensitivity of the ADMP621. A 1 kHz sine wave at a 94 dB SPL acoustic input to the ADMP621 results in an output signal with a −46 dBFS level. The output digital word peaks at −46 dB below the digital full-scale level. A common misunderstanding is that the output has an rms level of −49 dBFS; however, this is not true because of the definition of the 0 dBFS sine wave. DATA DATA2 (L) DATA1 (R) DATA2 (L) 1.0 11609-013 CLK DATA1 (R) 0.8 Figure 12. Stereo PDM Format DIGITAL AMPLITUDE (D) 0.6 If only one microphone is connected to the DATA signal, the output is only clocked on a single edge (see Figure 13). For example, a left channel microphone is never clocked on the rising edge of CLK. In a single microphone application, each bit of the DATA signal is typically held for the full CLK period until the next transition because the leakage of the DATA line is not enough to discharge the line while the driver is tristated. 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 DATA1 (R) DATA1 (R) 11609-012 DATA DATA1 (R) Figure 13. Mono PDM Format See Table 6 for the channel assignments according to the logic level on the L/R SELECT pin. Table 6. Channel Setting L/R SELECT Setting Low (Tie to Ground) High (Tie to VDD) 0 Channel DATA1 (right) DATA2 (left) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 TIME (ms) 0.8 0.9 1.0 11609-114 CLK Figure 14. 1 kHz, 0 dBFS Sine Wave There is not a commonly accepted unit of measurement to express the instantaneous level, as opposed to the rms level of the signal, of a digital signal output from the microphone. Some measurement systems express the instantaneous level of an individual sample in units of D, where 1.0 D is digital full scale. In this case, a −46 dBFS sine wave has peaks at 0.005 D. For PDM data, the density of the pulses indicates the signal amplitude. A high density of high pulses indicates a signal near positive full scale, and a high density of low pulses indicates a signal near negative full scale. A perfect zero (dc) audio signal shows an alternating pattern of high and low pulses. The output PDM data signal has a small dc offset of about 3% of full scale. A high-pass filter in the codec that is connected to the digital microphone and does not affect the performance of the microphone typically removes this dc signal. Rev. 0 | Page 8 of 16 Data Sheet ADMP621 DYNAMIC RANGE CONSIDERATIONS 1.8V TO 3.3V The full-scale digital output (0 dBFS) of the ADMP621 is mapped to an acoustic input of 140 dB SPL. The microphone clips (THD = 10%) at 133 dB SPL (see Figure 9); however, it continues to output an increasingly distorted signal above that point. The peak output level, which is controlled by the modulator, limits at about −3 dBFS (see Figure 10). 0.1µF VDD ADMP621 0.1µF CODEC ADMP621 L/R SELECT CLK DATA CLOCK OUTPUT DATA INPUT 11609-014 GND DATA INPUT 1.8V TO 3.3V 0.1µF VDD ADMP621 L/R SELECT CLK DATA 11609-015 GND Figure 16. Stereo PDM Microphone Connection to Codec Decouple the VDD pin of the ADMP621 to GND with a 0.1 µF capacitor. Place this capacitor as close to VDD as the printed circuit board (PCB) layout allows. Do not use a pull-up or pull-down resistor on the PDM data signal line because it can pull the signal to an incorrect state during the period that the signal line is tristated. The DATA signal does not need to be buffered in normal use when the ADMP621 microphone(s) is placed close to the codec on the PCB. If the DATA signal must be driven over a long cable (>15 cm) or other large capacitive load, a digital buffer may be required. Only use a signal buffer on the DATA line when one microphone is in use or after the point where two microphones are connected (see Figure 17). The DATA output of each microphone in a stereo configuration cannot be individually buffered because the two buffer outputs cannot drive a single signal line. If a buffer is used, take care to select one with low propagation delay so that the timing of the data connected to the codec is not corrupted. ADMP621 Figure 15. Mono PDM Microphone (Right Channel) Connection to Codec CLK DATA CODEC CLOCK OUTPUT DATA INPUT ADMP621 CLK DATA 11609-016 VDD CLOCK OUTPUT GND CONNECTING PDM MICROPHONES 1.8V TO 3.3V DATA L/R SELECT To fully use the 111 dB digital dynamic range of the output data of the ADMP621 in a design, the digital signal processor (DSP), analog-to-digital converter (ADC), or codec circuit following it must be chosen carefully. The decimation filter that inputs the PDM signal from the ADMP621 must have a dynamic range sufficiently better than the dynamic range of the microphone so that the overall noise performance of the system is not degraded. If the decimation filter has a dynamic range of 10 dB better than the microphone (121 dB), the overall system noise only degrades by 0.4 dB. A PDM output microphone is typically connected to a codec with a dedicated PDM input. This codec separately decodes the left and right channels and filters the high sample rate modulated data back to the audio frequency band. This codec also generates the clock for the PDM microphones or is synchronous with the source that is generating the clock. See the Applications Information section for additional details on connecting the ADMP621 to Analog Devices, Inc., audio codecs with a PDM input. Figure 15 and Figure 16 show mono and stereo connections of the ADMP621 to a codec. The mono connection shows an ADMP621 set to output data on the right channel. To output on the left channel, tie the L/R SELECT pin to VDD instead of tying it to GND. CODEC CLK Figure 17. Buffered Connection Between Stereo ADMP621s and a Codec Rev. 0 | Page 9 of 16 ADMP621 Data Sheet When long wires are used to connect the codec to the ADMP621, a source termination resistor can be used on the clock output of the codec instead of a buffer to minimize signal overshoot or ringing. Match the value of this resistor to the characteristic impedance of the CLK trace on the PCB. Depending on the drive capability of the codec clock output, a buffer may still be needed, as shown in Figure 17. from sleep mode and begins to output data 32,768 cycles after the clock becomes active. For a 3.072 MHz clock, the microphone starts to output data in 10.7 ms. For a 2.4 MHz clock, the microphone starts to output data in 13.7 ms. The wake-up time, as specified in Table 2, indicates the time from when the clock is enabled to when the ADMP621 outputs data within 3 dB of its settled sensitivity. SLEEP MODE START-UP TIME The microphone enters sleep mode when the clock frequency falls below 1 kHz. In this mode, the microphone data output is in a high impedance state. The current consumption in sleep mode is less than 5.5 µA. The start-up time of the ADMP621 from when the clock is active is the same as the wake-up time. The microphone starts up 32,768 cycles after the clock is active. The ADMP621 enters sleep mode within 1 ms of the clock frequency falling below 1 kHz. The microphone wakes up Rev. 0 | Page 10 of 16 Data Sheet ADMP621 APPLICATIONS INFORMATION INTERFACING WITH ANALOG DEVICES CODECS Circuit Note The PDM output of the ADMP621 interfaces directly with the digital microphone inputs on the Analog Devices ADAU1361, ADAU1761, ADAU1781, and ADAU1772 codecs. See the connection diagram shown in Figure 18, and refer to the AN-1003 Application Note and the respective data sheets of the codecs for more details on the digital microphone interface. CN-0078, High Performance Digital MEMS Microphone Simple Interface to a SigmaDSP Audio Codec The CN-0078 Circuit Note describes the connection between these codecs and a digital microphone. All hardware configuration information is the same for the ADMP621 as it is for the ADMP421. SUPPORTING DOCUMENTS Application Notes AN-1003, Recommendations for Mounting and Connecting Analog Devices, Inc., Bottom-Ported MEMS Microphones AN-1068, Reflow Soldering of the MEMS Microphone AN-1112, Microphone Specifications Explained AN-1124, Recommendations for Sealing Analog Devices, Inc., Bottom-Port MEMS Microphones from Dust and Liquid Ingress AN-1140, Microphone Array Beamforming For additional information, see the following user guide, circuit note, and application notes. Evaluation Board User Guides UG-326, PDM Digital Output MEMS Microphone Evaluation Board 1.8V TO 3.3V AVDD MICBIAS CLK ADMP621 VDD DATA 0.1µF L/R SELECT ADAU1361 OR ADAU1761 GND BCLK/GPIO2 CLK ADMP621 GND 11609-008 L/R SELECT JACKDET/MICIN AGND DATA 0.1µF DGND VDD Figure 18. ADAU1361 or ADAU1761 Stereo Interface Block Diagram Rev. 0 | Page 11 of 16 ADMP621 Data Sheet PCB DESIGN AND LAYOUT microphone (0.25 mm, or 0.010 inch, in diameter). A 0.5 mm to 1 mm (0.020 inch to 0.040 inch) diameter for the hole is recommended. Take care to align the hole in the microphone package with the hole in the PCB. The exact degree of the alignment does not affect the microphone performance as long as the holes are not partially or completely blocked. The recommended PCB land pattern for the ADMP621 must be laid out to a 1:1 ratio to the solder pads on the microphone package, as shown in Figure 19. Avoid applying solder paste to the sound hole in the PCB. A suggested solder paste stencil pattern layout is shown in Figure 20. The response of the ADMP621 is not affected by the PCB hole size as long as the hole is not smaller than the sound port of the 3.80 ø1.70 CENTER LINE (0.30) 0.40 × 0.60 (4×) 0.35 (1.000) 0.90 (0.30) 2.80 ø1.10 (0.30) (0.550) 2× R0.10 2.05 11609-009 0.70 (0.30) 0.35 Figure 19. Recommended PCB Land Pattern Layout 2.45 1.498 × 0.248 0.9 0.248 × 0.948 (2×) 0.398 × 0.298 (4×) 1.849 0.35 1.45 CENTER LINE 0.7 1.000 1.525 1.849 0.248 × 1.148 (2×) 0.375 24° 0.248 × 0.498 (2×) 1.498 0.205 WIDE 0.362 CUT (3×) Figure 20. Suggested Solder Paste Stencil Pattern Layout Rev. 0 | Page 12 of 16 11609-010 1.17 24° Data Sheet ADMP621 ALTERNATIVE PCB LAND PATTERNS PCB MATERIAL AND THICKNESS The performance of the ADMP621 is not affected by PCB thickness and can be mounted on either a rigid or flexible PCB. A flexible PCB with the microphone can be attached directly to the device housing with an adhesive layer. This mounting method offers a reliable seal around the sound port, while providing the shortest acoustic path for good sound quality. 11609-017 The standard PCB land pattern of the ADMP621 has a solid ring around the edge of the footprint that can make routing the microphone signals more difficult in some board designs. This ring is used to improve the radio frequency (RF) immunity performance of the ADMP621; however, it is not necessary to have this full ring connected for electrical functionality. If a design can tolerate reduced RF immunity, this ring can either be broken or removed completely from the PCB footprint. Figure 21 shows an example PCB land pattern with no enclosing ring around the edge of the part, and Figure 22 shows an example PCB land pattern with the ring broken on two sides so that the inner pads can be more easily routed on the PCB. Note that in both of these patterns, the solid ring around the sound port is still present; this ring is needed to ground the microphone and for acoustic performance. The pad on the package connected to this ring is ground and still needs a solid electrical connection to the PCB ground. If a pattern like one of these two examples is used on a PCB, take care that the unconnected ring on the bottom of the ADMP621 is not placed directly over any exposed copper. This ring on the microphone is still at ground, and any PCB traces routed underneath it must be properly masked to avoid short circuits. 11609-018 Figure 21. Example PCB Land Pattern with No Enclosing Ring Figure 22. Example PCB Land Pattern with Broken Enclosing Ring Rev. 0 | Page 13 of 16 ADMP621 Data Sheet HANDLING INSTRUCTIONS PICK-AND-PLACE EQUIPMENT REFLOW SOLDER The MEMS microphone can be handled using standard pick-andplace and chip shooting equipment. Take care to avoid damage to the MEMS microphone structure as follows: For best results, the soldering profile must be in accordance with the recommendations of the manufacturer of the solder paste used to attach the MEMS microphone to the PCB. It is recommended that the solder reflow profile not exceed the limit conditions specified in Figure 4 and Table 4. • • • Use a standard pickup tool to handle the microphone. Because the microphone hole is on the bottom of the package, the pickup tool can make contact with any part of the lid surface. Do not pick up the microphone with a vacuum tool that makes contact with the bottom side of the microphone. Do not pull air out of or blow air into the microphone port. Do not use excessive force to place the microphone on the PCB. BOARD WASH When washing the PCB, ensure that water does not make contact with the microphone port. Do not use blow off procedures or ultrasonic cleaning. Rev. 0 | Page 14 of 16 Data Sheet ADMP621 OUTLINE DIMENSIONS 4.10 4.00 3.90 0.95 REF 3.54 REF 0.70 0.40 × 0.60 (Pins 1, 2, 4, 5) PIN 1 2.05 1.70 DIA. REFERENCE CORNER 0.30 REF 0.90 2.48 REF 3.10 3.00 2.90 3 1 2 5 4 0.30 REF 1.10 DIA. 1.50 0.25 DIA. (THRU HOLE) R 0.10 (2 ×) 2.80 1.05 REF TOP VIEW 0.35 1.10 1.00 0.90 0.35 0.30 REF 0.30 REF 0.72 REF SIDE VIEW 04-19-2012-G 3.80 BOTTOM VIEW 0.24 REF Figure 23. 5-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] 4 mm × 3 mm Body (CE-5-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADMP621ACEZ-RL ADMP621ACEZ-RL7 EVAL-ADMP621Z-FLEX 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 5-Terminal LGA_CAV, 13” Tape and Reel 5-Terminal LGA_CAV, 7” Tape and Reel Flexible Evaluation Board Z = RoHS Compliant Part. This package option is halide free. Rev. 0 | Page 15 of 16 Package Option 2 CE-5-1 CE-5-1 Ordering Quantity 5,000 1,000 ADMP621 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11609-0-7/13(0) Rev. 0 | Page 16 of 16