AD AD7568BS

a
LC2MOS
Octal 12-Bit DAC
AD7568
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
Low Power: 1 mW
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
44-Pin PQFP and PLCC
VDD
AGND
VREF D VREF C VREF B VREF A
DGND
R FB A
AD7568
INPUT
LATCH A
12
DAC A
LATCH
12
DAC B
LATCH
12
I OUT1A
DAC A
I OUT2A
RFB B
INPUT
LATCH B
12
I OUT1B
DAC B
IOUT2 B
RFB C
INPUT
LATCH C
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
12
DAC C
LATCH
12
DAC D
LATCH
12
I OUT1C
DAC C
I OUT2C
R FBD
INPUT
LATCH D
12
I OUT1D
DAC D
IOUT2 D
RFB E
INPUT
LATCH E
12
DAC E
LATCH
12
DAC F
LATCH
12
I OUT1E
DAC E
I OUT2E
GENERAL DESCRIPTION
RFB F
The AD7568 contains eight 12-bit DACs in one monolithic device. The DACs are standard current output with separate VREF,
IOUT1, IOUT2 and RFB terminals.
INPUT
LATCH F
IOUT1 F
DAC F
IOUT2 F
RFB G
INPUT
LATCH G
The AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a device address, and this feature may be used to simplify device
loading in a multi-DAC environment.
All DACs can be simultaneously updated using the asynchronous LDAC input and they can be cleared by asserting the
asynchronous CLR input.
12
DAC G
LATCH
12
12
I OUT1G
DAC G
I OUT2G
R FBH
INPUT
LATCH H
DAC H
LATCH
12
12
I OUT1H
DAC H
I OUT2H
CONTROL LOGIC
+
INPUT SHIFT
REGISTER
12
FSIN
CLKIN
SDIN
The AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.
A0
SDOUT
LDAC
CLR VREF E VREF F VREF G VREF H
PIN CONFIGURATIONS
NC 1
PIN 1 IDENTIFIER
33 NC
32 VREF C
R FB F 3
31 R FB C
IOUT1 F 4
30 I OUT1 C
AD7568 PQFP
AD7568
TOP
VIEW
VREF G 6
TOP
VIEW
Not
to Scale
(Not to Scale)
R FB G 7
IOUT2 D
IOUT1 D
VREF D
2
1
44 43 42 41 40
RFB D
AGND
3
VDD
4
DGND
5
RFB E
6
VREF E
IOUT2 E
IOUT1 E
34 IOUT2 D
35 IOUT1 D
36 R FB D
37 VREF D
38 AGND
39 DGND
40 VDD
Plastic Leaded Chip Carrier
VREF F 2
IOUT2 F 5
NC
7
VREF F
8
39 NC
38 VREF C
RFB F
9
37
RFB C
29 IOUT2 C
IOUT1 F 10
28 VREF B
IOUT2 F 11
AD7568 PLCC
35 IOUT2 C
VREF G 12
TOP VIEW
(Not to Scale)
34 VREF B
27 R FB B
36 IOUT1 C
30 VREF A
RFB H 17
29 RFB A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
32 IOUT1 B
IOUT1 A
IOUT2 A
A0
SDIN
CLKIN
FSIN
LDAC
CLR
SDOUT
18 19 20 21 22 23 24 25 26 27 28
IOUT2 H
NC = NO CONNECT
33 RFB B
IOUT1 H
I OUT1 A 22
31 IOUT2 B
VREF H 16
I OUT2 A 21
IOUT2 G 15
A0 20
23 R FB A
CLKIN 19
R FB H 11
FSIN 17
SDIN 18
IOUT1 G 14
LDAC 16
RFB G 13
24 VREF A
CLR 15
25 IOUT2 B
VREF H 10
SDOUT 14
26 I OUT1 B
I OUT2H 13
IOUT1 G 8
IOUT2 G 9
I OUT1 H 12
REV. B
41 VREF E
42 R FB E
44 I OUT2E
43 I OUT1E
Plastic Quad Flatpack
NC = NO CONNECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7568–SPECIFICATIONS1 unless otherwise noted)
(VDD = +4.75 V to +5.25 V; IOUT1 = IOUT2 = O V; VREF = +5 V; TA = TMIN to TMAX,
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
+25°C
TMIN to TMAX
Gain Temperature Coefficient
Output Leakage Current
IOUT1
@ +25°C
TMIN to TMAX
REFERENCE INPUT
Input Resistance
Ladder Resistance Mismatch
DIGITAL INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
POWER REQUIREMENTS
VDD Range
Power Supply Sensitivity
∆Gain/∆VDD
IDD
AD7568B2
Units
Test Conditions/Comments
12
± 0.5
± 0.9
Bits
LSB max
LSB max
1 LSB = VREF/212 = 1.22 mV when VREF = 5 V
±4
±5
2
5
LSBs max
LSBs max
ppm FSR/°C typ
ppm FSR/°C max
10
200
nA max
nA max
See Terminology Section
5
9
2
kΩ min
kΩ max
% max
Typical Input Resistance = 7 kΩ
2.4
0.8
±1
10
V min
V max
µA max
pF max
4.75/5.25
V min/V max
–75
300
3.5
dB typ
µA max
mA max
All Grades Guaranteed Monotonic over Temperature
Typically 0.6%
VINH = 4.0 V min, VINL = 0.4 V max
VINH = 2.4 V min, VINL = 0.8 V max
(These characteristics are included for Design Guidance and are not subject
AC PERFORMANCE CHARACTERISTICS to test. DAC output op amp is AD843.)
Parameter
AD7568B2
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
500
ns typ
Digital to Analog Glitch Impulse
40
nV–s typ
Multiplying Feedthrough Error
–66
dB max
Output Capacitance
Channel-to-Channel Isolation
60
30
–76
pF max
pF max
dB typ
Digital Crosstalk
40
nV–s typ
Digital Feedthrough
40
nV–s typ
Total Harmonic Distortion
Output Noise Spectral Density
@ 1 kHz
–83
dB typ
To 0.01% of Full-Scale Range. DAC Latch Alternately
Loaded with All 0s and All 1s.
Measured with VREF = 0 V. DAC Register Alternately
Loaded with All 0s and All 1s.
VREF = 20 V pk-pk, 10 kHz Sine Wave. DAC Latch
Loaded with All 0s.
All 1s Loaded to DAC.
All 0s Loaded to DAC.
Feedthrough from Any One Reference to the Others
with 20 V pk-pk, 10 kHz Sine Wave Applied.
Effect of all 0s to all 1s Code Transition on
Nonselected DACs.
Feedthrough to Any DAC Output with FSIN High
and Square Wave Applied to SDIN and SCLK.
VREF = 6 V rms, 1 kHz Sine Wave.
20
nV/√Hz
All 1s Loaded to the DAC. VREF = 0 V. Output Op
Amp is AD OP07.
NOTES
1
Temperature range as follows: B Version: –40°C to +85°C.
2
All specifications also apply for V REF = +10 V, except relative accuracy which degrades to ± 1 LSB.
Specifications subject to change without notice.
–2–
REV. B
AD7568
TIMING SPECIFICATIONS (V
DD
= +5 V 6 5%; IOUT1 = IOUT2 = 0 V; TA = TMIN to TMAX, unless otherwise noted)
Parameter
Limit at
TA = +258C
Limit at
TA = –408C to +858C
Units
Description
t1
t2
t3
t4
t5
t6
t7
t8 2
t9
100
40
40
30
30
5
90
70
40
100
40
40
30
30
5
90
70
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN Setup Time
Data Setup Time
Data Hold Time
FSIN Hold Time
SDOUT Valid After CLKIN Falling Edge
LDAC, CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
t1
CLKIN (I)
t3
t2
t4
t7
FSIN (I)
t5
t6
SDIN (I)
DB15
DB0
t8
SDOUT (O)
DB15
DB0
t9
LDAC, CLR
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Timing Diagram
1.6mA
I OL
ORDERING GUIDE
TO OUTPUT
PIN
+2.1V
CL
50pF
200µA
I OH
Temperature
Range
Linearity
Error (LSBs)
Package
Option*
AD7568BS
AD7568BP
–40°C to +85°C
–40°C to +85°C
± 0.5
± 0.5
S-44
P-44A
*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).
Figure 2. Load Circuit for Digital Output
Timing Specifications
REV. B
Model
–3–
AD7568
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
IOUT1 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
IOUT2 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . ± 15 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial Plastic (B Versions) . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 250 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN DESCRIPTION
Pin
Description
VDD
DGND
AGND
VREFA – VREFH
RFBA – RFBH
IOUTA – IOUTH
AGND
Positive power supply. This is +5 V ± 5%.
Digital Ground.
Analog Ground.
DAC reference inputs.
DAC feedback resistor pins.
DAC current output terminals.
This pin connects to the back gates of the current steering switches. It should be connected to the signal ground
of the system.
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.
Level-triggered control input (active low). This is the frame synchronization signal for the input data. When
FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the
address bit is valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling
edge after FSIN goes low.
Serial data input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining
bits following. Next comes the device address bit, A0. If this does not correspond to the logic level on pin A0,
the data is ignored. Finally come the three DAC select bits. These determine which DAC in the device is selected for loading.
This shift register output allows multiple devices to be connected in a daisy chain configuration.
Device address pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the data which follows is ignored and not loaded to any input latch. However it will appear at
SDOUT irrespective of this.
Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the
contents of the input latches.
Asynchronous CLR input. When this input is taken low, all DAC latch outputs go to zero.
CLKIN
FSIN
SDIN
SDOUT
A0
LDAC
CLR
–4–
REV. B
AD7568
TERMINOLOGY
Relative Accuracy
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage or full-scale
reading.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT terminal, when all 0s are
loaded in the DAC.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.
Output Leakage Current
Digital Crosstalk
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The IOUT2 leakage current is typically equal to that in
IOUT1.
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the device to show up as noise on the IOUT pin and subsequently on
the op amp output. This noise is digital feedthrough.
Output Capacitance
This is the capacitance from the IOUT1 pin to AGND.
Table I. AD7568 Loading Sequence
DB15
DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
Table II. DAC Selection
REV. B
DS2
DS1
DS0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A Selected
DAC B Selected
DAC C Selected
DAC D Selected
DAC E Sclected
DAC F Selected
DAC G Sclected
DAC H Selected
–5–
DB0
A0
DS2
DS1
DB0
DS0
AD7568 –Typical Performance Curves
5.5
2
5.0
1.0
V DD = +5V
V DD = +5V
TA = +25°C
4.5
0.8
4.0
0.7
3.0
2.5
VIH = +2.4V
DNL – LSBs
I DD – mA
I DD – mA
3.5
1
2.0
VIH = +4V
1.0
0.5
0.4
0.2
0.1
0.5
0.0
0.0
1.0
2.0
3.0
4.0
0
–40
5.0
–15
35
10
60
0.0
2.0
85
TEMPERATURE – °C
DIGITAL INPUT – Volts
Figure 3. Supply Current vs. Logic
Input Voltage
0.8
0.5
0.4
0.3
0.2
–55
VREF = +10V
VDD = +5V
TA = +25°C
10.0
V DD = +5V
TA = +25°C
V IN = 6V rms
OP AMP = AD713
–60
–65
0.6
THD – dBs
INL SPREAD – LSBs
0.6
8.0
–50
0.8
0.7
6.0
Figure 5. Differential Nonlinearity
Error vs. VREF
1.0
V DD = +5V
TA = +25°C
0.9
4.0
V REF – Volts
Figure 4. Supply Current vs.
Temperature
1.0
INL – LSBs
0.6
0.3
1.5
0.4
–70
–75
–80
–85
–90
0.2
0.1
–95
0.0
2.0
0.0
4.0
6.0
V REF – Volts
8.0
10.0
0
2048
4095
–100
10 2
DIGITAL CODE
Figure 6. Integral Nonlinearity Error
vs. VREF
Figure 7. Typical DAC to DAC
Linearity Matching
200ns
90
AD713 OUTPUT
VDD = +5V
TA = +25°C
VREF = +10V
OP AMP = AD713
10 5
0
VREF C = 20V pk-pk SINE WAVE
ALL OTHER REFERENCE INPUTS GROUNDED
DAC C LOADED WITH ALL 1s
ALL OTHER DACs LOADED WITH ALL 0s
–20
VREF B GROUNDED
ALL OTHER REFERENCE INPUTS =
20V pk-pk SINE WAVE
DAC B LOADED WITH ALL 0s
ALL OTHER DACs LOADED WITH ALL 1s
–10
–20
VOUT B/VOUT C – dBs
DIGITAL INPUTS
VOUT B/VOUT C – dBs
5V
10 4
10 3
FREQUENCY – Hz
Figure 8. Total Harmonic Distortion
vs. Frequency
0
–10
100
VDD = +5V
TA = +25°C
0.9
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
10
–80
0%
50mV
200ns
Figure 9. Digital-to-Analog Glitch
Impulse
–80
–90
–90
–100
–100
10 3
10 4
10 5
FREQUENCY – Hz
Figure 10. Channel-to-Channel
Isolation (1 DAC to 1 DAC)
–6–
10 6
10 3
10 4
10 5
FREQUENCY – Hz
10 6
Figure 11. Channel-to-Channel
Isolation (1 DAC to All Other DACs)
REV. B
AD7568
Interface Section
0
–10
DAC LOADED WITH ALL 1s
–20
The AD7568 is a serial input device. Three lines control the serial interface, FSIN, CLKIN and SDIN. The timing diagram is
shown in Figure 1.
V DD = +5V
TA = +25°C
V IN = 20V pk-pk
OP AMP = AD713
–30
–40
When the FSIN input goes low, data appearing on the SDIN
line is clocked into the input shift register on each falling edge of
CLKIN. When sixteen bits have been received, the register
loading is automatically disabled until the next falling edge of
FSIN detected. Also, the received data is clocked out on the
next rising edge of CLKIN and appears on the SDOUT pin.
This feature allows several devices to be connected together in a
daisy chain fashion.
–50
–60
–70
DAC LOADED WITH ALL 0s
–80
–90
–100
10 3
10 4
10 5
10 6
107
When the sixteen bits have been received in the input shift register, DB3 (A0) is checked to see if it corresponds to the state of
pin A0. If it does, then the word is accepted. Otherwise, it is disregarded. This allows the user to address one of two AD7568s
in a very simple fashion. DB0 to DB2 of the 16-bit word determine which of the eight DAC input latches is to be loaded.
When the LDAC line goes low, all eight DAC latches in the device are simultaneously loaded with the contents of their respective input latches, and the outputs change accordingly.
Figure 12. Multiplying Frequency Response vs.
Digital Code
GENERAL DESCRIPTION
D/A Section
The AD7568 contains eight 12-bit current-output D/A converters. A simplified circuit diagram for one of the D/A converters is
shown in Figure 13.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A, B and C.
The remaining 10 bits of the data word drive the switches S0 to
S9 in a standard R–2R ladder configuration.
Bringing the CLR line low resets the DAC latches to all 0s. The
input latches are not affected, so that the user can revert to the
previous analog output if desired.
Each of the switches A to C steers 1/4 of the total reference current with the remaining current passing through the R–2R
section.
CLKIN
FSIN
SDIN
Each DAC in the device has separate VREF, IOUT1, IOUT2 and
RFB pins. This makes the device extremely versatile and allows
DACs in the same device to be configured differently.
VOUT = –D•VREF
where D is the fractional representation of the digital word
loaded to the DAC. Thus, in the AD7568, D can be set from
0 to 4095/4096.
R
2R
C
2R
B
R
2R
A
R
2R
S9
2R
S8
2R
S9
2R
R/2
R FB
I OUT1
I OUT2
SHOWN FOR ALL 1s ON DAC
Figure 13. Simplified D/A Circuit Diagram
REV. B
SDOUT
Figure 14. Input Logic
When an output amplifier is connected in the standard configuration of Figure 15, the output voltage is given by:
V REF
16-BIT INPUT SHIFT REGISTER
–7–
AD7568
UNIPOLAR BINARY OPERATION
(2-Quadrant Multiplication)
R4
R2 10Ω
Figure 15 shows the standard unipolar binary connection diagram for one of the DACs in the AD7568. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication. Resistors
R1 and R2 allow the user to adjust the DAC gain error. Offset
can be removed by adjusting the output amplifier offset voltage.
R1 20Ω
I OUT1 A
V IN
DAC A
C1
20kΩ
R3
VOUT
A1
VREF A
10kΩ
I OUT2 A
AD7568
A1 should be chosen to suit the application. For example, the
AD OP07 or OP177 are ideal for very low bandwidth applications while the AD843 and AD845 offer very fast settling time
in wide bandwidth applications. Appropriate multiple versions
of these amplifiers can be used with the AD7568 to reduce
board space requirements.
20kΩ
R5
R FB A
A2
SIGNAL
GND
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 16. Bipolar Operation (4-Quadrant Multiplication)
The code table for Figure 15 is shown in Table III.
Table IV. Bipolar (Offset Binary) Code Table
R2 10Ω
RFB A
R1 20Ω
I OUT1 A
VIN
DAC A
C1
VOUT
Digital Input
MSB . . . . . LSB
Analog Output
(VOUT As Shown in Figure 16)
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
+VREF (2047/2048)
+VREF (1/2048)
+VREF (0/2048) = 0
–VREF (1/2048)
–VREF (2047/2048)
–VREF (2048/2048) = –VREF
A1
VREF A
AD7568
I OUT2 A
A1: OP-177
SIGNAL
ADOP-07
GND
AD711
AD843
NOTES
AD845
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
NOTE
Nominal LSB size for the circuit of Figure 16 is given by:
VREF (1/2048).
Figure 15. Unipolar Binary Operation
Table III. Unipolar Binary Code Table
Digital Input
MSB………LSB
Analog Output
(VOUT As Shown in Figure 15)
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
–VREF (4095/4096)
–VREF (2049/4096)
–VREF (2048/4096)
–VREF (2047/4096)
–VREF (1/4096)
–VREF (0/4096) = 0
SINGLE SUPPLY CIRCUITS
The AD7568 operates from a single +5 V supply, and this
makes it ideal for single supply systems. When operating in such
a system, it is not possible to use the standard circuits of Figures
15 and 16 since these invert the analog input, VIN. There are
two alternatives. One of these continues to operate the DAC as
a current-mode device, while the other uses the voltage switching mode.
RFB A
I OUT1 A
V IN
NOTE
Nominal LSB size for the circuit of Figure 15 is given by:
VREF (1/4096).
DAC A
V REF A
AD7568
VOUT
A1
I OUT2 A
BIPOLAR OPERATION
(4-Quadrant Multiplication)
Figure 16 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7568. The coding is
offset binary as shown in Table IV. When VIN is an ac signal,
the circuit performs 4-quadrant multiplication. To maintain the
gain error specifications, resistors R3, R4 and R5 should be ratio matched to 0.01%.
VBIAS
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 17. Single Supply Current-Mode Operation
–8–
REV. B
AD7568
Current Mode Circuit
R1
In the current mode circuit of Figure 17, IOUT2, and hence
IOUT1, is biased positive by an amount VBIAS. For the circuit to
operate correctly, the DAC ladder termination resistor must be
connected internally to IOUT2. This is the case with the AD7568.
The output voltage is given by:
{
R FB A
V IN I
OUT1 A
I OUT2 A
}
DAC
VOUT
V REF A
A1
DAC A
AD7568
V OUT = D R FB (V BIAS −V IN ) +V BIAS
R
R2
NOTES
1) ONLY ONE DAC IS SHOWN FOR CLARITY.
2) DIGITAL INPUT CONNECTIONS ARE OMITTED.
3) C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
As D varies from 0 to 4095/4096, the output voltage varies from
VOUT = VBIAS to VOUT = 2 VBIAS – VIN. VBIAS should be a low
impedance source capable of sinking and sourcing all possible
variations in current at the IOUT2 terminal without any
problems.
Figure 18. Single Supply Voltage Switching
Mode Operation
Voltage Mode Circuit
Figure 18 shows DAC A of the AD7568 operating in the
voltage-switching mode. The reference voltage, VIN is applied to
the IOUT1 pin, IOUT2 is connected to AGND and the output voltage is available at the VREF terminal. In this configuration, a
positive reference voltage results in a positive output voltage
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder resistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the voltage input should be driven from a low impedance source.
APPLICATIONS
Programmable State Variable Filter
The AD7568 with its multiplying capability and fast settling
time is ideal for many types of signal conditioning applications.
The circuit of Figure 19 shows its use in a state variable filter
design. This type of filter has three outputs: low pass, high pass
and bandpass. The particular version shown in Figure 19 uses
one half of an AD7568 to control the critical parameters f0, Q
and A0. Instead of several fixed resistors, the circuit uses the
DAC equivalent resistances as circuit elements. Thus, R1 in
Figure 19 is controlled by the 12-bit digital word loaded to
DAC A of the AD7568. This is also the case with R2, R3 and
R4. The fixed resistor R5 is the feedback resistor, RFBB.
It is important to note that VIN is limited to low voltages because the switches in the DAC no longer have the same sourcedrain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, VIN must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.
DAC Equivalent Resistance, REQ = (RLADDER 3 4096)/N
where:
RLADDER is the DAC ladder resistance.
N is the DAC Digital Code in Decimal (0 < N < 4096).
C3 10pF
R8 30kΩ
A1
R6
10kΩ
R7 30kΩ
HIGH
PASS
OUTPUT
C1 1000pF
A2
C1 1000pF
A3
LOW
PASS
OUTPUT
A1
I OUT1 A
VIN
VREF A
DAC A
(R1)
I OUT1 B
RFB B VREF B VREF C
DAC B
(R2)
I OUT1 C
DAC C
(R3)
VREF D
I OUT1 D
DAC D
(R4)
1/2 x AD7568
I OUT2 A
I OUT2 C
I OUT2 B
I OUT2 D
NOTES
1. A1, A2, A3, A4: 1/4 x AD713
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE
Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN
BANDWIDTH LIMITATIONS.
Figure 19. Programmable 2nd Order State Variable Filter
REV. B
–9–
BAND
PASS
OUTPUT
AD7568
In the circuit of Figure 19:
C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to
each DAC).
Resonant frequency, f0 = 1/(2πR3C1).
Quality Factor, Q = (R6/R8)•(R2/R5).
Bandpass Gain, A0 = –R2/R1.
Using the values shown in Figure 19, the Q range is 0.3 to 5,
and the f0 range is 0 to 12 kHz.
APPLICATION HINTS
Output Offset
the data word transmitted to the AD7568 corresponds to the
loading sequence shown in Table I. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its serial data in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. To load data to the AD7568, P3.3 is left low after the first eight bits are transferred, and a second byte of data
is then transferred serially to the AD7568. When the second serial transfer is complete, the P3.3 line is taken high. Note that
the 80C51 outputs the serial data byte in a format which has the
LSB first. The AD7568 expects the MSB first. The 80C51
transmit routine should take this into account.
CMOS D/A converters in circuits such as Figures 15, 16 and 17
exhibit a code dependent output resistance which in turn can
cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the
D/A converter nonlinearity, depends on VOS, where VOS is the
amplifier input offset voltage. For the AD7568 to maintain
specified accuracy with VREF at 10 V, it is recommended that
VOS be no greater than 500 µV, or (50 3 10–6)•(VREF), over the
temperature range of operation. Suitable amplifiers include the
AD OP07, AD OP27, OP177, AD711, AD845 or multiple versions of these.
80C51*
High Frequency Considerations
The output capacitances of the AD7568 DACs work in conjunction with the amplifier feedback resistance to add a pole to
the open loop response. This can cause ringing or oscillation.
Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. This is shown as
C1 in Figures 15, 16 and 17.
MICROPROCESSOR INTERFACING
AD7568–80C51 Interface
A serial interface between the AD7568 and the 80C51 microcontroller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7568 while RXD drives the serial data line of
the part. The FSIN signal is derived from the port line P3.3.
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
P3.5
CLR
P3.4
LDAC
P3.3
FSIN
TXD
SCLK
RXD
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Temperature Coefficients
The gain temperature coefficient of the AD7568 has a maximum value of 5 ppm/°C and a typical value of 2 ppm/°C. This
corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively
over a 100°C temperature range. When trim resistors R1 and
R2 are used to adjust full-scale in Figures 15 and 16, their temperature coefficients should be taken into account. For further
information see “Gain Error and Gain Temperature Coefficient
of CMOS Multiplying DACs,” Application Note, Publication
Number E630c–5–3/86, available from Analog Devices.
AD7568*
Figure 20. AD7568 to 80C51 Interface
LDAC and CLR on the AD7568 are also controlled by 80C51
port outputs. The user can bring LDAC low after every two
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the input registers have been loaded (sixteen byte transmits) and then
update the DAC outputs.
AD7568–68HC11 Interface
Figure 21 shows a serial interface between the AD7568 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7568, while the MOSI output drives the serial data line
of the AD7568. The FSIN signal is derived from a port line
(PC7 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes (MSB first), with only eight falling clock
edges occurring in the transmit cycle. To load data to the
AD7568, PC7 is left low after the first eight bits are transferred,
and a second byte of data is then transferred serially to the
AD7568. When the second serial transfer is complete, the PC7
line is taken high.
–10–
REV. B
AD7568
68HC11*
AD7568*
TMS320C25*
AD7568*
+5V
PC5
CLR
PC6
LDAC
PC7
FSIN
SCK
CLKIN
MOSI
CLR
XF
SDIN
LDAC
FSX
FSIN
DX
SDIN
CLKX
*ADDITIONAL PINS OMITTED FOR CLARITY
CLKIN
CLOCK
GENERATION
Figure 21. AD7568 to 68HC11 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.
Figure 23. AD7568 to TMS320C25 Interface
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.
AD7568–ADSP-2101 Interface
Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. The ADSP-2101 may be
set up to operate in the SPORT Transmit Normal Internal
Framing Mode. The following ADSP-2101 conditions are recommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. Transmission is initiated by writing a word to the
TX register after the SPORT has been enabled. The data is then
clocked out on every rising edge of SCLK after TFS goes low.
TFS stays low until the next data transfer.
Multiple DAC Systems
If there are only two AD7568s in a system, there is a simple way
of programming each. This is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to program a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.
ADSP-2101*
ADSP-2101*
AD7568*
AD7568*
A0
+5V
+5V
CLR
FO
FO
LDAC
TFS
FSIN
DT
SDIN
LDAC
TFS
FSIN
DT
SDIN
SCLK
SCLK
CLR
CLKIN
CLKIN
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7568*
Figure 22. AD7568 to ADSP-2101 Interface
LDAC
AD7568–TMS320C25 Interface
FSIN
Figure 23 shows an interface circuit for the TMS320C25
digital signal processor. The data on the DX pin is clocked
out of the processor’s Transmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST1 register to 0. The transmit operation begins when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting
SDIN
CLKIN
A0
+5V
CLR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Interfacing ADSP-2101 to Two AD7568s
REV. B
–11–
AD7568
68HC11*
AD7568*
(DAC 1)
SDIN
MOSI
PC7
FSIN
SCK
SCLK
PC6
LDAC
MISO
A0
C1565–24–7/91
For systems which contain larger numbers of AD7568s and
where the user also wishes to read back the DAC contents for
diagnostic purposes, the SDOUT pin may be used to daisy
chain several devices together and provide the necessary serial
readback. An example with the 68HC11 is shown in Figure 25.
The routine below shows how four AD7568s would be programmed in such a system. Data is transmitted at the MOSI pin
of the 68HC11. It flows through the input shift registers of the
AD7568s and finally appears at the SDOUT pin of DAC N. So,
the readback routine can be invoked any time after the first four
words have been transmitted (the four input shift registers in the
chain will now be filled up and further activity on the CLKIN
pin will result in data being read back to the microcomputer
through the MISO pin). System connectivity can be verified in
this manner. For a four-device system (32 DACs) a two-line to
four-line decoder is necessary.
SDOUT
SDIN
DECODE LOGIC
AD7568*
(DAC 2)
FSIN
SCLK
LDAC
A0
SDOUT
Note that to program the 32 DACs, 35 transmit operations are
needed. In the routine, three words must be retransmitted. The
first word for DACs #3, #2 and #1 must be transmitted twice in
order to synchronize their arrival at the SDIN pin with A0 going
low.
SDIN
AD7568*
(DAC N)
Table V. Routine for Loading 4 AD7568s Connected As in
Figure 25
FSIN
SCLK
LDAC
A0
SDOUT
Bring PC7 (FSIN) low to allow writing to the AD7568s.
Enable AD7568 #4 (Bring A0 low). Disable the others.
Transmit 1st 16-bit word: Data for DAC H, #4
....
....
Transmit 9th 16-bit word: Data for DAC H, #3
Transmit 9th 16-bit word again: Data for DAC H, #3
Transmit 10th 16-bit word: Data for DAC G, #3
Transmit 11th 16-bit word: Data for DAC F, #3
Enable AD7568 #3, Disable the others.
Transmit 12th 16-bit word: Data for DAC E, #3
....
....
Transmit 17th 16-bit word: Data for DAC H, #2
Transmit 17th 16-bit word again: Data for DAC H, #2
Transmit 18th 16-bit word: Data for DAC G, #2
Enable AD7568 #2, Disable the others.
Transmit 19th 16-bit word: Data for DAC F, #2
....
....
Transmit 25th word: Data for DAC H, #1
Enable AD7568 #1, Disable the others.
Transmit 25th word again: Data for DAC H, #1
Transmit 26th word: Data for DAC G, #1
....
....
Transmit 32nd word: Data for DAC A, #1
Bring PC7 (FSIN) high to disable writing to the AD7568s.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Multi-DAC System
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Pin PQFP
(Suffix S)
0.547 ± 0.01 SQ
(13.9 ± 0.25)
0.394 ± 0.004 SQ
(10 ± 0.1)
0.096 (2.45) MAX
4°± 4°
33
23
34
22
0.394 ± 0.004
(10 ± 0.1)
PRINTED IN U.S.A.
0.031 ± 0.006
(0.8 ± 0.15)
TOP VIEW
PIN 1
44
12
1
0.036 ± 0.004
(0.92 ± 0.1)
0.079 + 0.004/–0.002
(2 + 0.1/–0.05)
–12–
11
0.036 ± 0.004
(0.92 ± 0.1)
0.014 ± 0.002
(0.35 ± 0.05)
0.031 ± 0.002
(0.8 ± 0.05)
REV. B