MOTOROLA MC74LVX4245

SEMICONDUCTOR TECHNICAL DATA
" ! LVX
The 74LVX4245 is a 24–pin dual–supply, octal translating transceiver
that is designed to interface between a 5V bus and a 3V bus in a mixed
3V/5V supply environment such as laptop computers using a 3.3V CPU
and 5V LCD display. The A port interfaces with the 5V bus; the B port
interfaces with the 3V bus.
The Transmit/Receive (T/R) input determines the direction of data flow.
Transmit (active–High) enables data from the A port to the B port.
Receive (active–Low) enables data from the B port to the A port. The
Output Enable (OE) input, when High, disables both A and B ports by
placing them in 3–State.
•
•
•
•
•
LOW–VOLTAGE CMOS
Bi–directional Interface Between 5V and 3V Buses
Control Inputs Compatible with TTL Level
5V Data Flow at A Port and 3V Data Flow at B Port
Outputs Source/Sink 24mA at 5V Bus and 12mA at 3V Bus
DW SUFFIX
24–LEAD PLASTIC SOIC PACKAGE
CASE 751E–04
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
• Available in SOIC and TSSOP Packages
• Functionally Compatible with the 74 Series 245
VCCB VCCB OE
B0
B1
B2
B3
B4
B5
B6
B7
GND
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
A0
A1
A2
A3
A4
A5
A6
A7
DT SUFFIX
24–LEAD PLASTIC TSSOP PACKAGE
CASE 948H–01
PIN NAMES
VCCA T/R
Figure 1. 24–Lead Pinout
(Top View)
GND GND
Pins
Function
OE
T/R
A0–A7
Output Enable Input
Transmit/Receive Input
Side A 3–State Inputs or 3–State
Outputs
Side B 3–State Inputs or 3–State
Outputs
B0–B7
7/97
 Motorola, Inc. 1997
1
REV 2
MC74LVX4245
OE 22
T/R 2
A0
3
21
A1
4
20
A2
B5
9
15
A7
B4
8
16
A6
B3
7
17
A5
B2
6
18
A4
B1
5
19
A3
B0
B6
10
14
B7
Figure 2. Logic Diagram
INPUTS
OE
T/R
OPERATING MODE
Non–Inverting
L
L
B Data to A Bus
L
H
A Data to B Bus
H
X
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level
and Transitions are Acceptable; For ICC reasons, Do Not Float Inputs
MOTOROLA
2
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
MC74LVX4245
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
VCCA, VCCB
DC Supply Voltage
VI
DC Input Voltage
VI/O
DC Input/Output Voltage
Value
Condition
Unit
–0.5 to +7.0
V
OE, T/R
–0.5 to VCCA +0.5
V
An
–0.5 to VCCA +0.5
V
Bn
–0.5 to VCCB +0.5
V
±20
VI < GND
mA
DC Output Diode Current
±50
VO < GND; VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC, IGND
DC Supply Current
±50
±200
±100
mA
TSTG
Storage Temperature Range
–65 to +150
°C
Latchup
DC Latchup Source/Sink Current
±300
mA
IIK
DC Input Diode Current
IOK
OE, T/R
Per Output Pin
Maximum Current at ICCA
Maximum Current at ICCB
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCCA, VCCB
Supply Voltage
VI
Input Voltage
VI/O
Input/Output Voltage
TA
Operating Free–Air Temperature
∆t/∆V
Minimum Input Edge Rate
VIN from 30% to 70% of VCC; VCC at 3.0V, 4.5V, 5.5V
Min
Max
Unit
4.5
2.7
5.5
3.6
V
OE, T/R
0
VCCA
V
An
Bn
0
0
VCCA
VCCB
V
–40
+85
°C
0
8
ns/V
VCCA
VCCB
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
VIHA
Parameter
Minimum HIGH Level
Input Voltage
Condition
An,OE
T/R
VIHB
VILA
Bn
Maximum LOW Level
Input Voltage
An,OE
T/R
VILB
VOHA
Bn
Minimum HIGH Level
Output Voltage
VOHB
VOLA
Maximum LOW Level
Output Voltage
VOLB
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
VCCA
VCCB
5.5
4.5
3.3
3.3
2.0
2.0
2.0
2.0
V
5.0
5.0
3.6
2.7
2.0
2.0
2.0
2.0
V
5.5
4.5
3.3
3.3
0.8
0.8
0.8
0.8
V
5.0
5.0
2.7
3.6
0.8
0.8
0.8
0.8
V
IOUT = –100µA
IOH = –24mA
4.5
4.5
3.0
3.0
4.50
4.25
4.40
3.86
4.40
3.76
V
IOUT = –100µA
IOH = –12mA
IOH = –8mA
4.5
4.5
4.5
3.0
3.0
2.7
2.99
2.80
2.50
2.9
2.4
2.4
2.9
2.4
2.4
V
IOUT = 100µA
IOL = 24mA
4.5
4.5
3.0
3.0
0.002
0.18
0.10
0.36
0.10
0.44
V
IOUT = 100µA
IOL = 12mA
IOL = 8mA
4.5
4.5
4.5
3.0
3.0
2.7
0.002
0.1
0.1
0.10
0.31
0.31
0.10
0.40
0.40
V
VOUT ≤ 0.1V
or
≥ VCC – 0.1V
VOUT ≤ 0.1V
or
≥ VCC – 0.1V
3
Typ
TA = –40 to +85°C
Guaranteed Limits
Unit
MOTOROLA
MC74LVX4245
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
Parameter
Condition
VCCA
VCCB
Typ
TA = –40 to +85°C
Guaranteed Limits
IIN
Max Input Leakage
Current
OE,
T/R
VI = VCCA, GND
5.5
3.6
±0.1
±1.0
IOZA
Max 3–State Output
Leakage
An
VI = VIH, VIL
OE = VCCA
VO = VCCA, GND
5.5
3.6
±0.5
±5.0
Max 3–State Output
Leakage
Bn
VI = VIH, VIL
OE = VCCA
VO = VCCB, GND
5.5
3.6
±0.5
±5.0
Maximum ICCT per
Input
An,OE
T/R
VI=VCCA–2.1V
5.5
3.6
1.35
1.5
Bn
VI=VCCB–0.6V
5.5
3.6
0.35
0.5
IOZB
∆ICC
ICCA
ICCB
1.0
Unit
µA
µA
µA
mA
mA
µA
Quiescent VCCA
Supply Current
An=VCCA or GND
Bn=VCCB or GND
OE=GND
T/R=GND
Quiescent VCCB
Supply Current
An=VCCA or GND
Bn=VCCB or GND
OE=GND
T/R=VCCA
5.5
3.6
5
5.5
3.6
8
80
µA
50
VOLPA
VOLPB
Quiet Output Max
Dynamic VOL
Notes 1., 2.
5.0
5.0
3.3
3.3
1.5
1.2
V
VOLVA
VOLVB
Quiet Output Min
Dynamic VOL
Notes 1., 2.
5.0
5.0
3.3
3.3
–1.2
–0.8
V
VIHDA
VIHDB
Min HIGH Level
Dynamic Input Voltage
Notes 1., 3.
5.0
5.0
3.3
3.3
2.0
2.0
V
VILDA
Max LOW Level
5.0
3.3
0.8
V
Notes 1., 3.
VILDB
Dynamic Input Voltage
5.0
3.3
0.8
1. Worst case package.
2. Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.
3. Max number of data inputs (n) switching. (n–1) inputs switching 0V to VCC level. Input under test switching: VCC level to threshold (VIHD), 0V
to threshold (VILD), f = 1MHz.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCCA = 5.0V; VCCB = 3.3V
4.5
pF
CI/O
Input/Output Capacitance
VCCA = 5.0V; VCCB = 3.3V
15
pF
CPD
Power Dissipation Capacitance
(Measured at 10MHz)
VCCA = 5.0V
VCCB = 3.3V
55
40
pF
MOTOROLA
B→A
A→B
4
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
MC74LVX4245
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
TA = –40 to +85°C
CL = 50pF
TA = –40 to +85°C
CL = 50pF
VCCA = 5V ±0.5V
VCCB = 3.3V ±0.3V
VCCA = 5V ±0.5V
VCCB = 2.7V
Min
Typ
(Note 4.)
Max
Min
Max
Unit
tPHL
tPLH
Propagation Delay A to B
1.0
1.0
5.1
5.3
9.0
9.0
1.0
1.0
10.0
10.0
ns
tPHL
tPLH
Propagation Delay B to A
1.0
1.0
5.4
5.5
9.0
9.0
1.0
1.0
10.0
10.0
ns
tPZL
tPZH
Output Enable Time OE to B
1.0
1.0
6.5
6.7
10.5
10.5
1.0
1.0
11.5
11.5
ns
tPZL
tPZH
Output Enable Time OE to A
1.0
1.0
5.2
5.8
9.5
9.5
1.0
1.0
10.0
10.0
ns
tPHZ
tPLZ
Output Disable Time OE to B
1.0
1.0
6.0
3.3
10.0
7.0
1.0
1.0
10.0
7.5
ns
tPHZ
tPLZ
Output Disable Time OE to A
1.0
1.0
3.9
2.9
7.5
7.0
1.0
1.0
7.5
7.5
ns
tOSHL
ns
Output to Output Skew, Data to Output (Note 5.)
1.0
1.5
1.5
tOSLH
4. Typical values at VCCA = 5.0V; VCCB = 3.3V at 25°C.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
This enables the user to easily replace this level shifter with a
3V ‘245 device without additional layout work or re–
manufacture of the circuit board (when both buses are 3V).
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dual–supply device well capable
of bidirectional signal voltage translation. This level shifting
ability provides an excellent interface between low voltage
CPU local bus and a standard 5V I/O bus. The device control
inputs can be controlled by either the low voltage CPU and
core logic or a bus arbitrator with 5V I/O levels.
LOW VOLTAGE CPU LOCAL BUS
The LVX4245 is ideal for mixed voltage applications such
as notebook computers using a 3.3V CPU and 5V peripheral
devices.
VCCB
LVX4245
Applications:
Mixed Mode Dual Supply Interface Solutions
VCCA
The LVX4245 is designed to solve 3V/5V interfaces when
CMOS devices cannot tolerate I/O levels above their applied
VCC. If an I/O pin of a 3V device is driven by a 5V device, the
P–Channel transistor in the 3V device will conduct — causing
current flow from the I/O bus to the 3V power supply. The
result may be destruction of the 3V device through latchup
effects. A current limiting resistor may be used to prevent
destruction, but it causes speed degradation and needless
power dissipation.
LVX4245
VCCA
EISA – ISA – MCA
(5V I/O LEVELS)
Figure 3. 3.3V/5V Interface Block Diagram
Powering Up the LVX4245
When powering up the LVX4245, please note that if the
VCCB pin is powered–up well in advance of the VCCA pin,
several milliamps of either ICCA or ICCB current will result. If
the VCCA pin is powered–up in advance of the VCCB pin then
only nanoamps of Icc current will result. In actuality the VCCB
can be powered “slightly” before the VCCA without the current
penalty, but this “setup time” is dependent on the power–up
ramp rate of the VCC pins. With a ramp rate of approximately
50mV/ns (50V/µs) a 25ns setup time was observed (VCCB
A better solution is provided in the LVX4245. It provides
two different output levels that easily handle the dual voltage
interface. The A port is a dedicated 5V port; the B port is a
dedicated 3V port. Figure 4 on page 6 shows how the
LVX4245 may fit into a mixed 3V/5V system.
Since the LVX4245 is a ‘245 transceiver, the user may
either use it for bidirectional or unidirectional applications.
The center 20 pins are configured to match a ‘245 pinout.
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
VCCB
5
MOTOROLA
MC74LVX4245
before VCCA). With a 7V/µs rate, the setup time was about
140ns. When all is said and done, the safest power–up
strategy is to simply power VCCA before VCCB. One more
5V
note: if the VCCB ramp rate is faster than the VCCA ramp rate
then power problems might still occur, even if the VCCA
power–up began prior to the VCCB power–up.
MICROCHANNEL/
EISA/ISA/AT
5V BUS
LOCAL
3V BUS
KEYBOARD
CONTROLLER
3V
CACHE
SRAM
SUPER
I/O
5V
VCCA
3V
VCCB
CPU
386/486
CORE
LOGIC
LVX4245
TRANSCEIVERS
A PORT
A0:7
B PORT
B0:7
ROM
BIOS
PCMCIA
CONTROLLER
MEMORY
DRIVER
VGA
CONTROLLER
Figure 4. MC74LVX4245 Fits Into a System with 3V Subsystem and 5V Subsystem
VCCA
MC74LVX4245
(T/R) DIR
VCCB
VCCB
A0
OE
A1
B0
A2
A3
A4
STANDARD
74 SERIES
‘245
B1
B2
B3
A5
B4
A6
B5
A7
B6
GND
B7
GND
GND
Figure 5. MC74LVX4245 Pin Arrangement Is Compatible to 20–Pin 74 Series ‘245s
MOTOROLA
6
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
MC74LVX4245
VCC
An, Bn
50%VCC
50% VCC
0V
tPLH
tPHL
VOH
50% VCC
Bn, An
50% VCC
VOL
WAVEFORM 1 – PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
VCCA
50% VCC
OE, T/R
50% VCC
0V
tPZH
tPHZ
VCC
VOH – 0.3V
50% VCC
An, Bn
≈ 0V
tPZL
tPLZ
≈ VCC
50% VCC
An, Bn
VOL + 0.3V
GND
WAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 6. AC Waveforms
VCC
PULSE
GENERATOR
R1
DUT
CL
RT
TEST
2 × VCC
OPEN
RL
SWITCH
tPLH, tPHL, tPZH, tPHZ
Open
2 × VCC
tPZL, tPLZ
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 7. Test Circuit
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
7
MOTOROLA
MC74LVX4245
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948H–01
ISSUE O
24X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
2X
24
L/2
13
B
–U–
L
PIN 1
IDENT.
12
1
0.15 (0.006) T U
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
A
–V–
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
C
0.10 (0.004)
–T– SEATING
PLANE
G
D
H
–W–
MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
DETAIL E
N
0.25 (0.010)
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
J1
M
N
F
SECTION N–N
DETAIL E
J
MOTOROLA
8
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
MC74LVX4245
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
–A
–
24
13
–B
–
1
P 12 PL
0.010 (0.25)
M
B
M
12
J
D 24 PL
0.010 (0.25)
M
T A
S
B
S
F
R X 45°
C
–T
–
SEATING
PLANE
K
G 22 PL
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25 15.54
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8°
0°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.601 0.612
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
0°
8°
0.395 0.415
0.010 0.029
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
◊
9
MC74LVX4245/D
MOTOROLA