FAIRCHILD 74LVQ08SJ

74LVQ08
Low Voltage Quad 2-Input AND Gate
General Description
Features
The LVQ08 contains four, 2-input AND gates.
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
Package Number
Package Description
74LVQ08SC
M14A
14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC
74LVQ08SJ
M14D
14-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Assignment
for SOIC JEDEC and EIAJ
DS011344-1
DS011344-2
Pin Descriptions
Pin Names
© 1998 Fairchild Semiconductor Corporation
DS011344
Description
An, Bn
Inputs
On
Outputs
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74LVQ08 Low Voltage Quad 2-Input AND Gate
April 1998
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
Recommended Operating
Conditions (Note 2)
−0.5V to +7.0V
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
VCC @ 3.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
2.0V to 3.6V
0V to VCC
0V to VCC
−40˚C to +85˚C
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
± 50 mA
± 200 mA
−65˚C to +150˚C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
± 100 mA
DC Electrical Characteristics
Parameter
VCC
(V)
Minimum High Level
3.0
Symbol
TA = +25˚C
TA = −40˚C to +85˚C
Typ
VIH
1.5
Units
Guaranteed Limits
2.0
2.0
V
Maximum Low Level
VOUT = 0.1V
or VCC − 0.1V
Input Voltage
VIL
Conditions
3.0
1.5
2.99
0.8
0.8
V
VOUT = 0.1V
Input Voltage
VOH
2.9
2.9
V
IOUT = −50 µA
2.58
2.48
V
VIN = VIL or VIH (Note 3)
0.1
0.1
V
IOUT = 50 µA
3.0
0.36
0.44
V
VIN = VIL or VIH (Note 3)
3.6
± 0.1
± 1.0
µA
VI = VCC, GND
Minimum High Level
3.0
Output Voltage
3.0
Maximum Low Level
3.0
Output Voltage
Maximum Input
IOH = −12 mA
VOL
0.002
IOL = 12 mA
IIN
Leakage Current
IOLD
Minimum Dynamic
3.6
36
mA
VOLD = 0.8V Max (Note 5)
IOHD
Output Current (Note 4)
3.6
−25
mA
VOHD = 2.0V Min (Note 5)
ICC
Maximum Quiescent
3.6
20.0
µA
2.0
Supply Current
VOLP
Quiet Output
VIN = VCC
or GND
3.3
0.4
0.8
V
(Notes 6, 7)
3.3
−0.4
−0.8
V
(Notes 6, 7)
3.3
1.8
2.0
V
(Notes 6, 8)
3.3
1.8
0.8
V
(Notes 6, 8)
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
VIHD
Maximum High Level
Dynamic Input Voltage
VILD
Maximum Low Level
Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
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2
AC Electrical Characteristics
Symbol
tPLH
tPHL
VCC
(V)
Parameter
Propagation Delay
Propagation Delay
tOSHL
Output to Output Skew
tOSLH
(Note 9)
TA = +25˚C
TA = −40˚C to +85˚C
CL = 50 pF
CL = 50 pF
Units
Min
Typ
Max
Min
2.7
1.5
9.0
13.4
1.0
Max
14.0
3.3 ± 0.3
1.5
7.5
9.5
1.0
10.0
2.7
1.5
8.4
12.0
1.0
13.0
3.3 ± 0.3
1.5
7.0
8.5
1.0
9.0
2.7
1.0
1.5
1.5
3.3 ± 0.3
1.0
1.5
1.5
ns
ns
ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = Open
Conditions
CPD (Note 10)
Power Dissipation Capacitance
17
pF
VCC = 3.3V
Note 10: CPD is measured at 10 MHz.
3
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4
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead (0.150" Wide) Small Outline Package, SOIC JEDEC
Package Number M14A
14-Lead Molded Small Outline Package, SOIC EIAJ
Package Number M14D
5
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74LVQ08 Low Voltage Quad 2-Input AND Gate
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device or system, or to affect its safety or effectiveness.
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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