MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms Order this document by MPC2104P/D MPC2104P MPC2105P The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2104P and MPC2105P utilize synchronous BurstRAMs. The MPC2104P module is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs. The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 data RAMs. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the 2104P, a 5 V cache tag RAM configured as 8K x 14 for tag field plus 8K x 2 for valid and dirty status bits is used. For tag bits on the 2105P, a 5 V cache tag RAM configured as 16K x 14 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internally to the BurstRAM by the CNTEN signal. Write cycles are internally self–timed and are initiated by the rising edge of the clock (CLKx) inputs. Writes are global with two inputs for reduced loading. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. • • • • • • • • • • • • • PowerPC–Style Burst Counter On Chip Pipeline Data I/O Plug and Pin Compatibility Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible Three State Outputs Buffered Addresses to Data RAMs for Reduced Loading Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 9 ns for Tag RAM Match 8 ns for Data RAM Decoupling Capacitors for Each Fast Static RAM High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes 178 Pin Card Edge Module Burndy Connector, Part Number: ELF178KSC–3Z50 BurstRAM is a trademark of Motorola. The PowerPC name is a trademark of IBM Corp., used under license therefrom. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 2 12/20/96 Motorola, Inc. 1996 MOTOROLA FAST SRAM MPC2104P•MPC2105P 1 MPC2104P BLOCK DIAGRAM 32K x 32 SRAM 16244 A28 A27 A14 – A26 ADS0 CNTEN0 VSS CG0 CLK0 VDD VSS VDD via 100Ω SGW SA0 SA1 SW SA SBa – SBd ADSC ADV SE1 G DQa – DQd K VDD LBO SE3 ZZ SE2, ADSP CWE0 VDD DH0 – DH31 BURSTMODE STANDBY 32K x 32 SRAM CLK1 VDD VSS VDD via 100Ω 22 Ω A14 – A26 A0 – A13 TCLR TWE 22 Ω CLK2 MATCH DIRTYOUT 22 Ω MPC2104P•MPC2105P 2 VALIDIN DIRTYIN TG SGW SA0 SA1 SW SA SBa – SBd ADSC ADV SE1 G DQa – DQd K VDD LBO SE3 ZZ SE2, ADSP TAG: 16K x 14 + V + D A0 – A12 TT1, E1 TDQ0 – TDQ13 SFUNC, GS, A13 RESET TAH, TAG, TAD WS E2, PWRDN WT VCC VCCQ K MATCH TA, VALIDQ DIRTYQ VALIDD DIRTYD GT CWE1 VDD DL0 – DL31 BURSTMODE STANDBY VSS VCC via 100 Ω VCC VDD NC PD3 J3 PD2 J2 PD1 J1 PD0 J0 MOTOROLA FAST SRAM MPC2105P BLOCK DIAGRAM 64K x 32 SRAM 16244 A28 A27 A13 – A26 ADS0 CNTEN0 VSS CG0 CLK0 VDD VSS VDD via 100Ω SGW SA0 SA1 SW SA SBa – SBd ADSC ADV SE1 G DQa – DQd K VDD LBO SE3 ZZ SE2, ADSP CWE0 VDD DH0 – DH31 BURSTMODE STANDBY 64K x 32 SRAM CLK1 VDD VSS VDD via 100Ω 22Ω A13 – A26 A0 – A12 TCLR TWE 22Ω MATCH DIRTYOUT 22Ω CLK2 VALIDIN DIRTYIN TG MOTOROLA FAST SRAM SGW SA0 SA1 SW SA SBa – SBd ADSC ADV SE1 G DQa – DQd K VDD LBO SE3 ZZ SE2, ADSP TAG: 16K x 14 + V + D A0 – A13 TT1, E1 TDQ0 – TDQ12 SFUNC, GS RESET TAH, TAG, TAD WS E2, PWRDN WT VCC VCCQ K MATCH TA, VALIDQ DIRTYQ TDQ13 VALIDD DIRTYD GT CWE1 VDD DL0 – DL31 BURSTMODE STANDBY VSS VCC via 100 Ω VCC VDD NC 4.7KΩ PD3 J3 PD2 J2 PD1 J1 PD0 J0 VSS MPC2104P•MPC2105P 3 PIN ASSIGNMENT 178–LEAD DIMM Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VSS 27 DH0 53 DL1 79 VSS 105 DH14 131 DL17 157 A22 2 PD0/IDSCLK 28 NC 54 DL0 80 A7 106 DH13 132 NC 158 A20 3 PD2 29 VSS 55 VSS 81 A5 107 NC 133 DL15 159 VSS 4 DH30 30 CLK1 56 CLK2 82 A3 108 DH10 134 DL13 160 A18 5 DH28 31 VSS 57 VSS 83 A0 109 DH8 135 VSS 161 A16 6 DH26 32 DL28 58 NC 84 VCC 110 NC 136 DL10 162 A15 7 DH24 33 DL26 59 CG0 85 TCLR 111 DH6 137 DL8 163 A14 8 VDD 34 DL24 60 NC 86 MATCH 112 VDD 138 CWE1 164 VDD 9 NC 35 NC 61 VDD 87 TG 113 DH4 139 DL6 165 A10 10 DH22 36 NC 62 NC 88 DIRTYIN 114 VSS 140 VDD 166 A8 11 DH20 37 DL22 63 RESERVED 89 VSS 115 CLK0 141 DL5 167 A6 12 DH19 38 DL20 64 ADS0 90 VSS 116 VSS 142 DL2 168 VSS 13 VSS 39 DL18 65 NC 91 PD1/IDSDATA 117 DH1 143 VSS 169 A4 14 DH17 40 DL16 66 A28 92 PD3 118 NC 144 NC 170 A2 15 NC 41 VSS 67 A26 93 DH31 119 DL31 145 VSS 171 A1 16 DH15 42 NC 68 A25 94 DH29 120 DL30 146 NC 172 BURSTMODE 17 DH12 43 DL14 69 A23 95 DH27 121 VSS 147 VSS 173 VCC 18 NC 44 DL12 70 VSS 96 DH25 122 DL29 148 CWE0 174 VALIDIN 19 DH11 45 DL11 71 A21 97 VDD 123 DL27 149 NC 175 TWE 20 DH9 46 VSS 72 A19 98 NC 124 DL25 150 VDD 176 STANDBY 21 NC 47 DL9 73 A17 99 DH23 125 NC 151 NC 177 DIRTYOUT 22 DH7 48 NC 74 A13 100 DH21 126 NC 152 RESERVED 178 VSS 23 VDD 49 DL7 75 VDD 101 DH18 127 DL23 153 CNTEN0 24 DH5 50 DL4 76 A12 102 VSS 128 DL21 154 NC 25 DH3 51 VDD 77 A11 103 DH16 129 DL19 155 A27 26 DH2 52 DL3 78 A9 104 NC 130 VSS 156 A24 NOTE: VCC and VDD must be connected on all modules. TOP VIEW – CASE TBD MPC2104P•MPC2105P 4 90 1 131 42 132 43 154 65 155 66 178 89 MOTOROLA FAST SRAM PIN DESCRIPTIONS Pin Locations Symbol Type 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 A0 – A28 Input Address Inputs — (MSB:0, LSB:28). 64 ADS0 Input Data RAM Address Strobe. 172 BURSTMODE Input Burstmode. 0 = Linear, 1 = Interleaved. 59 CG0 Input Data RAM Output Enable. 30, 56, 115 CLK0 – CLK2 Input Clock Inputs — CLK2 is for Tag RAM, CLK0 and CLK1 are for Data RAMs only. Description 153 CNTEN0 Input Data RAM Count Enable. 138, 148 CWE0 – CWE1 Input Data RAM Write Enables — (MSB:0, LSB:1). 4, 5, 6, 7, 10, 11, 12, 14, 6, 17, 19, 20, 22, 24, 25, 26, 27, 93, 94, 95, 96, 99, 100, 101, 103, 105, 106, 108, 109, 111, 113, 117 DH0 – DH31 I/O 88 DIRTYIN Input 177 DIRTYOUT Output 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 119, 120, 122, 123, 124, 127, 128, 129, 131, 133, 134, 136, 137, 139, 141, 142 DL0 – DL31 I/O 86 MATCH Output High Data Bus — (MSB:0, LSB:31). Dirty input bit. Dirty output bit. Low Data Bus — (MSB:0, LSB:31). Tag RAM active high match indication. 2 PD0/IDSCLK Input Presence detect bit 0/EEPROM serial clock. (EEPROM option only). 91 PD1/IDSDATA I/O Presence detect bit 1/EEPROM serial data. (EEPROM option only). 3, 92 PD2, PD3 Output 63, 152 RESERVED 176 STANDBY Input Standby pin. Reduces standby power consumption. 85 TCLR Input Tag RAM clear. 87 TG Input Tag RAM output enable. 175 TWE Input Tag RAM write enable. 174 VALIDIN Input Tag RAM valid bit. 84, 173 VCC Input + 5 V power supply. Must be connected. 8, 23, 51, 61, 75, 97, 112, 140, 150, 164 VDD Input + 3.3 V power supply. Must be connected. 1, 13, 29, 31, 41, 46, 55, 57, 70, 79, 89, 90, 102, 114, 116, 121, 130, 135, 143, 145, 147, 159, 168, 178 VSS Input Ground. 9, 15, 18, 21, 28, 35 – 36, 42, 48, 58, 60, 62, 65, 98, 104, 107, 110, 118, 125 – 126, 132, 144, 146, 149, 151, 154 NC — MOTOROLA FAST SRAM Presence detect bits. Reserved pin. There is no connection to the module. MPC2104P•MPC2105P 5 TRUTH TABLE (See Notes 1 through 4) Address Used Standby ADS0 CNTEN0 CG0 2 DHx/DLx CWEx 2 None 1 0 X X High–Z X External 0 0 X X High–Z 14 Next X 1 0 1 High–Z 1 Continue Read Next X 1 0 0 DQ 1 Suspend Read Current X 1 1 1 High–Z 1 Suspend Read Current X 1 1 0 DQ 1 Begin Write External 0 0 X X High–Z 0 Continue Write Next X 1 0 X High–Z 0 Suspend Write Current X 1 1 X High–Z 0 Next Cycle Deselect Begin Read Continue Read NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low. 2. CG0 is an asynchronous signal and is not sampled by the clock CLK0. CG0 drives the bus immediately (tGLQX) following CG0 going low. 3. On write cycles that follow read cycles, CG0 must be negated prior to the start of the write cycle to ensure proper write data setup times. CG0 must also remain negated at the completion of the write cycle to ensure proper write data hold times. 4. This READ assumes the RAM was previously deselected. ASYNCHRONOUS TRUTH TABLE Operation CG0 I/O Status Read L Data Out (DHx/DLx) Read H High–Z Write X High–Z Deselected X High–Z Sleep X High–Z LINEAR BURST ADDRESS TABLE (Burst Mode = VSS) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 INTERLEAVED BURST ADDRESS TABLE (Burst Mode = VDD) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 MPC2104P•MPC2105P 6 MOTOROLA FAST SRAM ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage Tag Data RAM VCC VDD – 0.5 to + 7.0 – 0.5 to + 4.6 V Voltage Relative to VSS Tag Data RAM Vin, Vout – 0.5 to VCC + 0.5 – 0.5 to VDD + 0.5 V Output Current (per I/O) Tag Data RAM Iout ± 20 ± 30 mA PD 3.86 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Power Dissipation This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, VDD = 3.3 V + 10%, – 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC VDD 4.75 3.135 5.25 3.60 V Input High Voltage VIH 2.2 VDD + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(I) — ± 1.0 µA Output Leakage Current (CG = VIH, Vout = 0 to VDD) * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Parameter Ilkg(O) — ± 1.0 µA TTL Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V TTL Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol Max Unit IDDA 410 700 mA POWER SUPPLY CURRENTS Parameter AC Supply Current (CG = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) MPC2104P MPC2105P ICCA 320 mA ISB1 (VDD) 210 240 mA ISB1 (VCC) 320 mA Symbol Max Unit Cin 15 10 5 5 pF (MATCH, DIRTYOUT) Cout 7 pF (DH0 – DH31, DL0 – DL31) CI/O 8 pF (A0 – A11) CI/O 7 pF MPC2104P MPC2105P CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Tag Output Capacitance Data RAM Input/Output Capacitance Tag Input/Output Capacitance MOTOROLA FAST SRAM (A13 – A28) (Data RAM Control Pins) (CLK0 – CLK2) (Tag Control Pins) MPC2104P•MPC2105P 7 DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, VDD = 3.3 V + 10%, – 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1 and 2) MPC2104P/5P P Parameter S b l Symbol Min Max U i Unit Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 8 ns Output Enable to Output Valid tGLQV — 6 ns Clock High to Output Active tKHQX1 0 — ns Clock High to Output Change tKHQX2 2 — ns Output Enable to Output Active tGLQX 0 — ns Output Disable to Q High–Z tGHQZ — 8 ns Clock High to Q High–Z tKHQZ 2 8 ns Clock High Pulse Width tKHKL 5 — ns Clock Low Pulse Width tKLKH 5 — ns N Notes 3 Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tSVKH tDVKH tWVKH tBAVVKH tEVKH 2.5 — ns 4 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX 0.5 — ns 4 NOTES: 1. All read and write cycle timings are referenced from CLK or CG0. 2. CG is a don’t care when CWEx is sampled low. 3. Maximum access times are guaranteed for all possible PowerPC external bus cycles. 4. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever ADS0 is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADS0 is low) to remain enabled. MPC2104P•MPC2105P 8 MOTOROLA FAST SRAM MOTOROLA FAST SRAM MPC2104P•MPC2105P 9 DQx COE0 Q(n–1) DESELECTED tKHQZ CWEx STANDBY CNTEN0 ADS0 A14 – A26 CLKx B SINGLE READ tKHQX1 A tKHKH Q(A) Q(B) tKHQX2 t KHQV tKHKL Q(B+3) tGHQZ Q(B+2) BURST READ Q(B+1) tKLKH READ/WRITE CYCLES D(C) C D(C+2) BURST WRITE D(C+1) D(C+3) t KHQV SINGLE WRITE D(D) D TAG RAM RESET FUNCTION TRUTH TABLE (See Notes 1 and 2) TCLR CLK TWE TAG0 – TAG11 DIRTYOUT MATCH Operation POWER L(3) Reset Status Active — Not Allowed — L L–H H High–Z L(3) L L–H L — — NOTES: 1. H = VIH, L = VIL, X = don’t care, — = undefined. 2. TG is X for this table. 3. These are output states. READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3) TG TWE CLK TAG0 – TAG11 VALIDIN DIRTYIN DIRTYOUT MATCH Operation L H X Dout — — Dout Dout Read Tag I/O H X X High–Z — — — — Tag I/O Disable WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2) TG TWE CLK TAG0 – TAG11 VALIDIN DIRTYIN DIRTYOUT MATCH Operation H L L–H Din — — — L Write Tag I/O L L L–H — — — — — Not Allowed NOTES: 1. H = VIH, L = VIL, X = don’t care, — = undefined. 2. This table applies when RESET and PWRDN are high. 3. Dout in this case is the same as Din. The input data is written through to the outputs during the write operation. MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4) TG TWE TAG0 – TAG11 VALIDIN(4) DIRTYIN(4) MATCH Operation X X — — — Dout Selected L H Dout — — L Read Tag I/O H L Din Din Din L Write Tag I/O, Status Bits H H TAGin L — L Invalid Data — Dedicated Status Bits H H TAGin H — H Match — Dedicated Status Bits NOTES: 1. H = VIH, L = VIL, X = don’t care, — = undefined. 2. M = high if TAGin equals the memory contents at the address; M = low if TAGin does not equal the contents at that address. 3. PWRDN and RESET are high for this table. GS and CLK are X. 4. This column represents the stored memory cell data for the given status bit at the selected address. MPC2104P•MPC2105P 10 MOTOROLA FAST SRAM TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted TAG RAM READ CYCLE (See Notes 1 through 4) Tag RAM P Parameter S b l Symbol Min Max U i Unit Clock Access Time tKHQV — 10 ns Output Enable to Output Valid tGLQV — 8 ns Output Enable to Output Active tGLQX 0 — ns Output Disable to Q High–Z tGHQZ 1 6 ns Status Bit Hold from Address Change tAXSX 3 — ns Address Access Time Status Bits tAVSV — 10 ns Tag Bit Hold from Address Change tAVQX 3 — ns Address Access Time Tag Bits tAVQV — 12 ns NOTES: 1. Setup and hold times, W (write) refers to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag reads are asynchronous. TAG RAM WRITE CYCLE (See Notes 1 through 4) Tag RAM P Parameter S b l Symbol Min Max U i Unit Cycle Time tKHKH 15 — ns Clock High Pulse Width tKHKL 4.5 — ns Clock Low Pulse Width tKLKH 4.5 — ns Clock High to Output Active tKHQX 1.5 — ns Setup Times Address Write tAVKH tWVKH 3 — ns Hold Times Address Write tKHAX tKHWX 1.5 — ns Status Output Hold tKHSX 0 — ns Clock High to Status Bits Valid tKHSV — 9 ns NOTES: 1. Setup and hold times, W (write) refers to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag writes are synchronous. MOTOROLA FAST SRAM MPC2104P•MPC2105P 11 MPC2104P•MPC2105P 12 MOTOROLA FAST SRAM DIRTYOUT VALIDIN DIRTYIN A0 – A13 TG TWE A14 – A26 CLK t WVKH t AVKH t WVKH t AVKH VALID t KHWX t KHAX t KHWX t WVKH t KHAX t KHKH t KHSV VALID INPUT VALID t KHSX t KLKH NOTES: 1. Transition is measured plus or minus 200 mV from steady state. 2. TCLR = High. t KHKL STATUS WRITE TAG WRITE VALID t AXSX t AVSV t KHQX (SEE NOTE 1) t KHQV t KHWX TAG READ AFTER WRITE (SEE NOTE 1) t GHQZ VALID VALID OUTPUT VALID TAG RAM WRITE AND READ CYCLES(See Note 2) t GLQX t GLQV VALID VALID OUTPUT VALID t AVSV t AXSX t AXQX t AVQV TAG READ AFTER READ VALID VALID OUTPUT TAG RAM MATCH CYCLE Tag RAM P Parameter S b l Symbol Min Max U i Unit Clock High Write to MATCH Invalid tKHML — 7 ns Clock High Read to MATCH Valid tKHMV — 10 ns Address Valid to MATCH Valid tAVMV — 10 ns MATCH Valid Hold from Address Change tAXMX 2 — ns TG Low to MATCH Invalid tGLML — 7 ns TG High to MATCH Valid tGHMX — 8 ns TAG RAM RESET (TCLR) CYCLE Tag RAM P Parameter S b l Symbol Min Max U i Unit TCLR Setup Time tSTC 4 — ns TCLR Hold Time tHTC 1 — ns Status Bit Reset Time tSRST — 60 ns Status Bit Hold from TCLR Low tSHRS 2 — ns TCLR Low to MATCH Invalid tRSML — 10 ns TCLR High to MATCH Valid tRSMV — 100 ns TCLR Low to TAG High–Z tRSQZ — 10 ns TCLR High to TAG Active tRSQX — 100 ns STANDBY Setup to TCLR Low tPDSR 30 — ns TCLR High to TWE Low tRHWX 80 — ns TIMING LIMITS +5 V 480 Ω Z0 = 50 Ω OUTPUT OUTPUT 50 Ω 255 Ω 5 pF VL = 1.5 V (a) (b) The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. Test Loads MOTOROLA FAST SRAM MPC2104P•MPC2105P 13 MPC2104P•MPC2105P 14 MOTOROLA FAST SRAM VALID t AVMV t AXMX MATCH VALID t KHML t KHWX t WVKH t KHMV t KHWX t WVKH VALID MATCH DATA FROM: PROCESSOR *Cache addresses used are: A14 – A26 for MPC2104P. MATCH TG TWE A0 – A13 A14 – A26* CLK VALID t GLML t WVKH VALID ADDRESS TAG RAM MATCH CYCLE TAG RAM VALID t GLMX PROCESSOR TAG RAM TCLR FUNCTION CLK tHTC tSTC TCLR tSHRS tSRST DIRTYOUT tRHWX tWVKH TWE tRSMV MATCH VALID tRSQZ* tRSQX A0 – A13 * Transition is measured plus or minus 200 mV from steady state. ORDERING INFORMATION (Order by Full Part Number) MPC 2104P 2105P XX XX Motorola Memory Prefix Speed (66 = 66 MHz) Part Number Package (DG = Gold Pad DIMM) Full Part Numbers — MPC2104PDG66 MPC2105PDG66 MOTOROLA FAST SRAM MPC2104P = 256KB, synchronous pipelined MPC2105P = 512KB, synchronous pipelined MPC2104P•MPC2105P 15 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 5405, Denver, Colorado, 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] — TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MPC2104P•MPC2105P 16 ◊ MPC2104P/D MOTOROLA FAST SRAM