PHILIPS UMA1015AM

INTEGRATED CIRCUITS
DATA SHEET
UMA1015AM
Low-power dual frequency
synthesizer for radio
communications
Product specification
Supersedes data of 1997 Jun 10
File under Integrated Circuits, IC17
1997 Sep 03
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
FEATURES
GENERAL DESCRIPTION
• Two fully programmable RF dividers up to 1.1 GHz
The UMA1015AM is a low-power dual frequency
synthesizer for radio communications which operates in
the 50 to 1100 MHz frequency range. Each synthesizer
consists of a fully programmable main divider, a phase and
frequency detector and a charge pump. There is a fully
programmable reference divider common to both
synthesizers which operates up to 35 MHz.
• Fully programmable reference divider up to 35 MHz
• 2 : 1 or 1 : 1 ratio of selectable reference frequencies
• Fast three-line serial bus interface
• Adjustable phase comparator gain
• Programmable out-of-lock indication for both loops
The device is programmed via a 3-wire serial bus which
operates up to 10 MHz. The charge pump currents (gains)
are fixed by an external resistance at pin 20 (ISET).
The BiCMOS device is designed to operate from 2.7 V
(3 NiCd cells) to 5.5 V at low current. Digital supplies VDD1
and VDD2 must be at the same potential. The charge pump
supply (VCC) can be provided by an external source or
on-chip voltage doubler. VCC must be equal to or higher
than VDD1.
• On-chip voltage doubler
• Low current consumption from 3 V supply
• Separate power-down mode for each synthesizer
• Up to 4 open-drain output ports
• Crystal input frequency signal inverted and buffered
output on separate pin.
APPLICATIONS
Each synthesizer can be powered-down independently via
the serial bus to save current. It is also possible to
power-down the device via the HPD input (pin 5).
• Cordless telephone
• Hand-held mobile radio.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD1, VDD2
digital supply voltage
2.7
−
5.5
V
VCC
charge pump supply voltage external supply; doubler
disabled; VCC ≥ VDD
2.7
−
6.0
V
VCCvd
charge pump supply from
voltage doubler
doubler enabled
−
2VDD1 − 0.6 6.0
V
IDD1 + IDD2 + ICC operating supply current
both synthesizers ON; doubler
disabled; VDD1 = VDD2 = 3 V
−
8.7
−
mA
IDDpd + ICCpd
total current in power-down
mode
doubler disabled;
VDD1 = VDD2 = 3 V
−
3
−
µA
IDDpd
current in power-down mode doubler enabled;
from supply VDD1 and VDD2 VDD1 = VDD2 = 3 V
−
0.25
−
mA
fRF
RF input frequency for each
synthesizer
50
−
1100
MHz
fXTALIN
crystal input frequency
3
−
35
MHz
fpc(min)
minimum phase comparator
frequency
−
10
−
kHz
fpc(max)
maximum phase
comparator frequency
−
750
−
kHz
Tamb
operating ambient
temperature
−30
−
+85
°C
1997 Sep 03
VDD1 = VDD2
2
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
UMA1015AM
SSOP20
DESCRIPTION
VERSION
plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
BLOCK DIAGRAM
VDD1
handbook, full pagewidth
4
CLK
DATA
VDD2
DGND
7
14
AGND
ISET
16
20
VCC
18
11
12
4-BIT SHIFT
REGISTER
17-BIT SHIFT REGISTER
PUMP
BIAS
VOLTAGE
DOUBLER
CONTROL LATCH
E
13
ADDRESS
DECODER
VDB enable
RF/64
power OOL current
down select ratio
port
bits
LATCH
RFA
6
LOCK
DETECTOR
5
SYNTHESIZER A
10
fXTALO
fXTALIN
CPA
RFA/64
TOOL A
HPD
3
PHASE
DETECTOR
MAIN DIVIDER
phase
error
TOOL A
LATCH
8
SR
UMA1015AM
LOCK
SELECT
DIV
BY 2
REFERENCE DIVIDER
SYNTHESIZER B
19
1
2
TOOL B
LOCK
DETECTOR
9
P0/OOL
P1
P2
P3
phase
error
LATCH
RFB
15
PHASE
DETECTOR
MAIN DIVIDER
TOOL B
17
RFB/64
MGG523
Fig.1 Block diagram.
1997 Sep 03
3
CPB
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
PINNING
SYMBOL
PIN
DESCRIPTION
P1
1
output Port 1
P2
2
output Port 2
CPA
3
charge pump output synthesizer A
VDD1
4
digital supply voltage 1
HPD
5
hardware power-down
(input LOW = power-down)
RFA
6
RF input synthesizer A
DGND
7
digital ground
fXTALIN
8
common crystal frequency input from
TCXO
P3
9
output Port 3
fXTALO
10
open-drain output of fXTAL signal
CLK
11
programming bus clock input
DATA
12
programming bus data input
E
13
programming bus enable input
(active LOW)
VDD2
14
digital supply voltage 2
RFB
15
RF input synthesizer B
AGND
16
analog ground to charge pumps
CPB
17
charge pump output synthesizer B
VCC
18
analog supply to charge pump;
external or voltage doubler output
P0/OOL
19
Port output 0/out-of-lock output
ISET
20
regulator pin to set charge pump
currents
handbook, halfpage
1
20 ISET
P2
2
19 P0/OOL
CPA
3
18 VCC
VDD1
4
17 CPB
HPD
5
16 AGND
UMA1015AM
RFA
6
15
RFB
DGND
7
14
VDD2
fXTALIN
8
13
E
P3
9
12
DATA
fXTALO 10
11 CLK
MGG522
Fig.2 Pin configuration.
divider. This clock signal is also inverted and output on pin
fXTALO (open drain). A crystal connected between fXTALIN
and fXTALO with suitable feedback components can be
used to make an oscillator. An extra divide-by-2 block
allows a reference comparison frequency for
synthesizer B to be half the frequency of synthesizer A.
This feature is selectable using the program bit SR. If the
programmed reference divider ratio is R then the ratio for
each synthesizer is as given in Table 1.
FUNCTIONAL DESCRIPTION
Main dividers
Each synthesizer has a fully programmable 17-bit main
divider. The RF input drives a pre-amplifier to provide the
clock to the first divider bit. The pre-amplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from below
50 mV (RMS) up to 250 mV (RMS), and at frequencies up
to 1.1 GHz. The high frequency sections of the divider are
implemented using bipolar transistors, while the slower
section uses CMOS technology. The range of division
ratios is 512 to 131071.
The range for the division ratio R is 8 to 4095. Opposite
edges of the divider output are used to drive the phase
detectors to ensure that active edges arrive at the phase
detectors of each synthesizer at different times. This
minimizes the potential for interference between the
charge pumps of each loop. The reference divider consists
of CMOS devices operating beyond 35 MHz.
Reference divider
There is a common fully programmable 12-bit reference
divider for the two synthesizers. The input fXTALIN drives a
pre-amplifier to provide the clock input for the reference
1997 Sep 03
P1
4
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
Table 1
An out-of-lock condition is flagged when the phase error is
greater than TOOL, which is approximately 30 ns.
The out-of-lock flag is only released after the first reference
cycle where the phase error is less than TOOL.
The out-of-lock function can be disabled, via the serial bus,
and the pin P0/OOL can be used as a port output. Three
other port outputs P1, P2 and P3 (open-drain transistors)
are also available.
Synthesizer ratio of reference divider
SR
SYNTHESIZER A
SYNTHESIZER B
0
R
R
1
R
2R
Phase comparators
For each synthesizer, the outputs of the main and
reference dividers drive a phase comparator where a
charge pump produces phase error current pulses for
integration in an external loop filter. The charge pump
current is set by an external resistance RSET at pin ISET,
where a temperature-independent voltage of 1.1 V is
generated. RSET should be between 12 and 60 kΩ.
The charge pump current, ICP, can be programmed to be
either (12 × ISET) or (24 × ISET) with a maximum of 2.3 mA.
The dead zone, caused by finite switching of current
pulses, is cancelled by an internal delay in the phase
detector thus giving improved linearity. The charge pump
has a separate supply, VCC, which helps to reduce the
interference on the charge pump output from other parts of
the circuit. VCC can be higher than VDD1 if a wider range on
the VCO input is required. VCC must not be less than VDD1.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable).
The data sent to the device is loaded in bursts framed
by E. Programming clock edges are ignored until E goes
active LOW. The programmed information is loaded into
the addressed latch when E returns inactive (HIGH). This
is allowed when CLK is in either state without causing any
consequences to the register data. Only the last 21 bits
serially clocked into the device are retained within the
programming register. Additional leading bits are ignored,
and no check is made on the number of clock pulses.
The fully static CMOS design uses virtually no current
when the bus is inactive. It can always capture new
programming data even during power-down of both
synthesizers.
Voltage doubler
However when either synthesizer A or synthesizer B or
both are powered-on, the presence of a TCXO signal is
required at pin 8 (fXTALIN) for correct programming.
If required, there is a voltage doubler on-chip to supply the
charge pumps at a higher level than the nominal available
supply. The doubler operates from the digital supply VDD1,
and is internally limited to a maximum output of 6 V.
An external capacitor is required on pin VCC for smoothing,
the capacitor required to develop the extra voltage is
integrated on-chip. To minimize the noise being introduced
to the charge pump output from the voltage doubler, the
doubler clock is suppressed (provided both loops are
in-lock) for the short time that the charge pumps are active.
The doubler clock (RF/64) is derived from whichever main
divider is operating (synthesizer A has priority). While both
synthesizers are powered down (and the doubler is
enabled), the doubler clock is supplied by a low-current
internal oscillator. The doubler can be disabled by
programming the bit VDON to logic 0, in order to allow an
external charge pump supply to be used.
Data format
Data is entered with the most significant bit first.
The leading bits make up the data field, while the trailing
four bits are an address field. The address bits are
decoded on the rising edge of E. This produces an internal
load pulse to store the data in the addressed latch.
To ensure that data is correctly loaded on first power-up,
E should be held LOW and only taken HIGH after having
programmed an appropriate register. To avoid erroneous
divider ratios, the pulse is inhibited during the period when
data is read by the frequency dividers. This condition is
guaranteed by respecting a minimum E pulse width after
data transfer. The data format and register bit allocations
are shown in Table 2.
Out-of-lock indication/output ports
There is a common lock detector on-chip for the
synthesizers. The lock condition of each, or both loops, is
output via an open-drain transistor which drives
pin P0/OOL (when out-of-lock, the transistor is turned on
and therefore the output is forced LOW). The lock
condition output is software selectable (see Table 4).
1997 Sep 03
UMA1015AM
5
FIRST
REGISTER BIT ALLOCATION
p1
p2
p3
p4
p5
p6
dt16
dt15 dt14
X
X
VDON PO
OLA OLB CRA CRB X
p8
p13
p14
p15
p16
p17
dt4
dt3
dt2
dt1
dt0
sPDA sPDB P3
P2
P1
X
X
0
0
0
1
0
0
SR
SYNTHESIZER A MAIN DIVIDER COEFFICIENT
MA0
0
1
0
0
R11
R0
0
1
0
1
MB0
0
1
1
0
0
0
0
0
1
0
0
0
dt13 dt12
MA16
0
p7
0
MB16
p9
p10
p12
DATA FIELD
X
REFERENCE DIVIDER COEFFICIENT
SYNTHESIZER B MAIN DIVIDER COEFFICIENT
RESERVED FOR
0
p11
LAST
0
0
0
0
0
0
0
0
TEST(1)
0
0
0
0
0
sPBF 0
Note
1. The test register should not be programmed with any other values except all zeros for normal operation.
Table 3
Bit allocation description
SYMBOL
DESCRIPTION
sPDA, sPDB
software power-down for synthesizers A and B (0 = power-down)
6
sPBF
software power-on for fxtal buffer (1 = buffer on)
P3, P2, P1 and P0
bits output to pins 1, 2, 9 and 19 (1 = high impedance)
VDON
voltage doubler enable (1 = doubler enabled)
OLA, OLB
out-of-lock select; selects signal output to pin 19 (see Table 4)
CRA, CRB
charge pump A/B current to ISET ratio select (see Table 5)
SR
reference frequency ratio select (see Table 6)
Table 4
0
p18
p19
p20
p21
ADDRESS
Philips Semiconductors
Bit allocation
Low-power dual frequency synthesizer
for radio communications
1997 Sep 03
Table 2
Out-of-lock select
OUTPUT AT PIN 19
0
0
P0
0
1
lock status of loop B; OOLB
1
0
lock status of loop A; OOLA
1
1
logic OR function of loops A and B
Product specification
OLB
UMA1015AM
OLA
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
Table 5
The synthesizers are powered up when both hardware
and software Power-down signals are at logic 1. When
only one synthesizer is powered down, the functions
common to both will be maintained (independent of the
state of sPBF). When both synthesizers are powered
down, the fxtal buffer can be maintained in an active state
by setting sPBF to logic 1. This will allow any system clock
derived from the fXTALO buffered output to remain on in
power-down. Note that sPBF is independent of the state of
HPD. When both synthesizers are switched off, the
voltage doubler (if enabled) will remain active drawing a
reduced current. An internal oscillator will drive the doubler
in this situation. If both synthesizers have been in a
power-down condition, then when one or both
synthesizers are reactivated, the reference and main
dividers restart in such a way as to avoid large random
phase errors at the phase comparator.
Charge pump current ratio
CRA/CRB
CURRENT AT PUMP
0
ICP = 12 × ISET
1
ICP = 24 × ISET
Table 6
Reference division ratio
SR
SYNTHESIZER A
SYNTHESIZER B
0
R
R
1
R
2R
UMA1015AM
Power-down modes
The device can be powered down either via pin HPD
(active LOW = power-down) or via the serial bus
(bits sPDA and sPDB, logic 0 = power-down).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD1, VDD2 DC range of digital power supply voltage with respect to DGND
−0.3
+6.0
V
VCC
DC charge pump supply voltage with respect to AGND
−0.3
+6.0
V
∆VCC-DD
difference in voltage between VCC and VDD1, VDD2
−0.3
+6.0
V
Vn
DC voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with respect to DGND −0.3
V3, 17
DC voltage at pins 3 and 17 with respect to AGND
∆VGND
Tstg
Tamb
VDD1 + 0.3
V
VCC + 0.3
V
difference in voltage between AGND and DGND (these pins should be −0.3
connected together)
+0.3
V
storage temperature
−55
+125
°C
operating ambient temperature
−30
+85
°C
−0.3
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
1997 Sep 03
7
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
CHARACTERISTICS
VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 6.0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies; (VDD1, VDD2 and VCC) voltage doubler disabled, external supply on VCC
VDD1, VDD2 digital supply voltage
VDD1 = VDD2
2.7
−
5.5
V
IDD1 + IDD2
fXTAL = 12.8 MHz;
both synthesizers on;
VDD1 = VDD2 = 3 V
−
8.7
−
mA
fXTAL = 12.8 MHz;
both synthesizers on;
VDD1 = VDD2 = 5.5 V
−
−
12.5
mA
total digital supply current
from VDD1 and VDD2 with
one synthesizer in
power-down mode
fXTAL = 12.8 MHz; one
synthesizer powered down;
VDD1 = VDD2 = 3 V
−
5.0
−
mA
fXTAL = 12.8 MHz; one
synthesizer powered down;
VDD1 = VDD2 = 5.5 V
−
−
7.5
mA
digital supply current from
VDD1 with both
synthesizers powered
down and crystal buffer on
fXTAL = 12.8 MHz; VHPD = 0 V;
sPBF = 1; VDD1 = VDD2 = 3 V
−
0.5
−
mA
fXTAL = 12.8 MHz; VHPD = 0 V;
sPBF = 1; VDD1 = VDD2 = 5.5 V
−
−
1.15
mA
IDDpd
digital supply current in
power-down mode
both synthesizers powered
down; VHPD = 0 V; sPBF = 0
−
−
60
µA
VCC
charge pump supply
voltage
VCC ≥ VDD
2.7
−
6.0
V
ICC
charge pump supply
current
both synthesizers on and in
lock; fref = 12.5 kHz
−
−
25
µA
ICCpd
charge pump supply
current in power-down
mode
both synthesizers powered
down
−
−
25
µA
IDDpda,
IDDpdb
IDD(xtal)
total digital supply current
from VDD1 and VDD2
Voltage doubler enabled
IDD
total digital supply current
from VDD1 and VDD2
fXTAL = 12.8 MHz; both
synthesizers on and in lock;
VDD1 = 3 V; fRF = 900 MHz
−
9.2
12
mA
IDDpd
total digital supply current
in power-down mode from
VDD1 and VDD2
both synthesizers powered
down; VDD1 = 3 V; VHPD = 0 V;
sPBF = 0
−
0.25
0.4
mA
VCCvd
charge pump supply
voltage
DC current drawn from
VCC = 50 µA; fRF > 100 MHz
4.2
2VDD1 − 0.6 6.0
1997 Sep 03
8
V
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
SYMBOL
PARAMETER
UMA1015AM
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RF main divider input; RFA and RFB
fRF
RF input frequency
VRF(rms)
RF input signal voltage
(RMS value; AC coupled)
Rs = 50 Ω;
fRF = 400 to 1100 MHz
50
−
1100
MHz
50
−
250
mV
−
400
mV
Rs = 50 Ω; fRF = 80 to 400 MHz 150
Rs = 50 Ω; fRF = 50 to 80 MHz
225
−
400
mV
ZI
input impedance
(real part)
fRF = 1 GHz; indicative, not
tested
−
300
−
Ω
CI
input capacitance
indicative, not tested
−
1
−
pF
Rpm
principle main divider ratio
512
−
131071
3
−
35
MHz
100
−
500
mV
Reference divider input; fXTALIN
fXTALIN
reference input frequency
from crystal
VXTALIN(rms) sinusoidal input voltage
(RMS value)
ZI
input impedance
(real part)
fXTALIN = 12.8 MHz; indicative,
not tested
−
10
−
kΩ
CI
input capacitance
indicative, not tested
−
1
−
pF
Rrd
reference divider ratio
8
−
4095
RSET = 12 to 60 kΩ
−
1.1
−
V
RSET = 15 kΩ;
CRA/CRB = logic 1;
Icp = ISET × 24;
Vcp = 0.4 V to VCC − 0.5 V
1.3
1.75
2.3
mA
RSET = 15 kΩ;
CRA/CRB = logic 0;
Icp = ISET × 12;
Vcp = 0.4 V to VCC − 0.5 V
0.7
0.9
1.2
mA
Vcp = 0.4 V to VCC − 0.5 V
−5
±1
+5
nA
Charge pump current setting resistor input; ISET
VSET
voltage output on ISET
Charge pump outputs; CPA and CPB
Icp
ILI
charge pump sink or
source current
charge pump off leakage
current
Logic input signal levels; DATA, CLK, E and HPD
VIH
HIGH level input voltage
at logic 1
0.7VDD1 −
VDD1 + 0.3
V
VIL
LOW level input voltage
at logic 0
−0.3
−
0.3VDD1
V
Ibias
input bias currents
at logic 1 or logic 0
−5
−
+5
µA
CI
input capacitance
indicative, not tested
−
1
−
pF
−
0.4
V
Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and fXTALO - open drain outputs
VOL
1997 Sep 03
LOW level output voltage
−
Isink < 0.4 mA
9
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
SERIAL TIMING CHARACTERISTICS
VDD1 = 3 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
tr, tf
input rise and fall times
−
10
40
ns
Tcy
clock period
100
−
−
ns
Enable programming; E
tSTART
delay to rising clock edge
40
−
−
ns
tEND
delay from last falling clock edge
−20
−
−
ns
tW
minimum inactive pulse width
4000
−
−
ns
tSU;E
enable set-up time to next clock edge
20
−
−
ns
Register serial input data; DATA
tSU;DAT
input data to clock set-up time
20
−
−
ns
tHD;DAT
input data to clock hold time
20
−
−
ns
tEND
handbook, full pagewidth
tSU;DAT
tHD;DAT
tf
Tcy
tr
tSU;E
CLK
DATA
LSB
MSB
ADDRESS
E
tSTART
MGG524
Fig.3 Serial bus timing diagram.
1997 Sep 03
10
tW
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
TYPICAL PERFORMANCE CHARACTERISTICS
MGK784
12
handbook, full pagewidth
IDD
(mA)
10
(1)
(2)
8
(3)
6
4
2
2.5
3
(1) Tamb = +90 °C.
3.5
(2) Tamb = +25 °C.
4
4.5
5
VDD (V)
5.5
(3) Tamb = −35 °C.
Fig.4 Typical IDD as a function of VDD with both synthesizers on and voltage doubler disabled.
MGK783
2.0
handbook, full pagewidth
(2)
ICPA
(mA)
1.6
(1)
1.2
0.8
0.4
0
−0.4
−0.8
−1.2
−1.6
−2.0
(1)
(2)
0
RSET = 15 kΩ;
CRA = 1.
1
(1) VCC = 2.7 V.
2
3
4
5
VCPA (V)
(2) VCC = 6.0 V.
Fig.5 Typical charge pump current as a function of CPA voltage with Tamb = 25 °C.
1997 Sep 03
11
6
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
MGK782
handbook, full pagewidth
4
ICPA
(nA)
2
(1)
0
(2)
(3)
−2
−4
0
1
VCC = VDD = 6 V;
RSET = 15 kΩ;
CRA = 1.
2
(1) Tamb = +25 °C.
3
4
(2) Tamb = −35 °C.
5
VCPA (V)
6
(3) Tamb = +90 °C.
Fig.6 Typical charge pump 3-state current as a function of CPA voltage.
MGK779
10
handbook, full pagewidth
VXTALIN
(dBm)
+7
guaranteed area
0
−7
−10
−20
−30
(1)
(2)
−40
−50
0
5
10
20
15
25
30
35
fXTALIN (MHz)
fXTALIN externally terminated by 50 Ω load; AC-coupled.
(1) VDD = 5.5 V.
(2) VDD = 2.7 V.
Fig.7 Typical crystal input sensitivity as a function of input frequency with Tamb = 25 °C.
1997 Sep 03
12
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
MGK780
10
handbook, full pagewidth
VXTALIN
(dBm)
+7
0
guaranteed area
−7
−10
−20
(1)
−30
(2)
(3)
−40
0
5
10
20
15
25
30
35
fXTALIN (MHz)
fXTALIN externally terminated by 50 Ω load; AC-coupled.
(1) Tamb = −35 °C.
(2) Tamb = +25 °C.
(3) Tamb = +90 °C.
Fig.8 Typical crystal input sensitivity as a function of input frequency with VDD = 5.5 V.
MGK781
10
handbook, full pagewidth
VRF
(dBm)
+5
+1
0
−3.5
guaranteed area
−10
−13
−20
(1)
(2)
−30
0
100
200
300
400
RF input externally terminated by 50 Ω load; AC-coupled.
500
600
(1) VDD = 5.5 V.
700
800
900
1000
1100
fRF (MHz)
(2) VDD = 2.7 V.
Fig.9 Typical RF input sensitivity as a function of input frequency with Tamb = 25 °C.
1997 Sep 03
13
1200
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
MGK778
10
handbook, full pagewidth
VRF
(dBm)
+5
+1
0
−3.5
guaranteed area
−10
−13
(1)
−20
(2)
(3)
−30
0
100
200
300
400
RF input externally terminated by 50 Ω load; AC-coupled.
500
700
600
(1) Tamb = −35 °C.
800
900
(2) Tamb = +25 °C.
1000
1100
fRF (MHz)
1200
(3) Tamb = +90 °C.
Fig.10 Typical RF input sensitivity as a function of input frequency with VDD = 5.5 V.
MGK777
6
handbook, full pagewidth
(1)
VCC
(2)
(V)
5.5
(3)
5
4.5
4
2.5
(1) Tamb = −35 °C.
3
(2) Tamb = +25 °C.
3.5
4
4.5
5
VDD (V)
5.5
(3) Tamb = +90 °C.
Fig.11 Typical charge pump supply voltage as a function of VDD voltage with voltage doubler enabled.
1997 Sep 03
14
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
1
handbook, full pagewidth
0.5
2
(1)
(2)
0.2
5
(3)
10
+j
0.2
0
0.5
1
2
5
∞
10
−j
10
5
0.2
2
0.5
(1) Real part: 500 Ω; imaginary part: 1.4 pF; at 1.2 GHz.
(2) Real part: 800 Ω; imaginary part: 1.1 pF; at 1.0 GHz.
MGK785
1
(3) Real part: 830 Ω; imaginary part: 0.9 pF; at 800 MHz.
Fig.12 Typical RF input admittance (IC powered on).
1
handbook, full pagewidth
0.5
2
0.2
5
10
+j
(2)
0
0.2
0.5
1
2
5
∞
10
(1)
−j
10
5
0.2
2
0.5
1
(1) Real part: 7.8 kΩ; imaginary part: 0.9 pF; at 3 MHz.
MGK786
(2) Real part: 9.8 kΩ; imaginary part: 1.0 pF; at 35 MHz.
Fig.13 Typical crystal input admittance (IC powered on).
1997 Sep 03
15
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
APPLICATION INFORMATION
modulated audio
handbook, full pagewidth
VOLTAGE
CONTROLLED
OSCILLATOR
SPLITTER
POWER
AMPLIFIER
TRANSMIT PLL
MAIN
DIVIDER A
959 MHz
DUPLEX
FILTER
LOW-PASS
FILTER
PHASE
COMPARATOR
A
REFERENCE
DIVIDER
TCXO
914 MHz
MAIN
DIVIDER B
UMA1015AM
PHASE
COMPARATOR
B
RECEIVE PLL
VOLTAGE
CONTROLLED
OSCILLATOR
SPLITTER
LOW NOISE
AMPLIFIER
856 MHz
1st IF AND REMAINDER OF
RECEIVER CHAIN
1st MIXER
to demodulation
MGG533
Fig.14 Typical application block diagram.
1997 Sep 03
LOW-PASS
FILTER
16
1997 Sep 03
17
33 Ω
18 Ω
1 nF
18 Ω
Vctr
100 nF
GND
VTCXO
fOSC
to power
amplifier
18 Ω
10 kΩ
positive
supply
100 nF
audio
modulation
959 MHz
1 nF
56 kΩ
3.3
nF
27
kΩ
1 nF
DGND
RFA
HPD
VDD1
CPA
27
kΩ
10
9
UMA1015AM
11
12
13
14
15
16
17
18
19
20
1 kΩ
CLK
1 kΩ
DATA 1 kΩ
E
VDD2
RFB
AGND
CPB
VCC
P0/OOL
ISET
15
kΩ
Fig.15 Typical CT1 application.
fXTALO
P3
8
7
6
5
4
3
2
1
positive
supply
P2
P1
27
kΩ
fXTALIN
27
kΩ
1 nF
56 Ω
18
Ω
ewidth
RF output
VCOTx
control
39
1 kΩ
nF
56
nF
100
nF
10
kΩ
3-line
bus
1 nF
100
nF
LED
100
nF
18 Ω
18 Ω
18 Ω
15 Ω
100
nF
MGG534
RF output
VCORx
control
1 nF
856 MHz
1 nF
56 kΩ
56
nF
39
kΩ
1 nF
to 1st
mixer
3.3
nF
positive supply
positive
supply
18 Ω
120 Ω
56 Ω
3.9 kΩ
Low-power dual frequency synthesizer
for radio communications
Transmit frequency = 959 MHz.
Receive frequency = 914 MHz.
1st IF = 58.1125 MHz.
2nd IF = 455 MHz.
VCO sensitivity = 2 MHz/V.
Channel spacing = 12.5 kHz.
Charge pump gain (CPA = CPB) = 1 mA/cycle.
100
nF
15 Ω
positive supply
Philips Semiconductors
Product specification
UMA1015AM
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
D
SOT266-1
E
A
X
c
y
HE
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0
1.4
1.2
0.25
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
90-04-05
95-02-25
SOT266-1
1997 Sep 03
EUROPEAN
PROJECTION
18
o
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Sep 03
UMA1015AM
19
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Sep 03
20
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for
radio communications
NOTES
1997 Sep 03
21
UMA1015AM
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for
radio communications
NOTES
1997 Sep 03
22
UMA1015AM
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for
radio communications
NOTES
1997 Sep 03
23
UMA1015AM
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/1200/03/pp24
Date of release: 1997 Sep 03
Document order number:
9397 750 02704