INTEGRATED CIRCUITS DATA SHEET UMA1021AM Low-voltage frequency synthesizer for radio telephones Product specification Supersedes data of 1998 Mar 03 File under Integrated Circuits, IC17 1998 Nov 19 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. FEATURES • Low phase noise The synthesizer operates at RF input frequencies up to 2.2 GHz with a fully programmable reference divider. All divider ratios are supplied via a 3-wire serial programming bus. • Low current from 3 V supply • Fully programmable main divider • 3-line serial interface bus • Independent fully programmable reference divider, driven from external crystal oscillator Separate power and ground pins are provided to the analog (charge pump) and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. VDD1 and VDD2 must also be at the same potential (VDD). VCC must be equal to or greater than VDD for wider control range of the Voltage Controlled Oscillator (VCO), e.g. VDD = 3 V and VCC = 5 V. • Hard and soft power-down control. APPLICATIONS • 900 MHz and 2 GHz mobile telephones • Portable battery-powered radio equipment. The charge pump current (phase detector gain) is fixed by an external resistor at pin ISET and controlled via the serial interface. Only a passive loop filter is necessary; the charge pump functions within a wide voltage compliance range to improve the overall system performance. GENERAL DESCRIPTION The UMA1021AM BICMOS device integrates a prescaler, programmable dividers, and a phase comparator to implement a phase-locked loop. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 2.7 − 5.5 V analog supply voltage for charge pump VCC ≥ VDD 2.7 − 5.5 V total supply current (IDD + ICC) VCC = VDD = 5.5 V − 10 − mA Itot(pd) total supply current in Power-down mode (IDD + ICC) logic levels 0 V or VDD − 5 − µA fRF RF input frequency 300 − 2200 MHz fxtal crystal reference oscillator input frequency 3 − 35 MHz fph(comp) phase comparator frequency − 200 − kHz Tamb operating ambient temperature −30 − +85 °C VDD1, VDD2 digital supply voltage VCC Itot VDD1 = VDD2 = VDD ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UMA1021AM 1998 Nov 19 SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm 2 VERSION SOT369-1 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM BLOCK DIAGRAM handbook, full pagewidth LOCK 1 2 CP VDD2 UMA1021AM 16 BAND GAP CHARGE PUMP 3 15 PHASE COMPARATOR VSS3 14 4 5 RFI VSS2 MAIN DIVIDER WITH PRESCALER 13 REFERENCE DIVIDER 12 6 to charge pump 11 PON 7 SERIAL INTERFACE 10 9 VSS1 ISET VCC GND(CP) XTAL VDD1 E DATA CLK 8 MGL406 Fig.1 Block diagram. PINNING SYMBOL LOCK PIN 1 DESCRIPTION out-of-lock detector output CP 2 charge pump output VDD2 3 digital supply voltage VSS3 4 ground 3 (0 V) RFI 5 2 GHz main divider input VSS2 6 ground 2 (0 V) PON 7 power-on input VDD2 3 VSS1 8 ground 1 (0 V) VSS3 4 CLK 9 programming bus clock input DATA 10 programming bus data input E 11 programming bus enable input (active LOW) VDD1 12 digital supply voltage XTAL 13 crystal frequency input GND(CP) 14 ground for charge pump VCC 15 analog supply voltage for charge pump ISET 16 charge pump current setting with external resistor from this pin to ground 1998 Nov 19 handbook, halfpage LOCK 1 16 ISET CP 2 15 VCC 14 GND(CP) 13 XTAL UMA1021AM 12 VDD1 RFI 5 11 E VSS2 6 PON 7 10 DATA VSS1 8 9 CLK MGL405 Fig.2 Pin configuration. 3 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM The 3 lines are DATA (data bits), CLK (clock pulses) and E (enable signal). The data sent to the device is loaded in bursts framed by E. Programming clock edges and their appropriate data bits are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns HIGH. During normal operation, E should be kept HIGH. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the programming bus is inactive. It can always capture new programmed data even during power-down. FUNCTIONAL DESCRIPTION Main divider The main divider is clocked at pin RFI by the RF signal which is AC-coupled from an external VCO. The divider operates with signal levels from 50 to 225 mV (RMS) and at frequencies from 300 MHz to 2.2 GHz. It consists of a fully programmable bipolar prescaler followed by a CMOS counter. The main divider allows programmable ratios from 512 to 131071 inclusive. Reference divider The reference divider is clocked by the signal at pin XTAL. The applied input signal should be AC-coupled. The circuit operates with levels from 50 up to 500 mV (RMS) and at frequencies from 3 to 35 MHz. Any divide ratios from 8 to 2047 inclusive can be programmed. When the synthesizer is switched on, the presence of a signal at the reference divider input is required for correct programming. Data format Phase comparator and charge pump The data format is shown in Table 1. The first bit entered is dt16, the last bit is ad0. The phase detector is driven by the edges of the output signals of the main and reference dividers. The detector produces current pulses at pin CP. The pulse duration is equal to the difference in time of arrival of the edges from the two dividers. If the main divider edge arrives first, pin CP sinks current. If the reference divider edge arrives first, pin CP sources current. The leading bits (dt16 to dt0) make up the data field. The current at pin CP can be controlled via the serial programming bus as a multiple of the reference current set by an external pull-down resistor connected between pin ISET and ground (see Table 2). Pin CP remains active except in the Power-down mode. The four trailing bits (ad3 to ad0) are the address field. The UMA1021AM uses 4 of the 16 available addresses. These are chosen for compatibility with other Philips Semiconductors radio telephone ICs. The trailing address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To avoid erroneous divider ratios, the load pulse is not allowed during data reads by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. Additional circuitry is included to ensure that the gain of the phase detector remains linear even for small phase errors. For the divider ratios, the first bits entered (PM16 and PR10) are the Most Significant Bits (MSBs). Out-of-lock detector The test register (address 0000) does not normally need to be programmed. However, if it is programmed all bits in the data field should be set to logic 0. The out-of-lock detector is enabled or disabled via the serial interface by setting bit OOL (dt12) HIGH or LOW (see Table 1). An open-drain transistor drives the output pin LOCK. It is recommended to keep the sink current in the LOW state below 400 µA by applying a pull-up resistor from pin LOCK to the positive supply. When the out-of-lock detector is enabled pin LOCK is HIGH if the error at the phase detector input is less than approximately 25 ns, otherwise pin LOCK is LOW. If the out-of-lock detector is disabled, pin LOCK remains HIGH. Power-down mode The synthesizer is switched on when both the power-on input (PON) and the programmed bit dt6 (sPON) are HIGH. When switched on, the dividers and phase detector are synchronized to avoid random phase errors. When switched off, the phase detector is synchronized to avoid interrupting of the charge pump pulses. The UMA1021AM has a very low current consumption in the Power-down mode. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. 1998 Nov 19 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... FIRST IN REGISTER BIT ALLOCATION LAST IN DATA FIELD dt16 dt15 dt14 dt13 dt12 dt11 dt10 dt9 ADDRESS dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 ad3 ad2 ad1 ad0 0 0 0 0 X 0 0 0 1 PM0 0 1 0 0 PR0 0 1 0 1 test bits; note 2 X X X X OOL(3) X X X X X CR1(4) X PR10(7) PM16(6) CR0 X X sPON(5) X X X main divider coefficient X reference divider coefficient X X Notes 1. X = don’t care. 2. The test register (address 0000) should not be programmed with any other values except all zeros for normal operation. 3. Bit OOL sets the Out-Of-Lock detector (1 = enabled). 4. Bits CR1 and CR0 set the charge pump current ratio (see Table 2). 5. Bit sPON sets the software power-up for the synthesizer (see Table 3). 6. PM16 is the MSB of the main divider coefficient. 5 7. PR10 is the MSB of the reference divider coefficient. Table 2 Charge pump current ratio; note 1 Table 3 BIT CR1 BIT CR0 CHARGE PUMP CURRENT 0 0 0 1 1 1 Power-on programming PIN PON(1) BIT sPON(2) SYNTHESIZER STATE 10 × Iset L X off 18 × Iset X 0 off 0 13 × Iset H 1 on 1 17 × Iset Note Notes 1. Signal level a) L = LOW. c) H = HIGH. 2. X = don’t care. Product specification b) X = don’t care. UMA1021AM V set 1. Reference current for charge pump: I set = ---------R set Philips Semiconductors Bit allocation; note 1 Low-voltage frequency synthesizer for radio telephones 1998 Nov 19 Table 1 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD1, VDD2 digital supply voltage −0.3 +5.5 V VCC analog supply voltage for charge pump −0.3 +5.5 V ∆VCC-DD supply voltage difference −0.3 +5.5 V −0.3 VDD + 0.3 V −0.3 VCC + 0.3 V −0.3 +0.3 V between the analog and digital supply voltages Vn voltage at pins 5, 7, 9, 10 and 11 at pins 1, 2, 13 and 16 ∆VGND difference in voltage between any of pins GND(CP), VSS1, VSS2 and VSS3 Ptot total power dissipation − 85 mW these pins should be connected together Tstg storage temperature −55 +125 °C Tamb operating ambient temperature −30 +85 °C Tj(max) maximum junction temperature − 150 °C HANDLING All pins withstand the ESD class 2 test in accordance with “EIA/JESD22-A114-A”. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1998 Nov 19 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 6 VALUE UNIT 142 K/W Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM CHARACTERISTICS All values refer to the typical test and application diagram of Fig.5; VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 5.5 V; Tamb = 25 °C; unless otherwise specified. Characteristics for which only a typical value is given are not tested. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies; pins 3, 12 and 15 VDD1, VDD2 digital supply voltage VDD1 = VDD2 = VDD 2.7 − 5.5 V VCC analog supply voltage for charge pump VCC ≥ VDD 2.7 − 5.5 V IDD total digital supply current of synthesizer (IDD1 + IDD2) VDD = 5.5 V − 7 9.5 mA ICC analog supply current of charge pump VCC = 5.5 V; Rset = 5.6 kΩ − 3 3.8 mA Itot(pd) total supply current in Power-down mode (IDD + ICC) logic levels 0 V or VDD − 5 50 µA 300 − 2200 MHz 50 − 225 mV 512 − 131071 fRF = 1 GHz − 750 − Ω fRF = 2 GHz − 130 − Ω fRF = 1 GHz − 0.5 − pF fRF = 2 GHz − 1.5 − pF RF main divider input; pin 5 fRF RF input frequency VRF(rms) input signal level (RMS value) D/Dm main divider ratio Zi input impedance (real part) Ci input capacitance AC-coupled; series resistance Rs = 50 Ω Reference divider input; pin 13 fxtal crystal reference oscillator input frequency 3 − 35 MHz Vxtal(rms) sinusoidal input signal level (RMS value) 50 − 500 mV D/Dref reference divider ratio Zi input impedance (real part) fxtal = 13 MHz − 10 − kΩ Ci input capacitance fxtal = 13 MHz − 1.3 − pF 8 2047 Phase comparator fph(comp) phase comparator frequency − 200 − kHz floop(max) maximum loop comparison frequency − 2000 − kHz Charge pump current setting; pin 16 Rset external resistor connected between pin 16 and ground 5.6 − 12 kΩ Vset regulated voltage Rset = 5.6 kΩ − 1.2 − V 1998 Nov 19 7 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones SYMBOL PARAMETER UMA1021AM CONDITIONS MIN. TYP. MAX. UNIT Charge pump output; pin 2 Vo(compl) compliance output voltage Rset = 5.6 kΩ 0.4 − VCC − 0.4 V Io(err) output current error Rset = 5.6 kΩ −25 − +25 % Io(match) sink-to-source current matching Rset = 5.6 kΩ − ±5 − % IL leakage current Rset = 5.6 kΩ; charge pump off; Vo(compl) = 1⁄2VCC −5 ±1 +5 nA N900 RF synthesizer’s contribution to close-in phase noise of 900 MHz VCO signal inside the closed loop bandwidth fxtal = 13 MHz; Vxtal = 0 dBm; fph(comp) = 200 kHz − −88 − dBc/Hz N1800 RF synthesizer’s contribution to close-in phase noise of 1.8 GHz VCO signal inside the closed loop bandwidth fxtal = 13 MHz; Vxtal = 0 dBm; fph(comp) = 200 kHz − −82 − dBc/Hz Phase noise Interface logic inputs; pins 7, 9, 10 and 11 VIH HIGH-level input voltage 0.7VDD − VDD + 0.3 V VIL LOW-level input voltage −0.3 − 0.3VDD V Ii(bias) input bias current −5 − +5 µA Ci input capacitance − 2 − pF logic 1 or logic 0 Out-of-lock detector output; pin 1 VOL LOW-level output voltage open-drain output − − 0.3VDD V Eϕ(th) threshold phase error open-drain output − 25 − ns 1998 Nov 19 8 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM SERIAL BUS TIMING CHARACTERISTICS VDD1 = VDD2 = VCC = 3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Serial programming clock; CLK tr rise time − 10 40 ns tf fall time − 10 40 ns Tcy clock cycle time 100 − − ns Enable programming; E tSTART delay to rising clock edge 40 − − ns tEND delay from last falling clock edge −20 − − ns tW minimum inactive pulse width 4000 − − ns tSU;E enable set-up time to next clock edge 20 − − ns note 1 Register serial input data; DATA tSU;DAT input data to clock set-up time 20 − − ns tHD;DAT input data to clock hold time 20 − − ns Note 1. The minimum pulse width (tW) can be smaller than 4000 ns when the both conditions are fulfilled: 447 a) Main divider input frequency: f RF > ---------tW 3 b) Reference divider input frequency: f xtal > -----tW tSU;DAT handbook, full pagewidth tHD;DAT tf Tcy tEND tSU;E tr CLK DATA MSB LSB ADDRESS E tSTART MBG368 Fig.3 Serial bus timing diagram. 1998 Nov 19 9 tW Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM APPLICATION INFORMATION handbook, full pagewidth power amplifier transmit data PLL SPLITTER VCO LPF transmit mixer MAIN DIVIDER duplex filter REFERENCE DIVIDER TCXO PHASE COMPARATOR AND CHARGE PUMP UMA1021AM low noise amplifier MGL407 to demodulation 1st mixer 2nd mixer Fig.4 Typical application block diagram. 1998 Nov 19 10 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM positive supply positive supply handbook, full pagewidth LOCK 1 16 ISET 5.6 kΩ 12 Ω 100 nF (1) 4.7 µF CP (1) (1) (1) VDD2 control 100 nF VSS3 out 1 nF 18 Ω 15 12 Ω (1) RF VCO 2 56 pF 18 Ω 3 14 4 13 12 Ω 100 nF GND(CP) XTAL 100 nF 1 nF 12 5 VCC VTCXO GND Vcontrol fosc UMA1021AM RFI 12 Ω 12 Ω VCC VDD1 100 nF 18 Ω 56 Ω VSS2 6 11 E 56 pF positive supply PON to 1st mixer 10 DATA 7 1 kΩ VSS1 8 9 CLK 12 Ω 12 Ω 3-wire bus (1) Values depend on application. Fig.5 Typical test and application diagram. 1998 Nov 19 11 12 Ω MGL408 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 94-04-20 95-02-04 SOT369-1 1998 Nov 19 EUROPEAN PROJECTION 12 o Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1998 Nov 19 UMA1021AM 13 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021AM DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Nov 19 14 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones NOTES 1998 Nov 19 15 UMA1021AM Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 435102/750/02/pp16 Date of release: 1998 Nov 19 Document order number: 9397 750 04261