TRIQUINT TQ3632

WIRELESS COMMUNICATIONS DIVISION
TQ3632
C2
Control
Logic
DATA SHEET
L1
C2
VDD
GND
GND
RF
IN
Low Current, 3V PCS
Band CDMA LNA IC
RF 50 ohm
OUT RF Out
LNA
gnd
C3
Control
Logic
Features
Small size: SOT23-8
Single 3V operation
Low-current operation
Product Description
Gain Select
The TQ3632 is a low current, 3V, RF LNA IC designed specifically for PCS band
CDMA applications. It’s RF performance meets the requirements of products
designed to the IS-95 specifications. The TQ3632 is designed to be used with the
TQ5631 or TQ5633 (CDMA mixer) which provides a complete CDMA receiver for
1900MHz phones.
High IP3 performance
The LNA incorporates on-chip switches which determine high, low and bypass mode
select. When used with the TQ5631 or TQ5633 (CDMA RFA/mixer), four gain steps
are available for use which provide low current/high IP3 and gain. The RF output
port is internally matched to 50 Ω, greatly simplifying the design and minimizing the
number of external components. The TQ3632 achieves excellent RF performance
with low current consumption, supporting long standby and talk times in portable
applications. Coupled with the very small SOT23-8 package, the part is ideally suited
for PCS band mobile phones.
Few external components
Applications
IS-95 CDMA PCS Mobile Phones
Electrical Specifications1
Parameter
Min
Typ
Max
Units
Frequency
1960
MHz
Gain
12.5
dB
Noise Figure
1.5
dB
3rd
7.0
dBm
7.5
mA
Input
Order Intercept
DC supply Current
Note 1: Test Conditions: Vdd=2.8V, RF=1960MHz, Tc=25C, CDMA High Gain state.
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1
TQ3632
Data Sheet
Electrical Characteristics
Parameter
Conditions
Min.
Typ/Nom
Max.
Units
RF Frequency
PCS band
1810
1960
1990
MHz
10.5
12.5
CDMA Mode-High Gain
Gain
Noise Figure
1.5
dB
1.9
Input IP3
5.0
Input Return Loss (with external matching)
10
dB
Output Return Loss
10
dB
Supply Current
7.0
dB
7.5
dBm
9.5
mA
CDMA Mode-High Gain-Low Linearity
Gain
8.5
Noise Figure
11.0
dB
1.8
dB
4.0
dBm
Input IP3
2.0
Input Return Loss (with external matching)
10
dB
Output Return Loss
10
dB
Supply Current
4.5
6.5
mA
Bypass Mode
Gain
-3.0
Noise Figure
Input IP3
20.0
-1.0
dB
2.0
3.0
dB
25.0
dBm
Input Return Loss (with external matching)
10
dB
Output Return Loss
10
dB
Supply Current
1.0
Supply Voltage
2.7
Note 1: Test Conditions: Vdd=2.8V, RF=1960MHz, TC = 25° C, unless otherwise specified.
Note 2: Min/Max limits are at +25°C case temperature, unless otherwise specified.
Absolute Maximum Ratings
Parameter
Value
Units
DC Power Supply
5.0
V
Power Dissipation
500
mW
Operating Temperature
-40 to 85
C
Storage Temperature
-60 to 150
C
Signal level on inputs/outputs
+20
dBm
Voltage to any non supply pin
+0.3
V
2
-2.0
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2.8
2.5
3.3
mA
V
TQ3632
Data Sheet
Typical Performance
Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=25C, RF=1960MHz
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
1920
CDMA High Gain Mode
Idd v Vdd v Temp
-30C
+25C
+85C
Idd (mA)
Gain (dB)
CDMA High Gain Mode
Gain v Freq v Temp
1940
1960
1980
2000
9.00
8.50
8.00
7.50
7.00
6.50
6.00
5.50
5.00
4.50
4.00
-30C
+25C
+85C
2.5
2.7
Frequency (MHz)
9.0
Gain (dB)
IIP3 (dBm)
9.5
8.5
8.0
-30C
+25C
+85C
7.5
1960
1980
2000
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
1920
1940
1960
1980
2000
Frequency (MHz)
CDMA High Gain Mode
Noise Figure v Freq v Temp
High Gain/Low Linearity Mode
IIP3 v Freq v Temp
7.0
6.5
6.0
IIP3 (dBm)
Noise Figure (dB)
3.5
-30C
+25C
+85C
Frequency (MHz)
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1920
3.3
High Gain/Low Linearity Mode
Gain v Freq v Temp
10.0
1940
3.1
Vdd (V)
CDMA High Gain Mode
IIP3 v Freq v Temp
7.0
1920
2.9
-30C
+25C
+85C
1940
1960
Frequency (MHz)
1980
5.5
5.0
4.5
-30C
+25C
+85C
4.0
3.5
2000
3.0
1920
1940
1960
1980
2000
Frequency (MHz)
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3
TQ3632
Data Sheet
High Gain/Low Linearity Mode
Noise Figure v Freq v Temp
BYPASS Mode
IIP3 v Freq v Temp
38.0
37.0
2.00
IIP3 (dBm)
36.0
1.50
1.00
-30C
+25C
+85C
0.50
0.00
1920
1940
1960
1980
34.0
33.0
30.0
1920
2000
1940
High Gain/Low Linearity Mode
Idd v Vdd v Temp
BYPASS Mode
Noise Figure v Freq v Temp
5.50
2.50
4.50
4.00
-30C
+25C
+85C
3.50
2.7
2.9
3.1
3.3
1.50
1.00
-30C
+25C
+85C
0.00
1920
3.5
1940
Vdd (V)
1960
1980
2000
Frequency (MHz)
BYPASS Mode
Gain v Freq v Temp
BYPASS Mode
Idd v Vdd v Temp
1.60
0.0
1.40
-0.5
1.20
-1.0
Idd (mA)
Gain (dB)
2000
2.00
0.50
3.00
-1.5
-2.0
-30C
+25C
+85C
-2.5
1.00
0.80
0.60
-30C
+25C
+85C
0.40
0.20
0.00
1940
1960
1980
2000
2.5
2.7
Frequency (MHz)
4
1980
Frequency (MHz)
3.00
-3.0
1920
1960
Frequency (MHz)
6.00
2.5
-30C
+25C
+85C
31.0
5.00
Idd (mA)
35.0
32.0
Noise Figure (dB)
Noise Figure (dB)
2.50
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2.9
3.1
Vdd (V)
3.3
3.5
TQ3632
Data Sheet
Application/Test Circuit
Vdd
R1
Control
Logic
C2
Vdd
GND
GND
C7
(paddle)
LNA input
L1
RF in
RF
out
LNA output
LNA
GND
C3
Control Logic
C8
Lbrd
Bill of Material for TQ3632 LNA Application/Test Circuit
Component
Reference Designator
Part Number
Value
Size
Manufacturer
Receiver IC
U1
TQ3631
SOT23-8
TriQuint Semiconductor
Capacitor
C7
4.7pF
0402
Capacitor
C8
1.5pF
0402
Resistor
R1
3.3Ω
0402
Inductor
L1
4.7nH
0402
Inductor
Lbrd
See application note
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Panasonic
5
TQ3632
Data Sheet
TQ3632 Product Description
Operation
The TQ3632 LNA uses a cascode low noise amplifier along with
signal path switching. A bias control circuit sets the quiescent
current for each mode and ensures peak performance over
process and temperature, see Figure 1. In the application,
CMOS level signals are applied to pins 1 and 5 and are
decoded by an internal logic circuit, this sets the device to the
desired mode. See Table 1 for truth table.
In the high gain mode, switches S1, S2, and S5 are closed, with
switches S3 and S4 open. In the bypass mode, switches S1,
S2, and S5 are open, with switches S3 and S4 closed. Six
internal switches ensures there are no parasitic feedback paths
for the RF signal. In the AMPS mode, control logic switches the
LNA into a low current bias condition.
Only three external components are needed. The chip uses an
external cap and inductor for the input match to pin 3. The
output is internally matched to 50 ohms at pin 6. A Vdd bypass
cap is required close to pin 8.
External degeneration of the cascode is required between pin 4
and ground. However, a small amount of PC board trace can
be used as the inductor. Alternatively, if an extra component
can be tolerated, a small value chip inductor could be used.
See Figure 2.
VDD
1
Bias and Switch Control Logic
8
C7
2
LNA IN
GND
S6
L1
3
S2
RFIN
C8
S3
4
Lbrd
LNA OUT
6
S1
5
DC
GND
Figure 1 TQ3632 Simplified Schematic
6
Typical Gain
High Gain
0
0
13(dB)
1
0
0
1
11(dB)
1
1
-2(dB)
High Gain
Low linearity
Bypass
Table 1 LNA States and Control Bits
LNA Input Network Design
Input network design for most LNA’s is a straightforward
compromise between noise figure and gain. The TQ3632 is no
exception, even though it has 3 different modes. The device
was designed so that one only needs to optimize the input
match in the high gain mode. As long as the proper grounding
and source inductance are used, the other two modes will
perform well with the same match.
It is probably wise to synthesize the matching network
component values for some intermediate range of Gamma
values, and then by experimentation, find the one which
provides the best compromise between noise figure and gain.
The quality of the chip ground will have some effect on the
Noise Parameter Analysis
RF
OUT
S4
S5
C3
The values used on our evaluation board may be used as a
starting point.
7
GND
C2
match, which is why some experimentation will likely be needed.
The input match will affect the output match to some degree, so
S22 should be monitored.
R1
VDD
Control
Logic C2
MODE
Control
Logic C3
A noise parameter analysis is shown on the next page for the
high gain and high gain low linearity modes. A “nominal” device
was mounted directly on a standard evaluation board without a
matching network (thru connected). The input reference plane
was set at pin 3 and board loss was included in the calculations.
C7 was set to 4.7pF.
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TQ3632
Data Sheet
Gain Control via Pin 4 Inductance
Gamma Opt analysis for TQ3632 High Gain Mode
The source connection of the LNA cascode is brought out
separately through pin 4. That allows the designer to make
some range of gain adjustment. The total amount of inductance
present at the source of the cascode is equal to the bond wire
plus package plus external inductance. One should generally
use an external inductance such that gain in the high gain
CDMA mode = 13.0dB. Although it is possible to increase the
gain of the TQ3632 by using little or no degeneration, input
intercept will be degraded.
Figure 2 shows how a spiral PC board trace can be used as the
external inductance. It is suggested that such a circuit be used
for the initial design prototype. Then the optimum inductance
can be found by simply solder bridging across the inductor. The
final PC board design can then include the proper shorted
version of the inductor.
Freq.
(MHz)
1800
1960
2040
Γ Opt
Γ Angle
0.454
0.390
0.354
70.5
84.8
87.3
Fmin
(dB)
1.534
1.209
1.369
R noise
29.27
18.47
16.94
Gamma Opt analysis for TQ3632 High Gain Low Linearity
Mode
Figure 2 Showing Lbrd and Grounding on Evaluation Board
Selection of the Vdd Bypass Cap for Optimum
Performance
The Vdd bypass capacitor has the largest effect on the LNA
Freq.
(MHz)
1800
1960
2040
Γ Opt
Γ Angle
0.454
0.390
0.354
70.5
84.8
87.3
Fmin
(dB)
1.534
1.209
1.369
R noise
29.27
18.47
16.94
output match, and is required for proper operation. Because the
input match affects the output match to some degree as well,
the process of picking the bypass cap value involves some
iteration. First, an input match is selected which gives adequate
gain and noise figure. Then the bypass capacitor is varied to
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7
TQ3632
Data Sheet
give the best output match. The demo board achieves 11-12dB
of return loss which is adequate for connection directly to the
input of a SAW filter.
Grounding
An optimal ground for the device is important in order to achieve
datasheet specified performance. Symptoms of a poor ground
include reduced gain and the inability to achieve <2:1 VSWR at
the output when the input is matched. It is recommended to use
multiple vias to a mid ground plane layer. The vias at pins 2 and
7 to this layer should be as close to the lead pads as possible
Additionally, the ground return on the Vdd bypass cap should
provide minimal inductance back to chip pins 2 and 7.
TQ3632 S-Parameters
TQ3632 High Gain Mode S-Parameters S12
Following are S-Parameter graphs for the high gain and high
gain low linearity modes. Data was taken on a single “nominal”
device at 2.8v Vdd. The reference planes were set at the end of
the package pins.
TQ3632 High Gain Mode S-Parameters S21
TQ3632 High Gain Mode S-Paremeters S11
8
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TQ3632
Data Sheet
TQ3632 High Gain Mode S-Parameters S22
TQ3632 High Gain Low Linearity Mode S-Parameters S21
TQ3632 High Gain Low Linearity Mode S Parameters S11
TQ3632 High Gain Low Linearity Mode S-Parameters S12
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9
TQ3632
Data Sheet
TQ3632 High Gain Low Linearity Mode S-Parameters S22
10
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TQ3632
Data Sheet
Package Pinout
C2
Control
Logic
L1
C2
VDD
GND
GND
RF
IN
GND
RF 50 ohm
OUT RF Out
C3
Control
Logic
Pin Descriptions
Pin Name
Pin #
Description and Usage
C2
1
Control logic 2
GND
2
Ground, paddle
RF IN
3
RF input, off-chip matching required
DC GND
4
Source of input FET
C3
5
Control logic 3
RF OUT
6
RF output, no matching required
GND
7
Ground
Vdd
8
LNA Vdd, typical 2.8V, C2 capacitor required
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11
TQ3632
Data Sheet
Package Type: SOT23-8 Plastic Package
Note 1
PIN 1
E
E1
b
FUSED LEAD
Note 2
A
c
e
DESIGNATION
A
A1
b
c
D
e
E
E1
L
Theta
L
A1
DESCRIPTION
OVERALL HEIGHT
STANDOFF
LEAD WIDTH
LEAD THICKNESS
PACKAGE LENGTH
LEAD PITCH
LEAD TIP SPAN
PACKAGE WIDTH
FOOT LENGTH
FOOT ANGLE
DIE
METRIC
1.20 +/-.25 mm
.100 +/-.05 mm
.365 mm TYP
.127 mm TYP
2.90 +/-.10 mm
.65 mm TYP
2.80 +/-.20 mm
1.60 +/-.10 mm
.45 +/-.10 mm
1.5 +/-1.5 DEG
θ
ENGLISH
0.05 +/-.250 in
.004 +/-.002 in
.014 in
.005 in
.114 +/-.004 in
.026 in
.110 +/-.008 in
.063 +/-.004 in
.018 +/-.004 in
1.5 +/-1.5 DEG
NOTE
3
3
3
3
1,3
3
3
2,3
3
Notes
1. The package length dimension includes allowance for mold mismatch and flashing.
2. The package width dimension includes allowance for mold mismatch and flashing.
3. Primary dimensions are in metric millimeters. The English equivalents are calculated and subject to rounding error.
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Tel: (503) 615-9000
Email: [email protected]
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of
this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 2000 TriQuint Semiconductor, Inc. All rights reserved.
Revision A, April, 2000
12
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