LT1166 Power Output Stage Automatic Bias System U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ The LT®1166 is a bias generating system for controlling class AB output current in high powered amplifiers. When connected with external transistors, the circuit becomes a unity-gain voltage follower. The LT1166 is ideally suited for driving power MOSFET devices because it eliminates all quiescent current adjustments and critical transistor matching. Multiple output stages using the LT1166 can be paralleled to obtain higher output current. Set Class AB Bias Currents Eliminates Adjustments Eliminates Thermal Runaway of IQ Corrects for Device Mismatch Simplifies Heat Sinking Programmable Current Limit May Be Paralleled for Higher Current Small SO-8 or PDIP Package U APPLICATIONS ■ ■ ■ ■ Thermal runaway of the quiescent point is eliminated because the bias system senses the current in each power transistor by using a small external sense resistor. A high speed regulator loop controls the amount of drive applied to each power device. The LT1166 can be biased from a pair of resistors or current sources and because it operates on the drive voltage to the output transistors, it operates on any supply voltage. Biasing Power MOSFETs High Voltage Amplifiers Shaker Table Amplifiers Audio Power Amplifiers , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION R1 Unity Gain Buffer Amp Driving 1Ω Load 15V MPS2907 100Ω 47Ω 2N2907 + R2 100Ω 220µF IRF530 1 ITOP = 15mA VTOP SENSE+ 8 4.3k VIN 2 ILIM– SENSE– 6 4 IBOTTOM = 15mA 1µF 1k RSENSE– 0.33Ω 47Ω 0V OUTPUT 0V VOUT R3 100Ω 1Ω IRF9530 1166 • TA01 300pF 2N2222 MPS2222 RSENSE+ 0.33Ω 5 VBOTTOM R4 100Ω 1µF 3 VIN LT1166 VOUT INPUT 1k 7 ILIM+ –15V + 5.6k 300pF 220µF 1166 • F01 Figure 1. Unity Gain Buffer with Current Limit 1 LT1166 U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION Supply Current (Pin 1 or Pin 4) ............................ 75mA Differential Voltage (Pin 2 to Pin 3) ......................... ±6V Output Short-Circuit Duration (Note 1) ......... Continuous Specified Temperature Range (Note 2) ........ 0°C to 70°C Operating Temperature Range ................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Junction Temperature (Note 3) ............................ 150°C Lead Temperature (Soldering, 10 sec).................. 300°C TOP VIEW + 8 SENSE 7 ILIM + VOUT 3 6 ILIM – VBOTTOM 4 5 SENSE – VTOP 1 +1 VIN 2 N8 PACKAGE 8-LEAD PDIP ORDER PART NUMBER LT1166CN8 LT1166CS8 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 100°C/ W (N8) TJMAX = 150°C, θJA = 150°C/ W (S8) 1166 Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS Pin 1 = 2V, Pin 4 = – 2V, Operating current 15mA and RIN = 20k, unless otherwise specified. PARAMETER Output Offset Voltage Input Bias Current Input Resistance VAB (Top) VAB (Bottom) Voltage Compliance Current Compliance Transconductance gmCC2 gmEE2 gmCC10 gmEE10 PSRRCC PSRREE Current Limit Voltage CONDITIONS Operating Current 15mA to 50mA Operating Current 15mA to 50mA (Note 4) Operating Current 15mA to 50mA (Note 5) Measure Pin 8 to Pin 3, No Load Measure Pin 5 to Pin 3, No Load Operating Current = 50mA (Notes 6, 9) Operating Voltage = ±2V (Note 7) Pin 1 = 2V, Pin 4 = – 2V Pin 1 = 2V, Pin 4 = – 2V Pin 1 = 10V, Pin 4 = – 10V Pin 1 = 10V, Pin 4 = – 10V (Note 8) (Note 8) Operating Current 15mA to 50mA Pin 7 Voltage to Pin 3 Pin 6 Voltage to Pin 3 The ● denotes specifications which apply over the full operating temperature range. Note 1: External power devices may require heat sinking. Note 2: Commercial grade parts are designed to operate over the temperature range of – 40°C to 85°C but are neither tested nor guaranteed beyond 0°C to 70°C. Industrial grade parts specified and tested over – 40°C and 85°C are available on special request, consult factory. Note 3: TJ calculated from the ambient temperature TA and the power dissipation PD according to the following formulas: LT1166CN8: TJ = TA + (PD • 100°C/W) LT1166CS8: TJ = TA + (PD • 150°C/W) Note 4: ITOP = IBOTTOM 2 MIN ● ● TYP 50 2 15 20 – 20 MAX 250 10 UNITS mV µA MΩ mV mV V mA ● 2 14 – 14 ±2 ±4 ● ● ● ● 0.08 0.08 0.09 0.09 0.100 0.100 0.125 0.125 19 19 0.13 0.13 0.16 0.16 mho mho mho mho dB dB ● ● 1.0 – 1.0 1.3 – 1.3 1.5 – 1.5 V V ● ● 26 – 26 ±10 ±50 Note 5: The input resistance is typically 15MΩ when the loop is closed. When the loop is open (current limit) the input resistance drops to 200Ω referred to Pin 3. Note 6: Maximum TJ can be exceeded with 50mA operating current and simultaneous 10V and – 10V (20V total). Note 7: Apply ±200mV to Pin 2 and measure current change in Pin 1 and 4. Pin 3 is grounded. Note 8: PSRRCC = gmCC2 – gmCC10 gm CC2 PSRREE = gmEE2 – gmEE10 gm EE2 Note 9: For Linear Operation, Pin 1 must not be less than 2V or more than 10V from Pin 3. Similarly, Pin 4 must not be less than 2V or more than 10V from Pin 3. LT1166 U W TYPICAL PERFORMANCE CHARACTERISTICS Input Bias Current vs Current Source Mismatch 150 0 ITOP = IBOTTOM = 4mA –50 –100 600 ITOP = IBOTTOM = 50mA RIN = 20k 400 200 0 RIN = 2k –200 –400 –600 –150 2.5 5.0 7.5 –10 –7.5 –5.0 –2.5 0 CURRENT SOURCE MISMATCH (%) –800 –1.0 –0.75 –0.5 –0.25 0 0.25 0.5 0.75 1.0 ITOP AND IBOTTOM MISMATCH (mA) 10 LT1166 • TPC01 8 2.6 2.5 2.4 2.3 2.2 2.1 50 25 0 75 TEMPERATURE (°C) 100 6 0 15 RTOP = RBOTTOM = 1k –2 –4 RL =10Ω GAIN (dB) –2 –3 –4 VS = ±15V RIN = 4.3k ITOP = IBOTTOM = 12mA C1 = C2 = 500pF SEE FIGURE 8 –8 0.001 0.01 0.1 1 FREQUENCY (MHz) 0 –5 ITOP = IBOTTOM = 12mA –10 –8 –15 6 8 10 LT1166 • TPC07 VS = ±15V RIN = 4.3k ITOP = IBOTTOM = 12mA C1 = C2 = 500pF SEE FIGURE 8 –20 0.001 10 0.01 0.1 1 FREQUENCY (MHz) LT1166 • TPC05 VOLTAGE DROP ACROSS SENSE RESISTORS (mV) 0 –7 5 Current Limit Pin Voltage vs Temperature 24 22 SENSE + 20 18 16 –16 –20 –24 –50 –25 1.25 VIN = ±1.5V 1.20 PIN 7 TO PIN 3 1.15 –1.15 –18 –22 10 LT1166 • TPC06 Voltage Across Sense Resistors vs Temperature RL = ∞ –1 10 –6 Closed-Loop Voltage Gain vs Frequency 125 RL =10Ω 20 4 2 100 RL = ∞ 25 –10 –10 –8 –6 –4 –2 0 2 4 INPUT VOLTAGE (V) 125 2 50 25 75 0 TEMPERATURE (°C) 30 RIN = 4.3k C1 = C2 = 500pF RL = 10Ω SEE FIGURE 8 LT1166 • TPC04 1 35 Open-Loop Voltage Gain vs Frequency GAIN (dB) 2.7 2.0 –50 –25 40 LT1166 • TPC03 10 OUTPUT VOLTAGE SWING (V) INPUT BIAS CURRENT (µA) 2.8 45 Output Voltage vs Input Voltage RL = ∞ ITOP = IBOTTOM = 15mA RIN = 4.3k 2.9 50 30 –50 –25 ILIM PIN VOLTAGE REFERENCED TO VOUT (V) 3.0 55 RL = ∞ ITOP = IBOTTOM = 15mA RIN = 4.3k LT1166 • TPC02 Input Bias Current vs Temperature –6 OUTPUT OFFSET VOLTAGE (mV) ITOP = IBOTTOM = 50mA 50 OUTPUT OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (µA) 60 800 100 –5 Output Offset Voltage vs Temperature Output Offset Voltage vs Current Source Mismatch –1.20 SENSE – 50 25 0 75 TEMPERATURE (°C) 100 125 LT1166 • TPC08 –1.25 –50 –25 PIN 6 TO PIN 3 50 25 0 75 TEMPERATURE (°C) 100 125 LT1166 • TPC09 3 LT1166 U W TYPICAL PERFORMANCE CHARACTERISTICS RL = 10Ω PO = 1W SEE FIGURE 8 25°C 0.110 0.100 TOTAL HARMONIC DISTORTION (%) INPUT TRANSCONDUCTANCE (mhos) 1000 10 0.120 125°C – 55°C 0.090 0.080 gmCC VIN = ±200mV RL = 0 RIN = 0 –0.080 –0.090 125°C gmEE – 55°C –0.100 25°C –0.110 –0.120 Sense Pin Voltage Referenced to VOUT vs Load Current SENSE PIN VOLTAGE REFERENCED TO VOUT (mV) Total Harmonic Distortion vs Frequency Input Transconductance vs Supply Voltage 0 1 2 3 4 5 6 7 8 SUPPLY VOLTAGE (V) 9 10 1 0.1 0.01 0.01 0.1 1 10 FREQUENCY (kHz) LT1166 • TPC10 100 LT1166 • TPC11 VBOTTOM VTOP 100 10 RSENSE = 100Ω 1 10 8 6 4 2 SINKING 0 2 4 6 8 SOURCING LOAD CURRENT (mA) 10 LT1166 • TPC12 U U U PIN FUNCTIONS VTOP (Pin 1): Pin 1 establishes the top side drive voltage for the output transistors. Operating supply current enters Pin 1 and a portion biases internal circuitry; Pin 1 current should be greater than 4mA. Pin 1 voltage is internally clamped to 12V with respect to VOUT and the pin current should be limited to 75mA maximum. VIN (Pin 2): Pin 2 is the input to a unity gain buffer which drives VOUT (Pin 3). During a fault condition (short circuit) the input impedance drops to 200Ω and the input current must be limited to 5mA or VIN to VOUT limited to less than ±6V. VOUT (Pin 3): Pin 3 of the LT1166 is the output of a voltage control loop that maintains the output voltage at the input voltage. VBOTTOM (Pin 4): Pin 4 establishes the bottom side drive voltage for the output transistors. Operating supply current exits this pin; Pin 4 current should be greater than 4mA. Pin 4 voltage is internally clamped to – 12V with respect to VOUT and the pin current should be limited to 75mA maximum. 4 SENSE – (Pin 5): The Sense – pin voltage is established by the current control loop and it controls the output quiescent current in the bottom side power device. Limit the maximum differential voltage between Pin 5 and Pin 3 to ±6V during fault conditions. ILIM – (Pin 6): The negative side current limit, limits the voltage at VBOTTOM to VOUT during a negative fault condition. The maximum reverse voltage on Pin 6 with respect to VOUT is 6V. ILIM + (Pin 7): The positive side current limit, limits the voltage at VTOP to VOUT during a positive fault condition. The maximum reverse voltage on Pin 7 with respect to VOUT is – 6V. SENSE + (Pin 8): The Sense + pin voltage is established by the current control loop and it controls the output quiescent current in the top side power device. Limit the maximum differential voltage between Pin 8 and Pin 3 to ±6V during fault conditions. LT1166 U W U U APPLICATIONS INFORMATION Overvoltage Protection The supplies VTOP (Pin 1) and VBOTTOM (Pin 4) have clamp diodes that turn on when they exceed ±12V. These diodes act as ESD protection and serve to protect the LT1166 when used with large power MOS devices that produce high VGS voltage. Current into Pin 1 or Pin 4 should be limited to ±75mA maximum. Multiplier Operation Figure 2 shows the current multiplier circuit internal to the LT1166 and how it works in conjunction with power output transistors. The supply voltages VT (top) and VB (bottom) of the LT1166 are set by the required “on” voltage of the power devices. A reference current IREF sets a constant VBE7 and VBE8. This voltage is across emitter base of Q9 and Q10 which are 1/10 the emitter area of Q7 and Q8. The expression for this current multiplier is: VBE7 + VBE8 = VBE9 + VBE10 or in terms of current: (IC9)(IC10) = (IREF)2/100 = Constant The product of IC9 and IC10 is constant. These currents are mirrored and set the voltage on the (+) inputs of a pair of RT 1k VTOP 1 internal op amps. The feedback of the op amps force the same voltage on the (–) inputs and these voltages then appear on the sense resistors in series with the power devices. The product of the two currents in the power devices is constant, as one increases the other decreases. The excellent logging nature of Q9 and Q10 allows this relation to hold over many decades in current. The total current in Q7 and Q8 is actually the sum of IREF and a small error current from the shunt regulator. During high output current conditions the error current from the regulator decreases. Current conducted by the regulator also decreases allowing VT or VB to increase by an amount needed to drive the power devices. Driving the Input Stage Figure 3 shows the input transconductance stage of the LT1166 that provides a way to drive VT and VB. When a positive voltage VIN is applied to RIN, a small input current flows into R2 and the emitter of Q2. This effect causes VO to follow VIN within the gain error of the amplifier. The input current is then mirrored by Q3/Q4 and current supplied to Q4’s collector is sourced by power device M1. The signal current in Q4’s emitter is absorbed by external resistor RB and this causes VB to rise by the same amount V+ VTOP M1 – IREF 10 SHUNT REGULATOR Q1 VAB+ 1Ω 1Ω RIN + 1k Q8 × 10 R2 Q12 VO VIN VAB– – Q11 3 VO 1k + R1 2 3 Q10 ×1 M1 CEXT1 8 Q9 ×1 Q7 × 10 1 V+ Q5 ×1 Q6 × 32 IREF RT 1k Q4 × 32 5 1Ω Q2 1Ω Q3 ×1 4 VBOTTOM 4 M2 VBOTTOM RB 1k CEXT2 M2 RB 1k V– 1166 • F03 V– 1166 • F02 Figure 2. Constant Product Generator Figure 3. Input Stage Driving Gates 5 LT1166 U W U U APPLICATIONS INFORMATION as VIN. Similarly for VT, when positive voltage is applied to RIN, current that was flowing in R1 and Q1 is now supplied through RIN. This effect reduces the current in mirror Q5/ Q6. The reduced current has the effect of reducing the drop on RT, and VT rises to make VO track VIN. The open-loop voltage gain VO/(VIN – VPIN2) can be increased by replacing RT and RB with current sources. The effect of this is to increase the voltage gain VOUT/ VIN from approximately 0.8 to 1 (see Typical Performance Characteristics curves). The use of current sources instead of resistors greatly increases loop gain and this compensates for the nonlinearity of the output stage resulting in much lower distortion. Frequency Compensation and Stability The input transconductance is set by the input resistor RIN and the 32:1 current mirrors Q3/Q4 and Q5/Q6. The resistors R1 and R2 are small compared to the value of RIN. Current in RIN appears 32 times larger in Q4 or Q6, which drive external compensation capacitors CEXT1 and CEXT2. These two input signal paths appear in parallel to give an input transconductance of: gm = 16/RIN The gain bandwidth is: 16 2π(RIN)(CEXT) Depending on the speed of the output devices, typical values are RIN = 4.3k and CEXT1 = CEXT2 = 500pF giving a – 3dB bandwidth of 1.2MHz (see Typical Performance Characteristics curves). GBW = To prevent instability it is important to provide good supply bypassing as shown in Figure 1. Large supply bypass capacitors (220µF) and short power leads can eliminate instabilities at these high current levels. The 100Ω resistors (R2 and R3) in series with the gates of the output devices stop oscillations in the 100MHz region as do the 100Ω resistors R1 and R4 in Figure 1. Driving Capacitive Loads Ideally, amplifiers have enough phase margin that they don’t oscillate but just slow down with capacitive loads. Practically, amplifiers that drive significant power require some isolation from heavy capacitive loads to prevent oscillation. This isolation is normally an inductor in series with the output of the amplifier. A 1µH inductor in parallel with a 10Ω resistor is sufficient for many applications. Setting Output AB Bias Current Setting the output AB quiescent current requires no adjustments. The internal op amps force VAB = ±20mV between each Sense (Pins 5 and 8) to the Output (Pin 3). At quiescent levels the output current is set by: IAB = 20mV/RSENSE The LT1166 does not require a heat sink or mounting on the heat sink for thermal tracking. The temperature coefficient of VAB is approximately 0.3%/°C and is set by the junction temperature of the LT1166 and not the temperature of the power transistors. Output Offset Voltage and Input Bias Current The output offset voltage is a function of the value of RIN and the mismatch between external current sources ITOP and IBOTTOM (see the Typical Performance Characteristics curves). Any error in ITOP and IBOTTOM match is reduced by the 32:1 input current mirror, but is multiplied by the input resistor RIN. Current Limit The voltage to activate the current limit is ±1.3V. The simplest way to protect the output transistors is to connect the Current Limit pins 6 and 7 to the Sense pins 5 and 8. A current limit of 1.3A can be set by using 1Ω sense resistors. To keep the current limit circuit from oscillating in hard limit, it is necessary to add an RC (1k and 1µF) between the Sense pin and the ILIM as shown in Figure 1. The sense resistors can be tapped up or down to increase or decrease the current limit without changing AB bias current in the power transistors. Figure 4 demonstrates 6 LT1166 U U W U APPLICATIONS INFORMATION how tapping the sense resistors gives twice the limit current or one half the limit current. Foldback current limit can be added to the normal or “square” current limit by including two resistors (30k typical) from the power supplies to the ILIM pins as shown in Figure 5. With square current limit the maximum output current is independent of the voltage across the power devices. Foldback limit simply makes the output current dependent on output voltage. This scheme puts dissipation limits on the output devices. The larger the voltage across the power device, the lower the available output current. This is represented in Figure 6, Output Voltage vs Output Current for the circuit of Figure 5. V+ 200 160 120 VTOP OUTPUT CURRENT (mA) 1 8 SENSE + 0.5Ω 7 ILIM + (2)(ILIM) 0.5Ω RIN 2 VIN 3 VIN LT1166 VOUT VOUT ILIM – 40 (1/2)(ILIM) FOLDBACK ILIM+ 0 –40 FOLDBACK ILIM– –80 –160 SQUARE ILIM– –200 –10 –8 –6 –4 –2 0 2 4 6 OUTPUT VOLTAGE (V) 1Ω 5 SENSE – 80 –120 1Ω 6 SQUARE ILIM+ VBOTTOM 8 10 LT1166 • F06 Figure 6. Output Current vs Output Voltage 4 V– 1166 • F04 Figure 4. Tapping Current Limit Resistors Driving the Shunt Regulator 15V 20mA 30k 100Ω + IRFR024 1 330pF VTOP SENSE + ILIM + 5.1k 8 1k 7 1µF 2 VIN LT1166 VOUT ILIM – SENSE – VBOTTOM 4 3 6 10Ω mA 1µF 1k VOUT 10Ω 5 100Ω IRFR9024 330pF 20mA 30k –15V 1166 • F05 Figure 5. Unity Gain Buffer Amp with Foldback Current Limit It is possible to current drive the shunt regulator directly without driving the input transconductance stage. This has the advantage of higher speed and eliminates the need to compensate the gm stage. With Pin 2 floating, the LT1166 can be placed inside a feedback loop and driven through the biasing current sources. The input transconductance stage remains biased but has no effect on circuit operation. The RL in Figure 7 is used to modulate the op amp supply current with input signal. This op amp functions as a V-to-I with the supply leads acting as current source outputs. The load resistor and the positive input of the op amp are connected to the output of the LT1166 for feedback to set AV = 1V/V. The capacitor CF eliminates output VOS due to mismatch between ITOP and IBOTTOM, and it also forms a pole at DC and a zero at 1/RFCF. The zero frequency is selected to give a –1V/V gain in the op amp before the phase of the MOSFETs degenerate the stability of the loop. 7 LT1166 U U W U APPLICATIONS INFORMATION APPLICATION CIRCUITS Bipolar Buffer Similar to the unity gain buffer in Figure 1, the LT1166 can be used to bias bipolar transistors as shown in Figure 8. The minimum operating voltage for the LT1166 is ±2V, so it is necessary to bias the part with adequate voltage from the output stage. The simplest way to do this is to use Darlington drivers and series diodes. There are no thermal tracking circuits or adjustments necessary and the LT1166 does not need to be mounted on the heat sink with the power devices. RTOP and RBOTTOM can be used to replace ITOP and IBOTTOM; see Typical Characteristics curves. 15V + 47Ω 100Ω 220µF 2N2907 RTOP 2N2907 ITOP = 15mA 100Ω 2N2222 500pF V+ IT 1 VTOP 5.6k SENSE + 8 ILIM + 7 IN4001 M1 TIP29 1 RF RIN VIN CF SENSE + 8 150Ω 4.7k VIN ILIM – + 2 VIN LT1166 VOUT 150Ω ILIM 1Ω 2 + VIN LT1166 VOUT ILIM – 3 6 SENSE – 1Ω 10Ω TIP30 5 IN4001 VBOTTOM RL 1Ω 6 VOUT 100Ω 4 SENSE – VOUT 7 – 1Ω 3 2N2907 5 500pF VBOTTOM IBOT = 15mA 2N2222 4 M2 100Ω RBOTTOM 2N2222 IB V– 220µF + VTOP 47Ω 1166 • F08 1166 • F07 Figure 7. Current Source Drive 8 –15V Figure 8. Bipolar Buffer Amp LT1166 U U W U APPLICATIONS INFORMATION Adding Voltage Gain The circuit in Figure 9 adds voltage gain to the circuit in Figure 1. At low frequency the LT1166 is in the feedback loop of the LT1360 so the gain error and the VOS are reduced and the closed-loop gain is 10V/V. LT1004-2.5 15V + 110Ω 440µF MPS2907 5.1k 15mA 100Ω IRF530 300pF 1 VT SENSE + 0.1µF 3 VIN 1k ILIM + + 7 LT1360 2 – 39k 6 8 1k 7 1µF LT1166 2 VOUT VIN VOUT 4 CF 500pF 0.1µF 0.33Ω 3 ILIM – 6 SENSE – 5 1µF 0.33Ω 1Ω 1k VBOT 100Ω 4 IRF9530 15mA 5.1k MPS2222 300pF LT1004 2.5 110Ω –15V 909Ω 1166 • F09 100Ω 440µF + 500pF Figure 9. Power Op Amp AV = 10 INPUT 0V OUTPUT 0V 1166 • F10 Figure 10. Power Amp Driving 1Ω Load INPUT 0V 0V OUTPUT 1166 • F11 Figure 11. Power Amp at 6A Current Limit 9 LT1166 U U W U APPLICATIONS INFORMATION 1A Adjustable Voltage Reference common mode voltage to its output. The following applications utilize amplifiers operating in suspended-supply operation (Figure 13). See “Linear Technology Magazine” Volume IV Number 2 for a discussion of suspended supplies. The gain setting resistors used in suspendedsupply operation must be tight tolerance or the gain will be wrong. For example: with 1% resistors the gain can be as far off as 75%, but with 0.1% resistors that error is cut to less than 5%. Using the values shown in Figure 13, the formula for computing the gain is: The circuit in Figure 12 uses the LT1166 in a feedback loop with the LT1431 to make a voltage reference with an “attitude.” This 5V reference can drive ±1A and maintain 0.4% tolerance at the output. If other output voltages are desired, external resistors can be used instead of the LT1431’s internal 5k resistors. HIGH VOLTAGE APPLICATION CIRCUITS In order to use op amps in high voltage applications it is necessary to use techniques that confine the amplifier’s AV = R8(R9 + R10) = –11.22 (R8 • R9) – (R7 • R10) 12V 100Ω 100Ω 12V IRF530 1 VTOP 12V SENSE + 8 ILIM + 7 1k 2k 4 7 RTOP RMID 8 3 1 REF V+ COL 1µF 2 VIN LT1166 VOUT 1µF ILIM – 6 SENSE – VBOTTOM 5 2.5V 1Ω 220µF 100Ω 4 IRF9530 LT1431 GND FORCE GND/SENSE– 5 100Ω 6 Figure 12. ±1A, 5V Voltage Reference R8 1k IN R7 10k – OUT + R9 9.1k R10 1k 1166 • F13 Figure 13. Op Amp in Suspended-Supply Operation 10 5VOUT + 1k – 5k 1Ω 3 + 5k 1k 1166 • F12 LT1166 U U W U APPLICATIONS INFORMATION Parallel Operation Parallel operation is an effective way to get more output power by connecting multiple power drivers. All that is required is a small ballast resistor to ensure current sharing between the drivers and an isolation inductor to keep the drivers apart at high frequency. In Figure 14 one power slice can deliver ±6A at 100VPK, or 300W RMS into 16Ω. The addition of another slice boosts the power output to 600W RMS into 8Ω and the addition of two or more drivers theoretically raises the power output to 1200W RMS into 4Ω. Due to IR loss across the sense 15V resistors, the FET RON resistance at 10A, and some sagging of the power supply, the circuit of Figure 14 actually delivers 350W RMS into 8Ω. Performance photos and a THD vs frequency plot are included in Figure 15 through 18. Frequency compensation is provided by the 2k input resistor, 180µH inductor and the 1nF compensation capacitors. The common node in the auxiliary power supplies is connected to amplifier output to generate the floating ±15V supplies. POWER SLICE + R1 100Ω 10µF FB 2N3906 R15 390Ω 1nF R9* 9.1k VTOP SENSE + 8 + 7 LT1004-2.5 12.5V C4 0.1µF R14 1k ILIM 7 + 6 LT1360 2 – RIN 2k 180µH LT1166 2 VOUT VIN 4 VIN 6 SENSE – VBOTTOM 5 R8* 1k –12.5V 3 – ILIM R7* 10k IRF230 1 R10* 1k 3 100V R2 100Ω R5 1k C1 1µF R3 0.22Ω C2 R6 1µF 1k R4 0.22Ω R17 0.22Ω L1** 0.4µH R11 100Ω 4 IRF9240 R16 390Ω FB LT1004-2.5 1nF 2N3904 + R13 200Ω 10µF –100V R12 100Ω –15V C3 3300pF ~ 110V AC + DIODE BRIDGE ~ – + C7 1000µF 35V + C8 1000µF 35V 7815 + + 7915 POWER SLICE 15V C5 220µF 25V 1Ω C6 220µF 25V –15V 10A FAST-BLOW 1166 • F14 AUXILARY SUPPLIES L3*** 1.5µH VOUT * 0.1% RESISTORS ** 4 TURNS T37-52 (MICROMETALS) *** 6 TURNS T80-52 (MICROMETALS) Figure 14. 350W Shaker Table Amplifier 11 LT1166 U W U U APPLICATIONS INFORMATION 1166 • F15 Figure 15. 0.3% THD at 10kHz, PO = 350W, RL = 8Ω 1166 • F17 Figure 17. 2kHz Square-Wave, CL = 1µF TOTAL HARMONIC DISTORTION (%) 1.0 PO = 350W R L = 8Ω 0.1 0.01 10 1166 • F16 Figure 16. Clipping at 1kHz, RL = 8Ω 100 10k 1k FREQUENCY (Hz) 100k LT1166 • F18 Figure 18. THD vs Frequency 100W Audio Power Amplifier The details of a low distortion audio amplifier are shown in Figure 19. The LT1360, designated U1, was chosen for its good CMRR and is operated in suspended-supply mode at a closed-loop gain of – 26.5V/V. The ±15V supplies of U1 are effectively bootstrapped by the output at point D and are generated as shown in Figure 14. A 3VP-P signal at VIN will cause an 80VPP output at point A. Resistors 7 to 10 set the gain of – 26.5V/V of U1, while C1 compensates for the additional pole generated by the CMRR of U1. The rest of the circuit (point A to point D) is an ultralow distortion unity-gain buffer. The main component in the unity-gain buffer is U4 (LT1166). This controller performs two important functions, first it modifies the DC voltage between the gates of M1 and M2 by keeping the product of the voltage across R20 and R21 constant. Its secondary role is to perform current limit, protecting M1 and M2 during short circuit. 12 The function of U3 is to drive the gates of M1 and M2. This amplifier’s real output is not point C as it appears, but rather the Power Supply pins. Current through R6 is used to modulate the supply current and thus provide drive to VTOP and VBOTTOM. Because the output impedance of U3 (through its supply pins) is very high, it is not able to drive the capacitive inputs of M1 and M2 with the combination of speed and accuracy needed to have very low distortion at 20kHz. The purposes of U2 are to drive the gate capacitance of M1 and M2 through its low output impedance and to reduce the nonlinearty of the M1 and M2 transconductance. R24, C4 set a frequency above which U2 no longer looks after U3 and U4, but just looks after itself as its gain goes through unity. R1/R2 and C2/C3 are compensation components for the CMRR feedthough. Curves showing the performance of the amplifier are shown in Figures 20 through 22. R9* 9.6k R10* 1k 4 U1 LT1360 7 6 2 3 A * 0.1% RESISTORS ** SEE POWER SUPPLY OF FIGURE 13 C1 10pF 2 3 R7* 10k R8* 1k 7 – R2 100Ω 4 U2 LT1363 + R1 100Ω 6 C3 470pF C2 470pF C4 20pF B R24 2.4k R4 1k R5 3.3k 2 3 C5 3300pF R12 100Ω 2N3904 4 U3 LT1360 7 2N3906 6 Figure 19. 100W Audio Amplifier LT1009-2.5 R3 10k + + – VIN – LT1009-2.5 + 2 1 R17 500Ω ILIM + VTOP SENSE + – C7 0.01µF – + 15V ** R14 500Ω 4 VBOTTOM SENSE – ILIM – U4 V VIN OUT LT1166 C9 0.01µF C6 22µF R13 30Ω R6 160Ω C R16 30Ω 22µF 15V ** + 5 6 3 7 8 R19 1k R15 100Ω C11 R22 1µF 1k C10 1µF R18 100Ω –50V C14 0.1µF M2 IRF9530 R21 0.22Ω R20 0.22Ω M1 IRF530 D C12 0.1µF 1166 • F18 C15 22µF R23 10Ω L1 1µH VOUT 22µF + C13 U U W + C8 APPLICATIONS INFORMATION U R11 100Ω + 50V LT1166 13 LT1166 U W U U APPLICATIONS INFORMATION 1166 • F20 RL = 8Ω f = 8kHz RL = 8Ω f = 20kHz Figure 20. Square Wave Response Into 8Ω Figure 21. 100W 20kHz Sine Wave and Its Distortion TOTAL HARMONIC DISTORTION (%) 0.1 RL = 8Ω POWER OUT = 100W 0.01 0.001 10 100 1k 10k FREQUENCY (Hz) 100k LT1166 • F21 Figure 22. THD vs Frequency 14 1166 • F21 LT1166 W W SI PLIFIED SCHEMATIC 1 VTOP Q5 ×1 Q6 × 32 IREF – SHUNT REGULATOR Q1 R1 200Ω Q11 VIN 2 + IREF 10 8 SENSE+ VAB + 7 ILIM+ Q7 × 10 Q9 ×1 1k Q8 × 10 Q10 ×1 1k 3 VOUT R2 200Ω Q12 6 ILIM– Q2 + VAB – – 5 SENSE– Q3 ×1 Q4 × 32 4 VBOTTOM 1166 • SS U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 +0.635 8.255 –0.381 ) 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN 0.100 ± 0.010 (2.540 ± 0.254) 0.018 ± 0.003 (0.457 ± 0.076) 0.015 (0.380) MIN N8 0695 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT1166 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 5 6 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.050 (1.270) BSC 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE SO8 0695 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1010 Fast ±150mA Power Buffer Ideal for Boosting Op Amp Output Current LT1105 Off-Line Switching Regulator Generate High Power Supplies LT1206 250mA/60MHz Current Feedback Amplifier C-LoadTM Op Amp with Shutdown and 900V/µs Slew Rate LT1210 1A/40MHz Current Feedback Amplifier C-Load Op Amp with Shutdown and 700V/µs Slew Rate LT1270A 10A High Efficiency Switching Regulator Use as Battery Boost Converter LT1360 50MHz, 800V/µs Op Amp ±15V, Ideal for Driving Capacitive Loads LT1363 70MHz, 800V/µs Op Amp ±15V, Very High Speed, C-Load C-Load is a registered trademark of Linear Technology 16 Linear Technology Corporation LT/GP 1195 6K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1995