PHILIPS TDA6650TT

INTEGRATED CIRCUITS
DATA SHEET
TDA6650TT; TDA6651TT
5 V mixer/oscillator and low noise
PLL synthesizer for hybrid
terrestrial tuner (digital and analog)
Product specification
Supersedes data of 2003 Sep 11
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
CONTENTS
TDA6650TT;
TDA6651TT
10
HANDLING
11
THERMAL CHARACTERISTICS
12
CHARACTERISTICS
13
INTERNAL PIN CONFIGURATION
14
APPLICATION AND TEST INFORMATION
Tuning amplifier
Crystal oscillator
Examples of I2C-bus program sequences
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
14.1
14.2
14.3
7
FUNCTIONAL DESCRIPTION
15
PACKAGE OUTLINE
7.1
7.2
7.3
Mixer, Oscillator and PLL (MOPLL) functions
I2C-bus voltage
Phase noise, I2C-bus traffic and crosstalk
16
SOLDERING
16.1
8
I2C-BUS PROTOCOL
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
Write mode; R/W = 0
I2C-bus address selection
XTOUT output buffer and mode setting
Step frequency setting
AGC detector setting
Charge pump current setting
Automatic Loop Bandwidth Control (ALBC)
Read mode; R/W = 1
Status at Power-on reset
16.2
16.3
16.4
16.5
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
9
LIMITING VALUES
2004 Mar 22
2
17
DATA SHEET STATUS
18
DEFINITIONS
19
DISCLAIMERS
20
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
1
TDA6650TT;
TDA6651TT
FEATURES
• Single-chip 5 V mixer/oscillator and low phase noise
PLL synthesizer for TV and VCR tuners, dedicated to
hybrid (digital and analog) as well as pure digital
applications (DVB-T)
• Five possible step frequencies to cope with different
digital terrestrial TV and analog TV standards
2
• Eight charge pump currents between 40 and 600 µA to
reach the optimum phase noise performance over the
bands
• Digital and analog terrestrial tuners (OFDM, PAL, etc.)
• Cable tuners (QAM)
• Automatic Loop Bandwidth Control (ALBC) sets the
optimum phase noise performance for DVB-T channels
• Digital TV sets
• Digital set-top boxes.
• I2C-bus protocol compatible with 2.5, 3.3 and 5 V
microcontrollers:
– Address + 5 data bytes transmission (I2C-bus write
mode)
– Address + 1 status byte (I2C-bus read mode)
– Four independent I2C-bus addresses
• Five PMOS open-drain ports with 15 mA source
capability for band switching and general purpose; one
of these ports is combined with a 5-step ADC
• Wide band AGC detector for internal tuner AGC:
– Six programmable take-over points
– Two programmable time constants
– AGC flag
• In-lock flag
• Crystal frequency output buffer
• 33 V tuning voltage output
• Fractional-N programmable divider
• Balanced mixers with a common emitter input for the low
band and for the mid band (each single input)
• Balanced mixer with a common base input for the high
band (balanced input)
• 2-pin asymmetrical oscillator for the low band
• 2-pin symmetrical oscillator for the mid band
• 4-pin symmetrical oscillator for the high band
• Switched concept IF amplifier with both asymmetrical
and symmetrical outputs to drive low impedance or
SAW filters i.e. 500 Ω//40 pF.
2004 Mar 22
APPLICATIONS
3
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
3
The AGC detector provides a control that can be used in a
tuner to set the gain of the RF stage. Six AGC take-over
points are available by software. Two programmable AGC
time constants are available for search tuning and normal
tuner operation.
GENERAL DESCRIPTION
The TDA6650TT; TDA6651TT is a programmable 3-band
mixer/oscillator and low phase noise PLL synthesizer
intended for pure 3-band tuner concepts applied to hybrid
(digital and analog) terrestrial and cable TV reception.
The local oscillator signal is fed to the fractional-N divider.
The divided frequency is compared to the comparison
frequency into the fast phase detector which drives the
charge pump. The loop amplifier is also on-chip, including
the high-voltage transistor to drive directly the 33 V tuning
voltage without the need to add an external transistor.
The device includes three double balanced mixers for low,
mid and high bands, three oscillators for the corresponding
bands, a switchable IF amplifier, a wide band AGC
detector and a low noise PLL synthesizer. The frequencies
of the three bands are shown in Table 1. Two pins are
available between the mixer output and the IF amplifier
input to enable IF filtering for improved signal handling and
to improve the adjacent channel rejection.
Table 1
The comparison frequency is obtained from an on-chip
crystal oscillator. The crystal frequency can be output to
the XTOUT pin to drive the clock input of a digital
demodulation IC.
Recommended band limits in MHz for PAL and
DVB-T tuners; note 1
RF INPUT
Control data is entered via the I2C-bus; six serial bytes are
required to address the device, select the local
oscillator (LO) frequency, select the step frequency,
program the output ports and set the charge pump current
or select the ALBC mode, enable or disable the crystal
output buffer, select the AGC take-over point and time
constant and/or select a specific test mode. A status byte
concerning the AGC level detector and the ADC voltage
can be read out on the SDA line during a read operation.
During a read operation, the loop ‘in-lock’ flag, the
Power-on reset flag and the automatic loop bandwidth
control flag are read.
OSCILLATOR
BAND
MIN.
Low
44.25
MAX.
157.25
MIN.
83.15
MAX.
196.15
Mid
157.25
443.25
196.15
482.15
High
443.25
863.25
482.15
902.15
Note
1. RF input frequency is the frequency of the
corresponding picture carrier for analog standard.
The device has 4 programmable addresses. Each address
can be selected by applying a specific voltage to pin AS,
enabling the use of multiple devices in the same system.
The IF amplifier is switchable in order to drive both
symmetrical and asymmetrical outputs. When it is used as
an asymmetrical amplifier, the IFOUTB pin needs to be
connected to the supply voltage VCCA.
The I2C-bus is fast mode compatible, except for the timing
as described in the functional description and is
compatible with 5, 3.3 and 2.5 V microcontrollers
depending on the voltage applied to pin BVS.
Five open-drain PMOS ports are included on the IC. Two
of them, BS1 and BS2, are also dedicated to the selection
of the low, mid and high bands. PMOS port BS5 pin is
shared with the ADC.
4
TDA6650TT;
TDA6651TT
ORDERING INFORMATION
TYPE
NUMBER
TDA6650TT
TDA6651TT
2004 Mar 22
PACKAGE
NAME
TSSOP38
DESCRIPTION
plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
4
VERSION
SOT510-1
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
5
TDA6650TT;
TDA6651TT
BLOCK DIAGRAM
IFFIL1
handbook, full pagewidth
VCCA
n.c.
21 (18)
IFOUTA
IFFIL2
6 (33)
26 (13)
IFOUTB
7 (32)
28 (11)
27 (12)
(30) 9
IF
AMP
TDA6650TT
(TDA6651TT)
AGC
DETECTOR
AGC
flag
AL0, AL1, AL2
ATC
(10) 29
(1) 38
LBIN
4 (35)
LOW
INPUT
BS1
LOW
MIXER
BS1
MID
MIXER
BS2
LOW
OSCILLATOR
(2) 37
(5) 34
MBIN
HBIN1
HBIN2
3 (36)
MID
INPUT
BS2
MID
OSCILLATOR
HIGH
INPUT
BS1 . BS2
BS1 . BS2
HIGH
OSCILLATOR
(7) 32
(6) 33
RFGND
VCCD
5 (34)
(3) 36
24 (15)
N [14:0]
FRACTIONAL
DIVIDER
OUTPUT
BUFFER
R0, R1,
R2
LOOP
AMP
XTAL1
XTAL2
SCL
SDA
AS
BVS
MOSCIN1
(21) 18
HOSCIN1
HOSCOUT1
HOSCOUT2
HOSCIN2
OSCGND
XTOUT
(17) 22
VT
19 (20)
20 (19)
CRYSTAL
OSCILLATOR
16 (23)
17 (22)
TRANSCEIVER
13 (26)
ADC
FRACTIONAL
SPURIOUS
BS5BS1 COMPENSATION
BAND SWITCH
OUTPUT PORTS
AGC
14
(25)
8
(31)
10
(29)
11
(28)
12
(27)
(14) 25
FCE723
BS3
ADC/
BS5
BS4
BS1
BS2
The pin numbers in parenthesis represent the TDA6651TT.
Fig.1 Block diagram.
5
CP
T0, T1, CP0, CP1,
T2
CP2
LOCK
DETECTOR
I2C-BUS
(16) 23
CHARGE
PUMP
REFERENCE
DIVIDER
15 (24)
POR
2004 Mar 22
LOSCOUT
T0, T1, T2
PHASE
COMPARATOR
FRACTIONAL
CALCULATOR
LOSCIN
MOSCIN2
(8) 31
HIGH
MIXER
IFGND
(4) 35
(9) 30
1 (38)
2 (37)
AGC
PLLGND
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
6
TDA6650TT;
TDA6651TT
PINNING
PIN
SYMBOL
DESCRIPTION
TDA6650TT
TDA6651TT
HBIN1
1
38
high band RF input 1
HBIN2
2
37
high band RF input 2
MBIN
3
36
mid band RF input
LBIN
4
35
low band RF input
RFGND
5
34
RF ground
IFFIL1
6
33
IF filter output 1
IFFIL2
7
32
IF filter output 2
BS4
8
31
PMOS open-drain output port 4 for general purpose
AGC
9
30
AGC output
BS3
10
29
PMOS open-drain output port 3 for general purpose
BS2
11
28
PMOS open-drain output port 2 to select the mid band
BS1
12
27
PMOS open-drain output port 1 to select the low band
BVS
13
26
bus voltage selection input
ADC/BS5
14
25
ADC input or PMOS open-drain output port 5 for general purpose
SCL
15
24
I2C-bus serial clock input
SDA
16
23
I2C-bus serial data input and output
AS
17
22
I2C-bus address selection input
XTOUT
18
21
crystal frequency buffer output
XTAL1
19
20
crystal oscillator input 1
XTAL2
20
19
crystal oscillator input 2
n.c
21
18
not connected
VT
22
17
tuning voltage output
CP
23
16
charge pump output
VCCD
24
15
supply voltage for the PLL part
PLLGND
25
14
PLL ground
VCCA
26
13
supply voltage for the analog part
IFOUTB
27
12
IF output B for symmetrical amplifier and asymmetrical IF amplifier
switch input
IFOUTA
28
11
IF output A
IFGND
29
10
IF ground
HOSCIN1
30
9
high band oscillator input 1
HOSCOUT1
31
8
high band oscillator output 1
HOSCOUT2
32
7
high band oscillator output 2
HOSCIN2
33
6
high band oscillator input 2
MOSCIN1
34
5
mid band oscillator input 1
MOSCIN2
35
4
mid band oscillator input 2
OSCGND
36
3
oscillators ground
LOSCOUT
37
2
low band oscillator output
LOSCIN
38
1
low band oscillator input
2004 Mar 22
6
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
handbook, halfpage
handbook, halfpage
HBIN1 1
38 LOSCIN
HBIN2 2
37 LOSCOUT
MBIN 3
LOSCIN
1
38 HBIN1
LOSCOUT
2
37 HBIN2
36 OSCGND
OSCGND
3
36 MBIN
LBIN 4
35 MOSCIN2
MOSCIN2
4
35 LBIN
RFGND 5
34 MOSCIN1
MOSCIN1
5
34 RFGND
IFFIL1 6
33 HOSCIN2
HOSCIN2
6
33 IFFIL1
IFFIL2 7
32 HOSCOUT2
HOSCOUT2
7
32 IFFIL2
31 HOSCOUT1
HOSCOUT1
8
BS4 8
TDA6650TT
AGC 9
30 HOSCIN1
BS3 10
9
30 AGC
29 IFGND
IFGND 10
29 BS3
BS2 11
28 IFOUTA
IFOUTA 11
28 BS2
BS1 12
27 IFOUTB
IFOUTB 12
27 BS1
BVS 13
26 VCCA
VCCA 13
26 BVS
HOSCIN1
25 PLLGND
ADC/BS5 14
23 CP
CP 16
23 SDA
22 VT
VT 17
22 AS
21 n.c.
n.c. 18
SDA 16
AS 17
20 XTAL2
20 XTAL1
FCE874
Fig.2 Pin configuration TDA6650TT.
Fig.3 Pin configuration TDA6651TT.
FUNCTIONAL DESCRIPTION
a fractional calculator on the chip that generates the data
for the fractional divider as well as the reference divider
ratio, depending on the step frequency selected. The
crystal oscillator requires a 4 MHz crystal in series with an
18 pF capacitor between pins XTAL1 and XTAL2.
Mixer, Oscillator and PLL (MOPLL) functions
Bit BS1 enables the BS1 port, the low band mixer and the
low band oscillator. Bit BS2 enables the BS2 port, the mid
band mixer and the mid band oscillator. When both BS1
and BS2 bits are logic 0, the high band mixer and the high
band oscillator are enabled.
The output of the phase comparator drives the charge
pump and the loop amplifier section. This amplifier has an
on-chip high voltage drive transistor. Pin CP is the output
of the charge pump, and pin VT is the pin to drive the
tuning voltage to the varicap diodes of the oscillators and
the tracking filters. The loop filter has to be connected
between pins CP and VT. The spurious signals introduced
by the fractional divider are automatically compensated by
the spurious compensation block.
The oscillator signal is applied to the fractional-N
programmable divider. The divided signal fdiv is fed to the
phase comparator where it is compared in both phase and
frequency with the comparison frequency fcomp. This
frequency is derived from the signal present on the crystal
oscillator fxtal and divided in the reference divider. There is
2004 Mar 22
21 XTOUT
XTAL2 19
FCE724
7.1
25 ADC/BS5
24 SCL
24 VCCD
XTAL1 19
PLLGND 14
VCCD 15
SCL 15
XTOUT 18
7
31 BS4
TDA6651TT
7
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
It is possible to drive the clock input of a digital
demodulation IC from pin XTOUT with the 4 MHz signal
from the crystal oscillator. This output is also used to
output 1/2fdiv and fcomp signals in a specific test mode (see
Table 6). It is possible to switch off this output, which is
recommended when it is not used.
7.3
Linked to this noise improvement, some disturbances may
become visible while they were not visible because they
were hidden into the noise in analog dedicated
applications and circuits.
In addition to the BS1 and BS2 output ports that are used
for the band selection, there are three general purpose
ports BS3, BS4 and BS5. All five ports are PMOS
open-drain type, each with 15 mA drive capability. The
connection for port BS5 and the ADC input is combined on
one pin. It is not possible to use the ADC if port BS5 is
used.
This is especially true for disturbances coming from the
I2C-bus traffic, whatever this traffic is intended for the
MOPLL or for another slave on the bus.
To avoid this I2C-bus crosstalk and be able to have a clean
noise spectrum, it is necessary to use a bus gate that
enables the signal on the bus to drive the MOPLL only
when the communication is intended for the tuner part
(such a kind of I2C-bus gate is included into the Philips
terrestrial channel decoders), and to avoid unnecessary
repeated sending of the same information.
The AGC detector compares the level at the IF amplifier
output to a reference level which is selected from
6 different levels via the I2C-bus. The time constant of the
AGC can be selected via the I2C-bus to cope with normal
operation as well as with search operation.
8
When the output level on pin AGC is higher than the
threshold VRMH, then bit AGC = 1. When the output level
on pin AGC is lower than the threshold VRML, then
bit AGC = 0. Between these two thresholds, bit AGC is not
defined. The status of the AGC bit can be read via the
I2C-bus according to the read mode as described in
Table 12.
The TDA6650TT; TDA6651TT fulfils the fast mode
I2C-bus, according to the Philips I2C-bus specification (see
Chapter 20), except for the timing as described in Fig.4.
The I2C-bus interface is designed in such a way that the
pins SCL and SDA can be connected to 5, 3.3 or to 2.5 V
pulled-up I2C-bus lines, depending on the voltage applied
to pin BVS (see Table 2).
The I2C-bus lines SCL and SDA can be connected to an
I2C-bus system tied to 2.5, 3.3 or 5 V. The choice of the
bus input threshold voltages is made with pin BVS that can
be left open-circuit, connected to the supply voltage or to
ground (see Table 2).
I2C-bus voltage selection
PIN BVS
BUS
CONNECTION VOLTAGE
LOGIC LEVEL
LOW
HIGH
To ground
2.5 V
Open-circuit
3.3 V
0 to 1.0 V
2.3 to 5.5 V
To VCC
5V
0 to 1.5 V
3.0 to 5.5 V
2004 Mar 22
I2C-BUS PROTOCOL
The TDA6650TT; TDA6651TT is controlled via the
two-wire I2C-bus. For programming, there is one device
address (7 bits) and the R/W bit for selecting read or write
mode. To be able to have more than one MOPLL in an
I2C-bus system, one of four possible addresses is selected
depending on the voltage applied to address selection
pin AS (see Table 5).
I2C-bus voltage
Table 2
Phase noise, I2C-bus traffic and crosstalk
While the TDA6650TT; TDA6651TT is dedicated for hybrid
terrestrial applications, the low noise PLL will clean up the
noise spectrum of the VCOs close to the carrier to reach
noise levels at 1 kHz offset from the carrier compatible with
e.g. DVB-T reception.
For test and alignment purposes, it is also possible to
release the tuning voltage output by selecting the sinking
mode (see Table 6), and by applying an external voltage
on pin VT.
7.2
TDA6650TT;
TDA6651TT
0 to 0.75 V 1.75 to 5.5 V
8
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
8.1
Write mode; R/W = 0
TDA6650TT;
TDA6651TT
sent by the controller, additional data bytes can be entered
without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission
(STOP condition). Each control byte is loaded after the
8th clock pulse of the corresponding control byte. Main
divider data are valid only if no new I2C-bus transmission
is started (START condition) during the computation
period of 50 µs.
After the address transmission (first byte), data bytes can
be sent to the device (see Table 3). Five data bytes are
needed to fully program the TDA6650TT; TDA6651TT.
The I2C-bus transceiver has an auto-increment facility that
permits programming the device within one single
transmission (address + 5 data bytes).
The TDA6650TT; TDA6651TT can also be partly
programmed on the condition that the first data byte
following the address is byte 2 (divider byte 1) or byte 4
(control byte 1). The first bit of the first data byte
transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I2C-bus STOP condition is
Both DB1 and DB2 need to be sent to change the main
divider ratio. If the value of the ratio selection bits R2, R1
and R0 are changed, the bytes DB1 and DB2 have to be
sent in the same transmission.
50 µs
handbook, full pagewidth
START
ADDRESS DIVIDER
BYTE
BYTE 1
DIVIDER CONTROL CONTROL CONTROL CONTROL
STOP
BYTE 2
BYTE 1
BYTE 2
BYTE 1
BYTE 2
START
I2C transmission dedicated to
the MOPLL
ADDRESS
BYTE
I2C transmission
dedicated to
another IC
FCE921
Fig.4 Example of I2C-bus transmission frame.
Table 3
I2C-bus write data format
BIT
NAME
BYTE
ACK
MSB(1)
LSB
Address byte
1
1
1
0
0
0
MA1
MA0
R/W = 0
A
Divider byte 1 (DB1)
2
0
N14
N13
N12
N11
N10
N9
N8
A
Divider byte 2 (DB2)
3
N7
N6
N5
N4
N3
N2
N1
N0
A
Control byte 1
(CB1); see Table 4
4
Control byte 2 (CB2)
5
1
T/A = 1
T2
T1
T0
R2
R1
R0
A
1
T/A = 0
0
0
ATC
AL2
AL1
AL0
A
CP2
CP1
CP0
BS5
BS4
BS3
BS2
BS1
A
Note
1. MSB is transmitted first.
2004 Mar 22
9
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Table 4
TDA6650TT;
TDA6651TT
Description of write data format bits
BIT
DESCRIPTION
A
acknowledge
MA1 and MA0
programmable address bits; see Table 5
R/W
logic 0 for write mode
N14 to N0
programmable LO frequency; N = N14 × 214 + N13 × 213 + N12 × 212 + ... + N1 × 21 + N0
T/A
test/AGC bit
T/A = 0: the next six bits sent are AGC settings
T/A = 1: the next six bits sent are test and reference divider ratio settings
T2, T1 and T0
test bits; see Table 6
R2, R1, and R0
reference divider ratio and programmable frequency step; see Table 7
ATC
AGC current setting and time constant; capacitor on pin AGC = 150 nF
ATC = 0: AGC current = 220 nA; AGC time constant = 2 s
ATC = 1: AGC current = 9 µA; AGC time constant = 50 ms
AL2, AL1 and AL0
AGC take-over point bits; see Table 8
CP2, CP1 and CP0
charge pump current; see Table 9
BS5, BS4, BS3,
BS2 and BS1
PMOS ports control bits
BSn = 0: corresponding port is off, high-impedance state (status at Power-on reset)
BSn = 1: corresponding port is on; VO = VCC − VDS(sat)
8.1.1
I2C-BUS ADDRESS SELECTION
The device address contains programmable address bits MA1 and MA0, which offer the possibility of having up to four
MOPLL ICs in one system. Table 5 gives the relationship between the voltage applied to the AS input and the MA1 and
MA0 bits.
Table 5
Address selection
VOLTAGE APPLIED TO PIN AS
MA1
MA0
0 V to 0.1VCC
0
0
0.2VCC to 0.3VCC or open-circuit
0
1
0.4VCC to 0.6VCC
1
0
0.9VCC to VCC
1
1
2004 Mar 22
10
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
8.1.2
recommended to disable it, by setting T[2:0] to 000. This
pin is also used to output 1/2fdiv and fcomp in a test mode.
At Power-on, the XTOUT output buffer is set to on,
supplying the fxtal signal. The relation between the signal
on pin XTOUT and the setting of theT[2:0] bits is given in
Table 6.
XTOUT OUTPUT BUFFER AND MODE SETTING
The crystal frequency can be sent to pin XTOUT and used
in the application, for example to drive the clock input of a
digital demodulator, saving a quartz crystal in the bill of
material. To output fxtal, it is necessary to set T[2:0] to 001.
If the output signal on this pin is not used, it is
Table 6
TDA6650TT;
TDA6651TT
XTOUT buffer status and test modes
T2
T1
T0
PIN XTOUT
0
0
0
disabled
normal mode with XTOUT buffer off
0
0
1
normal mode with XTOUT buffer on
0
1
0
fxtal (4
1/ f
2 div
0
1
1
fxtal (4 MHz)
switch ALBC on or off (note 1)
1
0
0
test mode
1
0
1
fcomp
1/ f
2 div
1
1
0
fxtal (4 MHz)
charge pump sinking current (note 2)
1
1
1
disabled
charge pump sourcing current
MHz)
MODE
charge pump off
test mode
Notes
1. Automatic Loop Bandwidth Control (ALBC) is disabled at Power-on reset. After Power-on reset this feature is
enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts like a toggle
switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC, two consecutive Control
byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will be switched on or off and one byte
programming the test mode to be selected (see Table 23, example of I2C-bus sequence).
2. This is the default mode at Power-on reset. This mode disables the tuning voltage.
8.1.3
STEP FREQUENCY SETTING
The step frequency is set by three bits, giving five steps to cope with different application requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either
4, 2 or 1 MHz.
Table 7 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0
are changed, it is necessary to re-send the data bytes DB1 and DB2.
Table 7
Reference divider ratio select bits
R2
R1
R0
REFERENCE
DIVIDER RATIO
FREQUENCY
COMPARISON
FREQUENCY STEP
0
0
0
2
2 MHz
62.5 kHz
0
0
1
1
4 MHz
142.86 kHz
0
1
0
1
4 MHz
166.67 kHz
0
1
1
4
1 MHz
50 kHz
1
0
0
1
4 MHz
125 kHz
1
0
1
−
−
reserved
1
1
0
−
−
reserved
1
1
1
−
−
reserved
2004 Mar 22
11
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
8.1.4
TDA6650TT;
TDA6651TT
AGC DETECTOR SETTING
The AGC take-over point can be selected out of 6 levels according to Table 8.
Table 8
AGC programming
AL2
AL1
AL0
TYPICAL TAKE-OVER POINT LEVEL
0
0
0
124 dBµV (p-p)
0
0
1
121 dBµV (p-p)
0
1
0
118 dBµV (p-p)
0
1
1
115 dBµV (p-p)
1
0
0
112 dBµV (p-p)
1
0
1
109 dBµV (p-p)
1
1
0
IAGC = 0; note 1
1
1
1
VAGC = 3.5 V; note 2
Notes
1. The AGC current sources are disabled. The AGC output goes into a high-impedance state and an external AGC
source can be connected in parallel and will not be influenced.
2. The AGC detector is disabled and IAGC = 9 µA.
8.1.5
CHARGE PUMP CURRENT SETTING
The charge pump current can be chosen from 8 values depending on the value of bits CP2, CP1 and CP0 bits; see
Table 9. The programming of the CP bits are not taken into account when ALBC mode is in use.
Table 9
8.1.6
Charge pump current
CP2
CP1
CP0
CHARGE PUMP CURRENT
NUMBER
TYPICAL CURRENT
(ABSOLUTE VALUE IN µA)
0
0
0
1
38
0
0
1
2
54
0
1
0
3
83
0
1
1
4
122
1
0
0
5
163
1
0
1
6
254
1
1
0
7
400
1
1
1
8
580
AUTOMATIC LOOP BANDWIDTH CONTROL (ALBC)
tuner, to set the charge pump current to different values
depending on the band and frequency used. This is to
cope with the variations of the different parameters that set
the bandwidth. The selection can be done in the
application and requires for each frequency to program not
only the divider ratios, but also the band and the best
charge pump current.
In a PLL controlled VCO in which the PLL reduces phase
noise close to the carrier, there is an optimum loop
bandwidth corresponding to the minimum integrated
phase jitter. This loop bandwidth depends on different
parameters like the VCO slope, the loop filter components,
the dividing ratio and the gain of the phase detector and
charge pump.
The TDA6650TT; TDA6651TT includes the ALBC feature
that automatically sets the band and the charge pump
current, provided the IC is used in the DVB-T standard
In order to reach the best phase noise performance it is
necessary, especially in a wide band system like a digital
2004 Mar 22
12
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
application shown in Figs 27 and 28. This feature is
activated by setting bits T[2:0] = 011 after Power-on reset.
This feature is disabled when the same bits are set again.
When ALBC is activated, the output ports BS1, BS2
and BS3 are not programmed by the corresponding
TDA6650TT;
TDA6651TT
BS bits, but are set according to Tables 10 and 11. When
ALBC is active, bit ALBC = 1. Table 11 summarizes the
programming of the band selection and the charge pump
current when ALBC is active.
Table 10 ALBC settings
BIT
CHARGE
PUMP
CURRENT
PORT
BS3
BS2
BS1
see
Table 11
follows
bit BS3
off
off
off
on
on
off
ALBC
BS3
BS2
BS1
BAND
SELECTED
0
X
0
0
high
0
X
0
1
low
0
X
1
0
mid
0
X
1
1
forbidden
1
X
X
X
depends on LO program, shown in Table 11
Table 11 ALBC band selection and charge current setting
LO FREQUENCY
BAND
80 to 92 MHz
low
CHARGE PUMP CURRENT
NUMBER
2
92 to 144 MHz
3
144 to 156 MHz
4
156 to 176 MHz
5
176 to 184 MHz
6
184 to 196 MHz
7
196 to 224 MHz
mid
2
224 to 296 MHz
3
296 to 380 MHz
4
380 to 404 MHz
5
404 to 448 MHz
6
448 to 472 MHz
7
472 to 484 MHz
484 to 604 MHz
8
high
4
604 to 676 MHz
5
676 to 752 MHz
6
752 to 868 MHz
7
868 to 904 MHz
8
2004 Mar 22
13
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
8.2
TDA6650TT;
TDA6651TT
A second data byte can be read from the device if the
microcontroller generates an acknowledge on the SDA
line (master acknowledge). End of transmission will occur
if no master acknowledge occurs. The device will then
release the data line to allow the microcontroller to
generate a STOP condition.
Read mode; R/W = 1
Data can be read from the device by setting the R/W bit
to 1 (see Table 12). After the device address has been
recognized, the device generates an acknowledge pulse
and the first data byte (status byte) is transferred on the
SDA line (MSB first). Data is valid on the SDA line during
a HIGH level of the SCL clock signal.
Table 12 I2C-bus read data format
BIT
NAME
BYTE
ACK
MSB(1)
LSB
Address byte
1
1
1
0
0
0
MA1
MA0
R/W = 1
A
Status byte
2
POR
FL
ALBC
1
AGC
A2
A1
A0
−
Note
1. MSB is transmitted first.
Table 13 Description of read data format bits
BIT
DESCRIPTION
A
acknowledge bit
POR
Power-on reset flag
POR = 0, normal operation
POR = 1, Power-on reset
FL
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
ALBC
automatic loop bandwidth control flag
ALBC = 0, no automatic loop bandwidth control
ALBC = 1, automatic loop bandwidth control selected
AGC
internal AGC flag
AGC = 0 when internal AGC is active (VAGC < VRML)
AGC = 1 when internal AGC is not active (VAGC > VRMH)
A2, A1, A0
2004 Mar 22
digital outputs of the 5-level ADC; see Table 14
14
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Table 14 ADC levels
VOLTAGE APPLIED TO PIN ADC(1)
A2
A1
A0
0.6VCC to VCC
1
0
0
0.45VCC to 0.6VCC
0
1
1
0.3VCC to 0.45VCC
0
1
0
0.15VCC to 0.3VCC
0
0
1
0 to 0.15VCC
0
0
0
Note
1. Accuracy is ±0.03VCC. Bit BS5 must be set to logic 0 to disable the BS5 output port. The BS5 output port uses the
same pin as the ADC and can not be used when the ADC is in use.
8.3
Status at Power-on reset
At power on or when the supply voltage drops below approximately 2.85 V (at Tamb = 25 °C), internal registers are set
according to Table 15.
At power on, the charge pump current is set to 580 µA, the test bits T[2:0] are set to 110 which means that the charge
pump is sinking current, the tuning voltage output is disabled and the ALBC function is disabled. The XTOUT buffer is
on, driving the 4 MHz signal from the crystal oscillator and all the ports are off. As a consequence, the high band is
selected by default.
Table 15 Default setting at Power-on reset
BIT(1)
NAME
BYTE
MSB
LSB
Address byte
1
1
1
0
0
0
MA1
MA0
X
Divider byte 1 (DB1)
2
0
N14 = X
N13 = X
N12 = X
N11 = X
N10 = X
N9 = X
N8 = X
Divider byte 2 (DB2)
3
N7 = X
N6 = X
N5 = X
N4 = X
N3 = X
N2 = X
N1 = X
N0 = X
Control byte 1 (CB1)
4
1
T/A = X;
note 2
T2 = 1
T1 = 1
T0 = 0
R2 = X
R1 = X
R0 = X
1
T/A = X;
note 3
0
0
ATC = 0
AL2 = 0
AL1 = 1
AL0 = 0
CP2 = 1
CP1 = 1
CP0 = 1
BS5 = 0
BS4 = 0
BS3 = 0
BS2 = 0
BS1 = 0
Control byte 2 (CB2)
5
Notes
1. X means that this bit is not set or reset at Power-on reset.
2. The next six bits are written, when bit T/A = 1 in a write sequence.
3. The next six bits are written, when bit T/A = 0 in a write sequence.
2004 Mar 22
15
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); positive currents are entering the IC and
negative currents are going out of the IC; all voltages are referenced to ground (GND); note 1
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA,
VCCD
supply voltage
−0.3
+6
V
VVT
tuning voltage output
−0.3
+35
V
VSDA
serial data input and output voltage
−0.3
+6
V
ISDA
serial data output current
0
10
mA
VSCL
serial clock input voltage
−0.3
+6
V
VAS
address selection input voltage
−0.3
+6
V
Vn
voltage on all other inputs, outputs and
combined inputs and outputs, except
GNDs
4.5 V< VCC < 5.5 V
−0.3
VCC + 0.3
V
IBSn
PMOS port output current
corresponding port on;
open-drain
−20
0
mA
IBS(tot)
sum of all PMOS port output currents
open-drain
−50
0
mA
tsc(max)
maximum short-circuit time
each pin to VCC or to GND
−
10
s
Tstg
storage temperature
−40
+150
°C
Tamb
ambient temperature
−20
Tamb(max)(2)
°C
Tj
junction temperature
−
+150
°C
during acknowledge
Notes
1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. Maximum
ratings cannot be accumulated.
2. The maximum allowed ambient temperature Tamb(max) depends on the assembly conditions of the package and
especially on the design of the PCB. The application mounting must be done in such a way that the maximum junction
temperature Tj is never exceeded. An estimation of the junction temperature can be obtained through measurement
of the temperature of the top centre of the package (Tpackage). The temperature difference junction to case (∆Tj-c) is
estimated at about 13 °C on the demoboard (PCB 827-3).
The junction temperature is: Tj = Tpackage + ∆Tj-c
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it
is desirable to take normal precautions appropriate to handling integrated circuits.
2004 Mar 22
16
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
VALUE
UNIT
TDA6650TT
82
K/W
TDA6651TT
74
K/W
thermal resistance from
junction to ambient
CONDITIONS
notes 1, 2 and 3
Notes
1. Measured in free air as defined by JEDEC standard JESD51-2
2. These values are given for information only. The thermal resistance depends strongly on the nature and design of
the PCB used in the application.The thermal resistance given corresponds to the value that can be measured on a
multilayer PCB (4 layers) as defined by JEDEC standard.
3. The junction temperature influences strongly the reliability of an IC. The PCB used in the application contributes in a
large part to the overall thermal characteristic. It must therefore be insured that the junction temperature of the IC
never exceeds Tj(max) = 150 °C at the maximum ambient temperature.
12 CHARACTERISTICS
VCCA = VCCD = 5 V, Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of
the IC; the performances of the circuits are measured in the measurement circuits Figs 27 and 28 for digital application
or in the measurement circuits Figs 29 and 30 for hybrid application; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCC
supply voltage
ICC
supply current
4.5
5.0
5.5
V
80
96
115
mA
one PMOS port on: sourcing 15 mA 96
112
131
mA
two PMOS ports on: one port
sourcing 15 mA and one other port
sourcing 5 mA
117
136
mA
2.85
3.5
V
−
1024
MHz
PMOS ports off
101
General functions
VPOR
Power-on reset supply
voltage
∆flock
frequency range the PLL is
able to synthesize
Power-on reset active if VCC < VPOR −
64
Crystal oscillator; note 1
fxtal
crystal frequency
−
4.0
−
MHz
Zxtal
input impedance (absolute
value)
fxtal = 4 MHz; VCC = 4.5 V to 5.5 V;
Tamb = −20 °C to + 85 °C
350
430
−
Ω
Pxtal
crystal drive level
fxtal = 4 MHz; note 2
−
70
−
µW
−10
−
−
µA
PMOS ports: pins BS1, BS2, BS3, BS4 and BS5
ILO(off)
2004 Mar 22
output leakage current in
off state
VCC = 5.5 V; VBS = 0 V
17
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
VDS(sat)
PARAMETER
output saturation voltage
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
TYP.
MAX.
UNIT
only corresponding buffer is on,
sourcing 15 mA;
VDS(sat) = VCC − VBS
−
0.2
0.4
V
ADC input: pin ADC
Vi
ADC input voltage
see Table 14
0
−
5.5
V
IIH
HIGH-level input current
VADC = VCC
−
−
10
µA
IIL
LOW-level input current
VADC = 0 V
−10
−
−
µA
Address selection input: pin AS
IIH
HIGH-level input current
VAS = 5.5 V
−
−
10
µA
IIL
LOW-level input current
VAS = 0 V
−10
−
−
µA
Bus voltage selection input: pin BVS
IIH
HIGH-level input current
VBVS = 5.5 V
−
−
100
µA
IIL
LOW-level input current
VBVS = 0 V
−100
−
−
µA
note 3
−
400
−
mV
−
175
−
Ω
frequency on SCL
−
−
400
kHz
Buffered output: pin XTOUT
Vo(p-p)
square wave AC output
voltage (peak-to peak
value)
Zo
output impedance
I2C-bus
INPUTS: PINS SCL AND SDA
fclk
clock frequency
VIL
LOW-level input voltage
VIH
IIH
IIL
HIGH-level input voltage
HIGH-level input current
LOW-level input current
VBVS = 0 V
0
−
0.75
V
VBVS = 2.5 V or open-circuit
0
−
1.0
V
VBVS = 5 V
0
−
1.5
V
VBVS = 0 V
1.75
−
5.5
V
VBVS = 2.5 V or open-circuit
2.3
−
5.5
V
VBVS = 5 V
3.0
−
5.5
V
VCC = 0 V; VBUS = 5.5 V
−
−
10
µA
VCC = 5.5 V; VBUS = 5.5 V
−
−
10
µA
VCC = 0 V; VBUS = 1.5 V
−
−
10
µA
VCC = 5.5 V; VBUS = 0 V
−10
−
−
µA
OUTPUT: PIN SDA
ILH
leakage current
VSDA = 5.5 V
−
−
10
µA
VO(ack)
output voltage during
acknowledge
ISDA = 3 mA
−
−
0.4
V
Charge pump output: pin CP
Io
output current (absolute
value)
see Table 9
−
−
−
µA
IL(off)
off-state leakage current
charge pump off (T[2:0] = 010)
−15
0
+15
nA
2004 Mar 22
18
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
PARAMETER
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
TYP.
MAX.
UNIT
Tuning voltage output: pin VT
IL(off)
leakage current when
switched-off
tuning supply voltage = 33 V
−
−
10
µA
Vo(cl)
output voltage when the
loop is closed
charge pump off (T[2:0] = 010);
tuning supply voltage = 33 V;
RL = 15 kΩ
0.3
−
32.7
V
digital application
−
0.5
−
deg
hybrid application
−
0.6
−
deg
43.25
−
157.25 MHz
fRF = 44.25 MHz
21
24
27
dB
fRF = 157.25 MHz
21
24
27
dB
fRF = 44.25 MHz
25
28
31
dB
fRF = 157.25 MHz
25
28
31
dB
fRF = 50 MHz
−
8.0
10.0
dB
fRF = 150 MHz
−
8.0
10.0
dB
fRF = 44.25 MHz
107
110
−
dBµV
fRF = 157.25 MHz
107
110
−
dBµV
fRF = 44.25 MHz
117
120
−
dBµV
fRF = 157.25 MHz
117
120
−
dBµV
Noise performance
Jφ(rms)
phase jitter (RMS value)
integrated between 1 kHz and
1 MHz offset from the carrier
Low band mixer, including IF amplifier
fRF
RF frequency
picture carrier; note 4
Gv
voltage gain
asymmetrical IF output; RL = 75 Ω;
see Fig.14
symmetrical IF output;
RL = 1.25 kΩ; see Fig.15
NF
Vo
noise figure
output voltage causing 1%
cross modulation in
channel
see Figs 16 and 17
asymmetrical application;
see Fig.18; note 5
symmetrical application;
see Fig.19; note 5
Vi
input voltage causing
asymmetrical IF output
750 Hz frequency
deviation pulling in channel
−
90
−
dBµV
INTSO2
channel SO2 beat
VRFpix = 80 dBµV; note 6
57
60
−
dBc
Vi(lock)
input level without lock-out
see Fig.25; note 7
−
−
120
dBµV
Gi
input conductance
Ci
2004 Mar 22
input capacitance
fRF = 44.25 MHz; see Fig.5
−
0.13
−
mS
fRF = 157.25 MHz; see Fig.5
−
0.11
−
mS
fRF = 44.25 to 157.25 MHz;
see Fig.5
−
1.36
−
pF
19
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
PARAMETER
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
TYP.
MAX.
UNIT
Mid band mixer, including IF amplifier
157.25 −
443.25 MHz
fRF = 157.25 MHz
21
24
27
dB
fRF = 443.25 MHz
21
24
27
dB
fRF = 157.25 MHz
25
28
31
dB
fRF = 443.25 MHz
25
28
31
dB
fRF = 150 MHz
−
8.0
10.0
dB
fRF = 300 MHz
−
9.0
11.0
dB
fRF = 157.25 MHz
107
110
−
dBµV
fRF = 443.25 MHz
107
110
−
dBµV
fRF = 157.25 MHz
117
120
−
dBµV
fRF = 443.25 MHz
117
120
−
dBµV
−
80
−
dBµV
dBµV
fRF
RF frequency
picture carrier; note 4
Gv
voltage gain
asymmetrical IF output;
load = 75 Ω; see Fig.14
symmetrical IF output;
load = 1.25 kΩ; see Fig.15
NF
Vo
noise figure
output voltage causing 1%
cross modulation in
channel
see Figs 16 and 17
asymmetrical application;
see Fig.18; note 5
symmetrical application;
see Fig.19; note 5
Vf(N+5)-1
(N + 5) − 1 MHz pulling
Vi
input voltage causing
asymmetrical IF output
750 Hz frequency
deviation pulling in channel
−
89
−
Vi(lock)
input level without lock-out
see Fig.25; note 7
−
−
120
dBµV
Gi
input conductance
see Fig.6
−
0.3
−
mS
Ci
input capacitance
see Fig.6
−
1.1
−
pF
443.25 −
863.25 MHz
fRF = 443.25 MHz
31.5
34.5
37.5
dB
fRF = 863.25 MHz
31.5
34.5
37.5
dB
fRF = 443.25 MHz
35.5
38.5
41.5
dB
fRF = 863.25 MHz
35.5
38.5
41.5
dB
fRF(wanted) = 443.25 MHz;
fosc = 482.15 MHz;
fRF(unwanted) = 482.25 MHz; note 8
High band mixer, including IF amplifier
fRF
RF frequency
picture carrier; note 4
Gv
voltage gain
asymmetrical IF output;
load = 75 Ω; see Fig.20
symmetrical IF output;
load = 1.25 kΩ; see Fig.21
2004 Mar 22
20
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
NF
Vo
PARAMETER
noise figure, not corrected
for image
output voltage causing 1%
cross modulation in
channel
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
TYP.
MAX.
UNIT
see Fig.22
fRF = 443.25 MHz
−
6.0
8.0
dB
fRF = 863.25 MHz
−
7.0
9.0
dB
fRF = 443.25 MHz
107
110
−
dBµV
fRF = 863.25 MHz
107
110
−
dBµV
fRF = 443.25 MHz
117
120
−
dBµV
fRF = 863.25 MHz
117
120
−
dBµV
asymmetrical application;
see Fig.23; note 5
symmetrical application;
see Fig.24; note 5
Vi(lock)
input level without lock-out
see Fig.26; note 7
−
−
120
dBµV
Vf(N+5)-1
(N + 5) − 1 MHz pulling
fRF(wanted) = 815.25 MHz;
fosc = 854.15 MHz;
fRF(unwanted) = 854.25 MHz; note 8
−
80
−
dBµV
Vi
input voltage causing
asymmetrical IF output
750 Hz frequency
deviation pulling in channel
−
79
−
dBµV
Zi
input impedance
(RS + jLSω)
RS
−
35
−
Ω
LS
−
8
−
nH
RS
−
36
−
Ω
LS
−
8
−
nH
fRF = 443.25 MHz; see Fig.7
fRF = 863.25 MHz; see Fig.7
Low band oscillator
fosc
oscillator frequency
note 9
83.15
−
196.15 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
note 10
−
110
−
kHz
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V with
compensation; note 11
−
900
−
kHz
Φosc(dig)
phase noise, carrier to
sideband noise in digital
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 8, 27 and 28
82
95
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 9, 27 and 28
87
100
−
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 10, 27 and 28
104
110
−
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 27 and 28
−
117
−
dBc/Hz
2004 Mar 22
21
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
Φosc(hyb)
RSCp-p
PARAMETER
phase noise, carrier to
sideband noise in hybrid
application
ripple susceptibility of VCC
(peak-to-peak value)
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
TYP.
MAX.
UNIT
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 11, 29, and 30
80
95
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 12, 29, and 30
85
96
−
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 13, 29, and 30
104
110
−
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 29 and 30
−
117
−
dBc/Hz
VCC = 5 V ±5%; worst case in the
frequency range; ripple frequency
500 kHz; note 12
15
200
−
mV
Mid band oscillator
fosc
oscillator frequency
note 9
196.15 −
482.15 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
note 10
−
110
−
kHz
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V with
compensation; note 11
−
1500
−
kHz
Φosc(dig)
phase noise, carrier to
sideband noise in digital
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 8, 27 and 28
85
90
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 9, 27 and 28
87
95
−
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 10, 27 and 28
104
110
−
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 27 and 28
−
115
−
dBc/Hz
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 11, 29 and 30
82
88
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 12, 29 and 30
85
90
−
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 13, 29 and 30
104
110
−
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 29 and 30
−
115
−
dBc/Hz
Φosc(hyb)
2004 Mar 22
phase noise, carrier to
sideband noise in hybrid
application
22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
RSCp-p
PARAMETER
ripple susceptibility of VCC
(peak-to-peak value)
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
VCC = 5 V ±5%; worst case in the
frequency range; ripple frequency
500 kHz; note 12
15
TYP.
140
MAX.
−
UNIT
mV
High band oscillator
fosc
oscillator frequency
note 9
482.15 −
902.15 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
note 10
−
300
−
kHz
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V; with
compensation; note 11
−
1100
−
kHz
Φosc(dig)
phase noise, carrier to
sideband noise in digital
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 8, 27 and 28
85
89
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 9, 27 and 28
87
93
−
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 11, 27 and 28
104
107
−
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 27 and 28
−
117
−
dBc/Hz
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 11, 29 and 30
80
85
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 12, 29 and 30
82
86
−
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 13, 29 and 30
104
107
−
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 29 and 30
−
117
−
dBc/Hz
ripple susceptibility of VCC
(peak-to-peak value)
VCC = 5 V ±5%; worst case in the
frequency range; ripple frequency
500 kHz; note 12
15
40
−
mV
output impedance
asymmetrical IF output
Φosc(hyb)
RSCp-p
phase noise, carrier to
sideband noise in hybrid
application
IF amplifier
Zo
RS at 38.9 MHz
−
50
−
Ω
LS at 38.9 MHz
−
5.4
−
nH
symmetrical IF output
2004 Mar 22
RS at 38.9 MHz
−
100
−
Ω
LS at 38.9 MHz
−
10.4
−
nH
23
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
SYMBOL
PARAMETER
CONDITIONS
TDA6650TT;
TDA6651TT
MIN.
TYP.
MAX.
UNIT
Rejection at the IF output (IF amplifier in asymmetrical mode)
INTdiv
divider interferences in
IF level
worst case; note 13
−
−
20
dBµV
INTxtal
crystal oscillator
interferences rejection
VIF = 100 dBµV; worst case in the
frequency range; note 14
−
−
−50
dBc
INTf(step)
step frequency rejection
measured in digital application for
DVB-T; fstep = 166.67 kHz;
IF = 36.125 MHz; note 15
−
−
−50
dBc
measured in hybrid application for
DVB-T; fstep = 166.67 kHz;
IF = 36.125 MHz; note 15
−
−
−57
dBc
measured in hybrid application for
PAL; fstep = 62.5 kHz;
IF = 38.9 MHz; note 15
−
−
−57
dBc
measured in hybrid application for
FM; fstep = 50 kHz; IF = 38.9 MHz;
note 15
−
−
−57
dBc
note 16
−
−
45
dBµV
122.5
124
125.5
dBµV
7.5
9.0
11.6
µA
INTXTH
crystal oscillator
harmonics in the
IF frequency
AGC output (IF amplifier in asymmetrical mode): pin AGC
AGCTOP(p-p)
AGC take-over point
(peak-to-peak level)
Isource(fast)
source current fast
Isource(slow)
source current slow
Vo
output voltage
bits AL[2:0] = 000
185
220
280
nA
maximum level
3.45
3.55
3.8
V
minimum level
0
−
0.1
V
bits AL[2:0] = 111
3.45
3.55
3.8
V
−
−
0.5
dB
Vo(dis)
output voltage with AGC
disabled
VRF(slip)
RF voltage range to switch
the AGC from active to not
active mode
VRML
low threshold AGC output
voltage
AGC bit = 0 or AGC not active
0
−
2.8
V
VRMH
high threshold AGC output
voltage
AGC bit = 1 or AGC active
3.2
3.55
3.8
V
ILO
leakage current
bits AL[2:0] = 110; 0 < VAGC < VCC
−50
−
+50
nA
2004 Mar 22
24
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Notes
1. Important recommendation: to obtain the performances mentioned in this specification, the serial resistance of the
crystal used with this oscillator must never exceed 120 Ω. The crystal oscillator is guaranteed to operate for any
supply voltage between 4.5 V and 5.5 V and at any temperature between −20 °C and +85 °C
2. The drive level is expected with a 50 Ω series resistance of the crystal at series resonance. The drive level will be
different with other series resistance values.
3. The VXTOUT level is measured when the pin XTOUT is loaded with 5 kΩ in parallel with 10 pF.
4. The RF frequency range is defined by the oscillator frequency range and the intermediate frequency (IF).
5. The 1% cross modulation performance is measured with AGC detector turned off (AGC bits set to 110).
6. Channel SO2 beat is the interfering product of fRFpix, fIF and fosc of channel SO2; fbeat = 37.35 MHz. The possible
mechanisms are: fosc − 2 × fIFpix or 2 × fRFpix − fosc.
7. The IF output signal stays stable within the range of the step frequency for any RF input level up to 120 dBµV.
8. (N + 5) − 1 MHz pulling is the input level of channel N + 5, at frequency 1 MHz lower, causing 100 kHz FM sidebands
30 dB below the wanted carrier.
9. Limits are related to the tank circuits used in Figs 27 and 28 for digital application or Figs 29 and 30 for hybrid
application. Frequency bands may be adjusted by the choice of external components.
10. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from
VCC = 5 to 4.5 V or from VCC = 5 to 5.25 V. The oscillator is free running during this measurement.
11. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from
Tamb = 25 to 50 °C or from Tamb = 25 to 0 °C. The oscillator is free running during this measurement.
12. The supply ripple susceptibility is measured in the measurement circuit according to Figs 27, 28, 29 and 30 using a
spectrum analyser connected to the IF output. An unmodulated RF signal is applied to the test board RF input. A
sinewave signal with a frequency of 500 kHz is superimposed onto the supply voltage. The amplitude of this ripple
signal is adjusted to bring the 500 kHz sidebands around the IF carrier to a level of −53.5 dB with respect to the
carrier.
13. This is the level of divider interferences close to the IF frequency. For example channel S3: fosc = 158.15 MHz,
1⁄ f
4 osc = 39.5375 MHz. The low and mid band inputs must be left open (i.e. not connected to any load or cable); the
high band inputs are connected to an hybrid.
14. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator.
15. The step frequency rejection is the level of step frequency sidebands (e.g. 166.67 kHz) related to the carrier.
16. This is the level of the 9th and 11th harmonics of the 4 MHz crystal oscillator into the IF output.
2004 Mar 22
25
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
1
handbook, full pagewidth
2
0.5
0.2
5
10
−j
∞
10
5
2
1
0.5
0.2
0
40 MHz
+j
200 MHz
10
5
0.2
2
0.5
MCE160
1
Fig.5 Input admittance (S11) of the low band mixer (40 to 200 MHz); Yo = 20 mS.
1
handbook, full pagewidth
2
0.5
0.2
5
10
−j
∞
10
5
2
1
0.5
0.2
0
100 MHz
+j
10
500 MHz
5
2
0.2
0.5
1
MCE161
Fig.6 Input admittance (S11) of the mid band mixer (100 to 500 MHz); Yo = 20 mS.
2004 Mar 22
26
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
1
handbook, full pagewidth
0.5
2
900 MHz
0.2
5
400 MHz
10
+j
0
0.2
0.5
1
2
5
∞
10
−j
10
5
0.2
2
0.5
1
MCE165
Fig.7 Input impedance (S11) of the high band mixer (400 to 900 MHz); Zo = 100 Ω.
FCE915
−80
handbook, full pagewidth
Φosc
(dBc/Hz)
−85
−90
−95
−100
40
140
240
340
440
540
640
740
840
940
fRF (MHz)
Fig.8 1 kHz phase noise typical performance in digital application (Figs 27 and 28).
2004 Mar 22
27
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FCE916
−80
handbook, full pagewidth
Φosc
(dBc/Hz)
−85
−90
−95
−100
−105
−110
40
140
240
340
440
540
640
740
840
940
fRF (MHz)
Fig.9 10 kHz phase noise typical performance in digital application (Figs 27 and 28).
FCE917
−100
handbook, full pagewidth
Φosc
(dBc/Hz)
−105
−110
−115
−120
40
140
240
340
440
540
640
740
840
940
fRF (MHz)
Fig.10 100 kHz phase noise typical performance in digital application (Figs 27 and 28).
2004 Mar 22
28
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FCE918
−80
handbook, full pagewidth
Φosc
(dBc/Hz)
−85
−90
−95
−100
−105
40
140
240
340
440
540
640
740
840
940
fRF (MHz)
Fig.11 1 kHz phase noise typical performance in hybrid application (Figs 29 and 30).
FCE919
−80
handbook, full pagewidth
Φosc
(dBc/Hz)
−85
−90
−95
−100
−105
40
140
240
340
440
540
640
740
840
940
fRF (MHz)
Fig.12 10 kHz phase noise typical performance in hybrid application (Figs 29 and 30).
2004 Mar 22
29
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FCE920
−100
handbook, full pagewidth
Φosc
(dBc/Hz)
−105
−110
−115
−120
40
140
240
340
440
540
640
740
840
940
fRF (MHz)
Fig.13 100 kHz phase noise typical performance in hybrid application (Figs 29 and 30).
handbook, full pagewidth
signal
50 Ω source
e
LBIN
or
MBIN
Vmeas V
50
Ω
27 Ω
IFOUTA
spectrum
analyzer
DUT
Vo
Vi
V'meas
50 Ω
IFOUTB
RMS
voltmeter
VCCA
FCE747
Zi >> 50 Ω → Vi = 2 × Vmeas = 70 dBµV.
Vi = Vmeas + 6 dB = 70 dBµV.
Vo = V’meas + 3.75 dB.
Vo
Gv = 20 log ------ .
Vi
DVB-T and PAL.
IF = 38.9 MHz.
Fig.14 Gain (GV) measurement in low and mid band with asymmetrical IF output.
2004 Mar 22
30
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
handbook, full pagewidth
signal
50 Ω source
e
LBIN
or
MBIN
Vmeas V
transformer
IFOUTA
DUT
50
Ω
TDA6650TT;
TDA6651TT
spectrum
analyzer
N1
C
Vi
Vo
50 Ω
N2
V'meas
IFOUTB
RMS
voltmeter
FCE748
Zi >> 50 Ω → Vi = 2 × Vmeas = 70 dBµV.
Vi = Vmeas + 6 dB = 70 dBµV.
Vo = V’meas + 15 dB (transformer ratio N2/N1 = 5 and transformer loss).
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Vo
Gv = 20 log ------ .
Vi
DVB-T and PAL.
IF = 38.9 MHz.
Fig.15 Gain (GV) measurement in low and mid band with symmetrical IF output.
handbook, full pagewidth
NOISE
SOURCE
BNC
RIM
LBIN
or
MBIN
INPUT
CIRCUIT
27 Ω
IFOUTA
NOISE
FIGURE
METER
DUT
IFOUTB
VCCA
FCE750
NF = NFmeas − loss of input circuit (dB).
Fig.16 Noise figure (NF) measurement in low and mid band with asymmetrical IF output.
2004 Mar 22
31
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
BNC
handbook, full pagewidth
connector Cs
Cc
Lp
TL
BNC
connector
to the IC
mixer input
Cc
Ls
Lp
Cp
TDA6650TT;
TDA6651TT
TL
to the IC
mixer input
Cp
MCE452
Schematic A.
Schematic B.
For fRF = 50 MHz (Schematic A)
Loss = 0 dB.
Cs = 12 pF in parallel with a 0.8 pF to 8 pF trimmer.
Cp = 18 pF in parallel with a 0.8 pF to 8 pF trimmer.
Cc = 4.7 nF.
Lp = 8 turns, ∅ 5 mm, wire ∅ = 0.4 mm air coil
TL = 50 Ω semi rigid cable, length = 75 mm.
For fRF = 300 MHz (Schematic B)
Loss = 0.5 dB.
Cp = 8.2 pF in parallel with a 0.8 pF to 8 pF trimmer.
Cc = 4.7 nF.
Ls = 2 turns, ∅ 1.5 mm, wire ∅ = 0.4 mm air coil.
Lp = 2 turns, ∅ 1.5 mm, wire ∅ = 0.4 mm air coil.
TL = 50 Ω semi rigid cable, length = 75 mm.
For fRF = 150 MHz (Schematic A)
Loss = 0 dB.
Cs = 0.8 pF to 8 pF trimmer.
Cp = 0.4 pF to 2.5 pF trimmer.
Cc = 4.7 nF.
Lp = 4 turns, ∅ 4.5 mm, wire ∅ = 0.4 mm air coil
TL = 50 Ω semi rigid cable, length = 75 mm.
Fig.17 Input circuit for optimum noise figure in low and mid band.
FILTER
50 Ω
AM = 30%
1 kHz
A
eu
unwanted
signal
source
LBIN
IFOUTA
or
MBIN
C
HYBRID
B
ew
wanted
signal
source
modulation
analyzer
Vo
DUT
50 Ω
27 Ω
10 dB
attenuator
38.9 MHz
V Vmeas
50 Ω
IFOUTB
D
50
Ω
VCCA
RMS
voltmeter
fce749
Vo = Vmeas + 3.75 dB.
Wanted signal source at fRFpix is 80 dBµV.
Unwanted output signal at fsnd.
The level of unwanted signal is measured by causing 1% AM modulation in
the wanted signal.
Fig.18 Cross modulation measurement in low and mid band with asymmetrical IF output.
2004 Mar 22
32
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FILTER
50 Ω
AM = 30%
1 kHz
A
unwanted
signal
source
eu
LBIN
or
MBIN
C
HYBRID
transformer
IFOUTA
DUT
modulation
analyzer
C
N2 V V'meas
N1
38.9 MHz
50 Ω
Vo
50 Ω
B
D
wanted
signal
source
ew
6 dB
attenuator
IFOUTB
50
Ω
RMS
voltmeter
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
Wanted signal source at fRFpix is 80 dBµV.
The level of unwanted signal Vo at fsnd is measured by causing 1%
AM modulation in the wanted output signal.
fce793
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Fig.19 Cross modulation measurement in low and mid band with symmetrical IF output.
handbook, full pagewidth
signal
50 Ω source
A
Vmeas V
e
50
Ω
Vi
IFOUTA
27 Ω
spectrum
analyzer
DUT
HYBRID
B
RMS
voltmeter
HBIN1
C
HBIN2
D
50
Ω
Vo
50 Ω
IFOUTB
VCCA
FCE751
Loss in hybrid = 1 dB.
Vi = Vmeas − loss = 70 dBµV.
Vo = V’meas + 3.75 dB.
Vo
Gv = 20 log ------ .
Vi
DVB-T and PAL.
IF = 38.9 MHz.
Fig.20 Gain (GVa) measurement in high band with asymmetrical IF output.
2004 Mar 22
33
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
handbook, full pagewidth
TDA6650TT;
TDA6651TT
signal
50 Ω source
A
Vmeas V
e
50
Ω
Vi
HBIN1
D
HBIN2
transformer
IFOUTA
DUT
HYBRID
B
RMS
voltmeter
C
spectrum
analyzer
N1
Vo
C
N2
V'meas
IFOUTB
50
Ω
FCE752
Loss in hybrid = 1 dB.
Vi = Vmeas − loss = 70 dBµV.
Vo = V’meas + 15 dB (transformer ratio N2/N1 = 5 and transformer
loss).
Vo
Gv = 20 log ------ .
Vi
DVB-T and PAL.
IF = 38.9 MHz.
Fig.21 Gain (GVs) measurement in high band with symmetrical IF output.
handbook, full pagewidth
NOISE
SOURCE
A
27 Ω
C
HBIN1
B
D
IFOUTA
NOISE
FIGURE
METER
DUT
HYBRID
HBIN2
50
Ω
IFOUTB
VCCA
FCE753
Loss in hybrid = 1 dB.
NF = NFmeas − loss.
Fig.22 Noise figure (NF) measurement in high band with asymmetrical IF output.
2004 Mar 22
50 Ω
34
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FILTER
50 Ω
AM = 30%
1 kHz
A
unwanted
signal
source
eu
A
C
C
27 Ω
HBIN1
HYBRID
HYBRID
10 dB
attenuator
IFOUTA
DUT
modulation
analyzer
Vo
38.9 MHz
V Vmeas
50 Ω
50 Ω
B
ew
B
D
wanted
signal
source
D
HBIN2
IFOUTB
50
Ω
50
Ω
VCCA
RMS
voltmeter
fce754
Wanted signal source at fRFpix is 70 dBµV.
Unwanted output signal at fsnd.
The level of unwanted signal is measured by causing 1% AM modulation
in the wanted signal.
Fig.23 Cross modulation measurement in high band with asymmetrical IF output.
AM = 30%
1 kHz
50 Ω
eu
unwanted
signal
source
transformer
A
A
C
C
HYBRID
HYBRID
6 dB
attenuator
FILTER
HBIN1 IFOUTA
DUT
modulation
analyzer
C
N1
N2
V V'meas
38.9 MHz
Vo
50 Ω
ew
B
wanted
signal
source
D
B
50
Ω
D
HBIN2 IFOUTB
50
Ω
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
RMS
voltmeter
N1 = 10 turns.
N2 = 2 turns.
N1 / N2 = 5.
Fig.24 Cross modulation measurement in high band with symmetrical IF output.
2004 Mar 22
50 Ω
35
fce794
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
signal
50 Ω source
handbook, full pagewidth
e
LBIN
or
MBIN
Vmeas V
27 Ω
IFOUTA
spectrum
analyzer
DUT
50
Ω
TDA6650TT;
TDA6651TT
50 Ω
IFOUTB
RMS
voltmeter
VCCA
FCE755
Zi >> 50 Ω → Vi = 2 × Vmeas.
Vi = Vmeas + 6 dB.
Fig.25 Maximum RF input level without lock-out in low and mid band with asymmetrical IF output.
handbook, full pagewidth
signal
50 Ω source
27 Ω
A
e
Vmeas V
50
Ω
Vi
IFOUTA
spectrum
analyzer
DUT
HYBRID
B
RMS
voltmeter
HBIN1
C
HBIN2
D
50
Ω
50 Ω
IFOUTB
VCCA
FCE756
Loss in hybrid = 1 dB.
Vi = Vmeas − loss.
Fig.26 Maximum RF input level without lock-out in high band with asymmetrical IF output.
2004 Mar 22
36
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
The TDA6650TT, TDA6651TT PLL loop stability is
guaranteed in the configuration of Figs. 27, 28, 29 and 30.
In this configuration, the external supply source is 30 V
minimum, the pull-up resistor R19, is 15 kΩ and all of the
local oscillators are aligned to operate at a maximum
tuning voltage of 26 V. If the configuration is changed,
there might be an impact on the loop stability.
V DC – V T
I delivered =  ------------------------ > I CP
 R pu 
Where
Idelivered is the delivered current
VDC is the supply source voltage or DC-to-DC converter
output voltage
For any other configurations, a stability analysis must be
performed. The conventional PLL AC model (cf. SIMPATA
Philips software) used for the stability analysis, is valid
provided the external source (DC supply source or
DC-to-DC converter) is able to deliver a minimum current
that is equal to the charge pump current in use.
VT is the tuning voltage
Rpu is the pull-up resistor between the DC supply source
(or the DC-to-DC converter output) and the tuning line
(R19 in Figs. 27 to 30)
ICP is the charge pump current in use.
The delivered current can be simply calculated with the
following formula:
2004 Mar 22
TDA6650TT;
TDA6651TT
37
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J2
HIGH2
C7
1.8 pF
N750
C6
6
4
2
L4
T0K0;
500 nF
C3
4.7
nF
C1
4.7
nF
2
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
C26
12 pF
12 pF
AGC
C28
150 nF
R20
R21
1 kΩ
D6
R22
1 kΩ
D7
1 kΩ
D8
R10
330
Ω
R9
330
Ω
R23
R11
330
Ω
1 (38)
(1) 38
2 (37)
(2) 37
3 (36)
(3) 36
4 (35)
(4) 35
5 (34)
(5) 34
6 (33)
(6) 33
7 (32)
(7) 32
TDA6650TT
8 (31)
(8) 31
(TDA6651TT)
9 (30)
(9) 30
10 (29)
(10) 29
11 (28)
(11) 28
12 (27)
(12) 27
13 (26)
(13) 26
14 (25)
(14) 25
15 (24)
(15) 24
16 (23)
(16) 23
17 (22)
(17) 22
(18) 21
18 (21)
19 (20)
(19) 20
C19
Y1
18 pF
4 MHz
ST2
ADC
R27
3.3
kΩ
VCC
R14
PLLGND
VCCD
CP
VT
n.c.
XTAL2
D1
C5
BB182
47 pF
N750
SCL
R28
3.3
kΩ
SDA
L1
25 nH
R2
C11 1 pF
R3
120 pF
N750
5.6 kΩ
5.6 kΩ
120 pF
N750
N750
C13 1 pF
D3
BB179
L2
13 nH
R01255
C18
N750
VCC
C14 1 pF
N750
R5
5.6 kΩ
R6
27 Ω
C17
15 pF
N470
R8
2.7 nF
5.6 kΩ
VCC
C23
4.7 nF
C21
100 nF
R7
1 kΩ
C20
330 pF
30 V
AS
C29
4.7 nF
1 kΩ
C32
10
µF
C30
10
µF
1 2 3 4
J5
R19
15 kΩ
R26
27 Ω
J6
J7
test
30 V
Fig.27 Measurement circuit for digital application, with asymmetrical IF output and DVB-T compliant loop filter.
IF out
MCE162
Product specification
C31
10
µF
TDA6650TT;
TDA6651TT
J8
1 2 3 4 5 6
5 V bus
D2
BB178
R4
N750
C12 1 pF
R13
6.8 kΩ
VCC
C34
C33
C16
4.7 nF
C15
4.7 nF
5 V bus
1 kΩ
ST1
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
VCC
5 V bus
R24
handbook, full pagewidth
38
1 kΩ
D5
1.5 pF
N750
R1
12 Ω
1 kΩ
3
C27
D4
C2
4.7
nF
* 6t
1
TP1
C4
4.7
nF
L3
140 nH
R08304
Philips Semiconductors
J1
HIGH1
J3
MID
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
2004 Mar 22
The pin numbers in parenthesis
represent the TDA6651TT.
J4
LOW
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J1
HIGH1
J2
HIGH2
C7
1.8 pF
N750
C6
6
4
2
L4
T0K0;
500 nF
C3
4.7
nF
C1
4.7
nF
2
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
3
C27
C26
12 pF
12 pF
C28
150 nF
R20
39
1 kΩ
D5
R21
1 kΩ
D6
1.5 pF
N750
R22
1 kΩ
D7
R10
330
Ω
R9
330
Ω
R23
1 kΩ
D8
R11
330
Ω
1 (38)
(1) 38
2 (37)
(2) 37
3 (36)
(3) 36
4 (35)
(4) 35
5 (34)
(5) 34
6 (33)
(6) 33
7 (32)
(7) 32
TDA6650TT
8 (31)
(8) 31
(TDA6651TT)
9 (30)
(9) 30
10 (29)
(10) 29
(11) 28
11 (28)
(12) 27
12 (27)
(13) 26
13 (26)
(14) 25
14 (25)
(15) 24
15 (24)
(16) 23
16 (23)
(17) 22
17 (22)
(18) 21
18 (21)
(19) 20
19 (20)
C19
Y1
18 pF
4 MHz
ST2
ADC
12 Ω
D1
C5
BB182
47 pF
N750
R2
R27
3.3
kΩ
VCC
R14
L1
25 nH
R3
120 pF
N750
5.6 kΩ
D2
BB178
R4
C33
C11 1 pF
5.6 kΩ
120 pF
N750
N750
C12 1 pF
N750
C13 1 pF
PLLGND
VCCD
D3
BB179
L2
13 nH
R01255
C14 1 pF
27 Ω
C21
100 nF
R13
6.8 kΩ
5.6 kΩ
15 pF
N470
R8
R6
N750
C16
4.7 nF
R5
C18
N750
VCC
CP
VT
n.c.
XTAL2
C15
4.7 nF
C34
C17
2.7 nF
5.6 kΩ
C24
4.7 nF
C23
4.7 nF
R7
1 kΩ
C25
C20
330 pF
12 pF
5 V bus
1 kΩ
ST1
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
VCC
5 V bus
R24
R1
1 kΩ
AGC
D4
C2
4.7
nF
* 6t
1
TP1
C4
4.7
nF
L3
140 nH
R08304
Philips Semiconductors
J3
MID
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
2004 Mar 22
J4
LOW
SCL
R28
3.3
kΩ
SDA
1
VCC
2
3
30 V
AS
C29
4.7 nF
1 kΩ
C32
10
µF
C30
10
µF
1 2 3 4
J5
6
R19
15 kΩ
J7
4
R26
0Ω
J6
test
30 V
IF out
5 V bus
The pin numbers in parenthesis represent
the TDA6651TT.
Fig.28 Measurement circuit for digital application, with symmetrical IF output and DVB-T compliant loop filter.
fce875
Product specification
C31
10
µF
TDA6650TT;
TDA6651TT
J8
1 2 3 4 5 6
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J3
MID
J1
HIGH1
J2
HIGH2
C7
1.8 pF
N750
C6
6
4
2
L4
T0K0;
500 nF
C3
4.7
nF
C1
4.7
nF
1
2
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
3
12 pF
AGC
C28
150 nF
40
R20
1 kΩ
D5
R21
1 kΩ
D6
1.5 pF
N750
R22
1 (38)
(1) 38
2 (37)
(2) 37
3 (36)
(3) 36
4 (35)
(4) 35
5 (34)
(5) 34
6 (33)
(6) 33
7 (32)
(7) 32
TDA6650TT (8) 31
8 (31)
(TDA6651TT)
9 (30)
(9) 30
10 (29)
(10) 29
(11) 28
11 (28)
(12) 27
12 (27)
(13) 26
13 (26)
(14) 25
14 (25)
(15) 24
15 (24)
(16) 23
16 (23)
(17) 22
17 (22)
(18) 21
18 (21)
(19) 20
19 (20)
1 kΩ
D7
R10
330
Ω
R9
330
Ω
R23
1 kΩ
D8
R11
330
Ω
C19
Y1
18 pF
4 MHz
ST2
ADC
D1
C5
BB182
47 pF
N750
R27
3.3
kΩ
VCC
R14
L1
25 nH
R2
C11 1 pF
SCL
R28
3.3
kΩ
SDA
R3
120 pF
N750
5.6 kΩ
D2
BB178
R4
5.6 kΩ
120 pF
N750
N750
C12 1 pF
N750
C13 1 pF
PLLGND
VCCD
D3
BB179
L2
13 nH
R01255
C14 1 pF
N750
R5
5.6 kΩ
C18
N750
VCC
CP
VT
n.c.
XTAL2
C15
4.7 nF
C34
C33
R6
27 Ω
C17
15 pF
N470
R8
4.7 nF
5.6 kΩ
VCC
R13
1.8 kΩ
VCC
C23
4.7 nF
C21
100 nF
C16
4.7 nF
5 V bus
1 kΩ
ST1
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
VCC
5 V bus
R24
R1
12 Ω
1 kΩ
C26
12 pF
D4
C2
4.7
nF
* 6t
C27
R7
1 kΩ
C20
2.7 nF
30 V
AS
C29
4.7 nF
1 kΩ
C32
10
µF
C30
10
µF
1 2 3 4
J5
R19
15 kΩ
R26
27 Ω
J6
J7
5 V bus
test
30 V
IF out
FCE909
Fig.29 Measurement circuit for hybrid application, with asymmetrical IF output and loop filter for PAL and DVB-T standards.
Product specification
C31
10
µF
TDA6650TT;
TDA6651TT
J8
1 2 3 4 5 6
handbook, full pagewidth
TP1
C4
4.7
nF
L3
140 nH
R08304
Philips Semiconductors
J4
LOW
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
2004 Mar 22
The pin numbers in parenthesis
represent the TDA6651TT.
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J1
HIGH1
J2
HIGH2
C7
1.8 pF
N750
C6
6
4
2
L4
T0K0;
500 nF
C3
4.7
nF
C1
4.7
nF
2
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
3
C27
C26
12 pF
12 pF
C28
150 nF
R20
41
1 kΩ
D5
R21
1 kΩ
D6
1.5 pF
N750
R22
1 kΩ
D7
R10
330
Ω
R9
330
Ω
R23
1 kΩ
D8
R11
330
Ω
1 (38)
(1) 38
2 (37)
(2) 37
3 (36)
(3) 36
4 (35)
(4) 35
5 (34)
(5) 34
6 (33)
(6) 33
7 (32)
(7) 32
TDA6650TT
8 (31)
(8) 31
(TDA6651TT)
9 (30)
(9) 30
10 (29)
(10) 29
(11) 28
11 (28)
(12) 27
12 (27)
(13) 26
13 (26)
(14) 25
14 (25)
(15) 24
15 (24)
(16) 23
16 (23)
(17) 22
17 (22)
(18) 21
18 (21)
(19) 20
19 (20)
C19
Y1
18 pF
4 MHz
ST2
ADC
12 Ω
D1
C5
BB182
47 pF
N750
R2
R27
3.3
kΩ
VCC
R14
L1
25 nH
R3
120 pF
N750
5.6 kΩ
D2
BB178
R4
C33
C11 1 pF
5.6 kΩ
120 pF
N750
N750
C12 1 pF
N750
C13 1 pF
PLLGND
VCCD
D3
BB179
L2
13 nH
R01255
C14 1 pF
27 Ω
C21
100 nF
R13
6.8 kΩ
5.6 kΩ
15 pF
N470
R8
R6
N750
C16
4.7 nF
R5
C18
N750
VCC
CP
VT
n.c.
XTAL2
C15
4.7 nF
C34
C17
2.7 nF
5.6 kΩ
C24
4.7 nF
C23
4.7 nF
R7
1 kΩ
C25
C20
2.7 nF
12 pF
5 V bus
1 kΩ
ST1
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
VCC
5 V bus
R24
R1
1 kΩ
AGC
D4
C2
4.7
nF
* 6t
1
TP1
C4
4.7
nF
L3
140 nH
R08304
Philips Semiconductors
J3
MID
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
2004 Mar 22
J4
LOW
SCL
R28
3.3
kΩ
SDA
1
VCC
3
30 V
AS
C29
4.7 nF
1 kΩ
C32
10
µF
C30
10
µF
1 2 3 4
J5
6
R19
15 kΩ
J7
4
R26
0Ω
J6
test
30 V
IF out
fce910
The pin numbers in parenthesis represent
the TDA6651TT.
Fig.30 Measurement circuit for hybrid application, with symmetrical IF output and loop filter for PAL and DVB-T standards.
Product specification
C31
10
µF
TDA6650TT;
TDA6651TT
J8
1 2 3 4 5 6
5 V bus
2
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
13 INTERNAL PIN CONFIGURATION
AVERAGE DC VOLTAGE VERSUS
BAND SELECTION
PIN
SYMBOL
TDA6650TT TDA6651TT
LOW
MID
DESCRIPTION(1)
HIGH
HBIN1
1
38
n.a.
n.a
1.0 V
HBIN2
2
37
n.a.
n.a
1.0 V
(38) 1
2 (37)
FCE899
MBIN
3
36
n.a.
1.8 V
n.a.
(36) 3
FCE901
LBIN
4
35
1.8 V
n.a.
n.a
(35) 4
FCE898
RFGND
5
34
−
−
−
5 (34)
FCE897
IFFIL1
6
33
3.7 V
3.7 V
3.7 V
IFFIL2
7
32
3.7 V
3.7 V
3.7 V
(33) 6
7 (32)
FCE896
2004 Mar 22
42
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
AVERAGE DC VOLTAGE VERSUS
BAND SELECTION
PIN
SYMBOL
TDA6650TT TDA6651TT
BS4
8
31
LOW
MID
HIGH
high Z or
VCC − VDS
high Z or
VCC − VDS
high Z or
VCC − VDS
TDA6650TT;
TDA6651TT
DESCRIPTION(1)
8 (31)
FCE895
AGC
9
30
0 V or
3.5 V
0 V or
3.5 V
0 V or
3.5 V
9 (30)
FCE907
BS3
10
29
high Z or
VCC − VDS
high Z or
VCC − VDS
high Z or
VCC − VDS
10 (29)
FCE893
BS2
11
28
high Z
VCC − VDS
high Z
11 (28)
FCE892
BS1
12
27
VCC − VDS
high Z
high Z
12 (27)
FCE891
2004 Mar 22
43
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
AVERAGE DC VOLTAGE VERSUS
BAND SELECTION
PIN
SYMBOL
TDA6650TT TDA6651TT
BVS
13
26
LOW
2.5 V
MID
2.5 V
TDA6650TT;
TDA6651TT
DESCRIPTION(1)
HIGH
2.5 V
(26) 13
MCE163
ADC/BS5
14
25
VCEsat or
high Z
VCEsat or
high Z
VCEsat or
high Z
(25) 14
FCE887
SCL
15
24
high Z
high Z
high Z
(24) 15
FCE889
SDA
16
23
high Z
high Z
high Z
(23) 16
FCE888
AS
17
22
1.25 V
1.25 V
1.25 V
(22) 17
FCE890
2004 Mar 22
44
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
AVERAGE DC VOLTAGE VERSUS
BAND SELECTION
PIN
SYMBOL
TDA6650TT TDA6651TT
XTOUT
18
21
LOW
3.45 V
MID
3.45 V
TDA6650TT;
TDA6651TT
DESCRIPTION(1)
HIGH
3.45 V
18 (21)
MCE164
XTAL1
19
20
2.2 V
2.2 V
2.2 V
XTAL2
20
19
2.2 V
2.2 V
2.2 V
19 (20)
20 (19)
FCE883
n.c.
21
18
n.a.
VT
22
17
VVT
not connected
VVT
VVT
22 (17)
FCE884
CP
23
16
1.8 V
1.8 V
1.8 V
23 (16)
FCE885
VCCD
2004 Mar 22
24
15
5V
5V
45
5V
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
AVERAGE DC VOLTAGE VERSUS
BAND SELECTION
PIN
SYMBOL
TDA6650TT TDA6651TT
PLLGND
25
TDA6650TT;
TDA6651TT
14
LOW
−
MID
−
DESCRIPTION(1)
HIGH
−
25 (14)
FCE882
VCCA
26
13
5V
5V
5V
IFOUTB
27
12
2.1 V
2.1 V
2.1 V
IFOUTA
28
11
2.1 V
2.1 V
2.1 V
28 (11)
FCE886
IFGND
29
10
−
−
−
29 (10)
FCE880
HOSCIN1
30
9
2.2 V
2.2 V
1.8 V
HOSCOUT1
31
8
5V
5V
2.5 V
HOSCOUT2
32
7
5V
5V
2.5 V
HOSCIN2
33
6
2.2 V
2.2 V
1.8 V
(8) 31
32 (7)
(6) 33
30 (9)
FCE879
MOSCIN1
34
5
2.3 V
1.3 V
2.3 V
MOSCIN2
35
4
2.3 V
1.3 V
2.3 V
34 (5)
35 (4)
FCE878
2004 Mar 22
46
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
AVERAGE DC VOLTAGE VERSUS
BAND SELECTION
PIN
SYMBOL
TDA6650TT TDA6651TT
OSCGND
36
TDA6650TT;
TDA6651TT
3
LOW
−
MID
−
DESCRIPTION(1)
HIGH
−
36 (3)
FCE908
LOSCOUT
37
2
1.7 V
1.4 V
1.4 V
LOSCIN
38
1
2.9 V
3.5 V
3.5 V
37 (2)
(1) 38
FCE877
Note
1. The pin numbers in parenthesis refer to the TDA6651TT.
2004 Mar 22
47
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
14 APPLICATION AND TEST INFORMATION
14.1
Do not use the signal on pins XTAL1 or XTAL2, or the
signal present on the crystal, to drive an external IC or for
any other use as this may dramatically degrade the phase
noise performance of the TDA6650TT; TDA6651TT.
Tuning amplifier
The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 15 kΩ
which is connected to the tuning voltage supply rail. The
loop filter design depends on the oscillator characteristics
and the selected reference frequency as well as the
required PLL loop bandwidth.
14.3
Examples of I2C-bus program sequences
Tables 16 to 23 show various sequences where:
S = START
A = acknowledge
Applications with the TDA6650TT; TDA6651TT have a
large loop bandwidth, in the order of a few tens of kHz. The
calculation of the loop filter elements has to be done for
each application, it depends on the reference frequency
and charge pump current. A simulation of the loop can
easily be done using the SIMPATA software from Philips.
14.2
TDA6650TT;
TDA6651TT
P = STOP.
The following conditions apply:
LO frequency is 800 MHz
fcomp = 166.666 kHz
N = 4800
BS3 output port is on and all other ports are off: thus the
high band is selected
Crystal oscillator
The TDA6650TT; TDA6651TT needs to be used with a
4 MHz crystal in series with a capacitor with a typical value
of 18 pF, connected between pin XTAL1 and pin XTAL2.
Philips crystal 4322 143 04093 is recommended. When
choosing a crystal, take care to select a crystal able to
withstand the drive level of the TDA6650TT; TDA6651TT
without suffering from accelerated ageing. For optimum
performances, it is highly recommended to connect the
4 MHz crystal without any serial resistance.
Charge pump current ICP = 280 µA
Normal mode, with XTOUT buffer on
IAGC = 220 nA
AGC take-over point is set to 112 dBµV (p-p)
Address selection is adjusted to make address C2 valid.
To fully program the device, either sequence of Table 16
or 17 can be used, while other arrangements of the bytes
are also possible.
The crystal oscillator of the TDA6650TT; TDA6651TT
should not be driven (forced) from an external signal.
Table 16 Complete sequence 1
START
S
ADDRESS
BYTE
C2
A
DIVIDER
BYTE 1
12
A
DIVIDER
BYTE 2
C0
A
CONTROL
BYTE 1(1)
CONTROL
BYTE 2
CONTROL
BYTE 1(2)
CA
A4
84
A
A
STOP
A
P
Notes
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 17 Complete sequence 2
START
S
ADDRESS
BYTE
CONTROL
BYTE 1(1)
CONTROL
BYTE 2
C2
CA
A4
A
A
DIVIDER
BYTE 1
A
12
A
DIVIDER
BYTE 2
C0
A
CONTROL
BYTE 1(2)
84
STOP
A
P
Notes
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
2004 Mar 22
48
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Table 18 Sequence to program only the main divider ratio
START
S
ADDRESS BYTE
DIVIDER BYTE 1
DIVIDER BYTE 2
C2
12
C0
A
A
STOP
A
P
Table 19 Sequence to change the charge pump current, the ports and the test mode. If the reference divider ratio is
changed, it is necessary to send the DB1 and DB2 bytes
START
CONTROL BYTE 1(1)
ADDRESS BYTE
S
C2
A
CA
CONTROL BYTE 2
A
A4
STOP
A
P
Note
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
Table 20 Sequence to change the test mode. If the reference divider ratio is changed, it is necessary to send the DB1
and DB2 bytes
START
CONTROL BYTE 1(1)
ADDRESS BYTE
S
C2
A
CA
STOP
A
P
Note
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
Table 21 Sequence to change the charge pump current, the ports and the AGC data
START
CONTROL BYTE 1(1)
ADDRESS BYTE
S
C2
A
82
CONTROL BYTE 2
A
A4
STOP
A
P
Note
1. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 22 Sequence to change only the AGC data
START
CONTROL BYTE 1(1)
ADDRESS BYTE
S
C2
A
84
STOP
A
P
Note
1. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 23 Sequence to program the main divider, the ALBC on and the test modes in normal mode with XTOUT buffer
off.
STAR
T
S
ADDRESS
BYTE
C2
A
DIVIDER
BYTE 1
12
A
DIVIDER
BYTE 2
C0
A
CONTROL
BYTE 1(1)
CONTROL
BYTE 2
CONTROL
BYTE 1
DA
00
C2
A
A
A
STOP
P
Note
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2004 Mar 22
49
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
15 PACKAGE OUTLINE
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
SOT510-1
E
D
A
X
c
HE
y
v M A
Z
20
38
A2
(A 3)
A
A1
pin 1 index
θ
Lp
L
1
19
bp
e
detail X
w M
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.85
0.25
0.27
0.17
0.20
0.09
9.8
9.6
4.5
4.3
0.5
6.4
1
0.7
0.5
0.2
0.08
0.08
0.49
0.21
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
98-09-16
03-02-18
SOT510-1
2004 Mar 22
EUROPEAN
PROJECTION
50
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
To overcome these problems the double-wave soldering
method was specifically developed.
16 SOLDERING
16.1
Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
16.2
TDA6650TT;
TDA6651TT
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all BGA, HTSSON-T and SSOP-T packages
16.4
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
16.3
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Mar 22
Manual soldering
51
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
16.5
TDA6650TT;
TDA6651TT
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
not
recommended(5)(6)
suitable
SSOP, TSSOP, VSO, VSSOP
not
recommended(7)
suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not suitable
LQFP, QFP, TQFP
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Mar 22
52
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
17 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18 DEFINITIONS
19 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 22
53
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2004 Mar 22
54
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA76
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R25/03/pp55
Date of release: 2004
Mar 22
Document order number:
9397 750 13025