PD- 91316F
IRLR/U3303
HEXFET® Power MOSFET
l
l
l
l
l
l
l
Logic-Level Gate Drive
Ultra Low On-Resistance
Surface Mount (IRLR3303)
Straight Lead (IRLU3303)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
D
VDSS = 30V
RDS(on) = 0.031Ω
G
ID = 35A
S
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.
D -P ak
T O -252 A A
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
I-P ak
T O -25 1A A
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, V GS @ 10V
Continuous Drain Current, V GS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
35
25
140
68
0.45
± 16
130
20
6.8
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Case-to-Ambient (PCB mount)**
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
2.2
50
110
°C/W
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
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1
9/28/98
IRLR/U3303
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
IGSS
Min. Typ. Max. Units
Conditions
30
––– –––
V
V GS = 0V, ID = 250µA
––– 0.035 ––– V/°C Reference to 25°C, ID = 1mA
–––
––– 0.031
VGS = 10V, ID = 21A
Ω
–––
––– 0.045
VGS = 4.5V, ID = 17A
1.0
––– –––
V
VDS = VGS, ID = 250µA
12
––– –––
S
VDS = 25V, ID = 20A
–––
––– 25
VDS = 30V, VGS = 0V
µA
–––
––– 250
VDS = 24V, VGS = 0V, TJ = 150°C
–––
––– 100
VGS = 16V
nA
–––
––– -100
VGS = -16V
–––
––– 26
ID = 20A
–––
––– 8.8
nC
VDS = 24V
–––
––– 15
VGS = 4.5V, See Fig. 6 and 13
–––
7.4 –––
VDD = 15V
–––
200 –––
ID = 20A
ns
–––
14 –––
RG = 6.5Ω, VGS = 4.5V
–––
36 –––
RD = 0.70Ω, See Fig. 10
Between lead,
–––
4.5
–––
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
–––
870 –––
VGS = 0V
–––
340 –––
pF
V DS = 25V
–––
170 –––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 35
showing the
A
G
integral reverse
––– ––– 140
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 20A, V GS = 0V
––– 72
110
ns
TJ = 25°C, IF = 20A
––– 180 280
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 15V, starting TJ = 25°C, L =470µH
RG = 25Ω, I AS = 20A. (See Figure 12)
ISD ≤ 20A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
2
Caculated continuous current based on maximum allowable
junction temperature;
Package limitation current = 20A.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
Uses IRL3303 data and test conditions.
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IRLR/U3303
1000
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOT TOM 2.5V
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
100
TOP
ID , D rain-to-S ourc e C urrent (A )
ID , D ra in -to -S o u rc e C u rren t (A )
TO P
10
1
2.5V
2 0µ s P U LS E W ID TH
T J = 25 °C
0.1
0.1
1
10
100
10
2 .5V
1
2 0µ s P U LS E W ID TH
T J = 1 75 °C
0.1
A
100
0.1
1
V D S , D rain-to-S ource V oltage (V )
Fig 2. Typical Output Characteristics
2.0
R D S (on) , Drain-to-S ource O n Resistance
(N orm alized)
I D , D rain-to-So urce C urren t (A )
1000
100
TJ = 2 5 °C
TJ = 1 75 °C
10
1
V DS = 1 5V
2 0µ s P U L S E W ID TH
2
3
4
5
6
7
8
9
V G S , G ate -to -So urce Volta ge (V )
Fig 3. Typical Transfer Characteristics
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A
100
V D S , D rain-to-S ource V oltage (V )
Fig 1. Typical Output Characteristics
0.1
10
10
A
I D = 3 4A
1.5
1.0
0.5
V G S = 10 V
0.0
-60
-40
-20
0
20
40
60
80
A
100 120 140 160 180
T J , Junction T em perature (°C )
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRLR/U3303
V GS
C is s
C rs s
C iss C o ss
C , C apacitance (pF)
1400
=
=
=
=
15
0V ,
f = 1M H z
C g s + C g d , Cd s S H O R T E D
C gd
C d s + C gd
V G S , G a te-to-S ou rc e V o ltag e (V )
1600
V D S = 24 V
V D S = 15 V
12
1200
1000
I D = 2 0A
C oss
800
600
C rss
400
9
6
3
200
0
1
10
100
FO R TE S T CIR C U IT
S E E FIG U R E 1 3
0
A
0
V D S , D rain-to-S ource V oltage (V )
20
30
A
40
Q G , T otal G ate C harge (nC )
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
O P E R A TIO N IN TH IS A R E A L IM ITE D
B Y R D S (o n)
I D , Drain C urrent (A )
I S D , R everse Drain C urrent (A )
10
100
T J = 17 5°C
T J = 25 °C
10
V G S = 0V
1
0.0
0.5
1.0
1.5
2.0
V S D , S ourc e-to-D rain V oltage (V )
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
A
2.5
10µ s
100
100 µs
10
1m s
10m s
T C = 25 °C
T J = 17 5°C
S ing le P u lse
1
1
A
10
100
V D S , D rain-to-S ource V oltage (V )
Fig 8. Maximum Safe Operating
Area
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IRLR/U3303
35
RD
VDS
LIMITED BY PACKAGE
VGS
30
D.U.T.
I D , Drain Current (A)
RG
+
-VDD
25
4.5V
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
Fig 10a. Switching Time Test Circuit
10
VDS
5
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.1
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U3303
1 5V
L
VDS
D .U .T
RG
IA S
20V
D R IV E R
+
V
- DD
0 .0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
A
E A S , S ingle P ulse A valanche E nergy (m J)
300
TO P
250
B O TTO M
ID
8.3 A
14 A
2 0A
200
150
100
50
0
V D D = 15 V
25
50
A
75
100
125
150
175
S tarting T J , J unc tion T em perature (°C )
V (B R )D SS
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
D.U.T.
QGD
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRLR/U3303
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
D=
Period
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLR/U3303
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2 .3 8 (.0 9 4 )
2 .1 9 (.0 8 6 )
6 .7 3 (.2 6 5 )
6 .3 5 (.2 5 0 )
-A 1 .2 7 (.0 5 0 )
0 .8 8 (.0 3 5 )
5 .4 6 (.2 1 5 )
5 .2 1 (.2 0 5 )
1 .1 4 (.0 4 5 )
0 .8 9 (.0 3 5 )
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
4
6 .4 5 (.2 4 5 )
5 .6 8 (.2 2 4 )
6 .2 2 (.2 4 5 )
5 .9 7 (.2 3 5 )
1.0 2 (.0 4 0 )
1.6 4 (.0 2 5 )
1 0 .4 2 (.4 1 0 )
9 .4 0 (.3 7 0 )
1
2
1 - GATE
1 .5 2 (.0 6 0 )
1 .1 5 (.0 4 5 )
3X
1 .1 4 (.0 4 5 )
0 .7 6 (.0 3 0 )
0 .8 9 (.0 3 5 )
0 .6 4 (.0 2 5 )
0 .2 5 ( .0 1 0 )
2 - D R A IN
0 .5 1 (.0 2 0 )
M IN .
-B -
2X
L E A D A S S IG N M E N T S
3
3 - S OU R CE
4 - D R A IN
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
M A M B
N O TE S :
2 .2 8 ( .0 9 0 )
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 .
4 .5 7 ( .1 8 0 )
2 C O N T R O L L IN G D IM E N S IO N : IN C H .
3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A .
4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP ,
S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) .
Part Marking Information
TO-252AA (D-PARK)
EXAM PLE : TH IS IS AN IR FR 120
W ITH ASSEM BLY
LO T C OD E 9U 1P
IN TER N ATIO N AL
RE CTIFIE R
LO G O
ASSEM BLY
L O T C OD E
8
A
IR FR
120
9U 1P
FIR ST PO R TIO N
OF PAR T N U MBER
SEC O ND PO R TIO N
O F PAR T NU M BER
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IRLR/U3303
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.26 5 )
6 .3 5 (.25 0 )
2 .3 8 (.0 9 4 )
2 .1 9 (.0 8 6 )
-A -
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
1 .2 7 ( .0 5 0 )
0 .8 8 ( .0 3 5 )
5 .4 6 (.2 1 5 )
5 .2 1 (.2 0 5 )
L E A D A S S IG N M E N T S
4
1 - GATE
2 - D R A IN
6 .4 5 (.2 4 5 )
5 .6 8 (.2 2 4 )
1
2
3
-B 2.2 8 (.0 9 0)
1.9 1 (.0 7 5)
3X
3 - SOURCE
4 - D R A IN
6 .2 2 ( .2 4 5 )
5 .9 7 ( .2 3 5 )
1 .5 2 (.0 6 0 )
1 .1 5 (.0 4 5 )
1 .1 4 (.0 45 )
0 .7 6 (.0 30 )
2 .28 (.0 9 0 )
3X
9 .6 5 ( .3 8 0 )
8 .8 9 ( .3 5 0 )
N O TE S :
1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 .
2 C O N T R O L L IN G D IM E N S IO N : IN C H .
3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A .
4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP ,
S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ).
0 .8 9 (.0 35 )
0 .6 4 (.0 25 )
1 .1 4 ( .0 4 5 )
0 .8 9 ( .0 3 5 )
0 .2 5 (.0 1 0 )
M A M B
2X
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
Part Marking Information
TO-251AA (I-PARK)
EXAM PLE : TH IS IS AN IR FU 12 0
W ITH ASSEM BLY
LO T C O D E 9U 1 P
IN TE RN ATION AL
R EC TIFIER
LO GO
AS SEMBL Y
LO T C O D E
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IR FU
12 0
9 U 1P
FIR ST PO RTION
O F PAR T N U M BER
SEC O N D PO R TIO N
O F PAR T N U MB ER
9
IRLR/U3303
Tape & Reel Information
TO-252AA
Dimensions are shown in millimeters (inches)
TR
TRR
1 6.3 ( .641 )
1 5.7 ( .619 )
12 .1 ( .4 76 )
11 .9 ( .4 69 )
F E E D D IR E C T IO N
TRL
16 .3 ( .641 )
15 .7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
F E E D D IR E C T IO N
NO T ES :
1. C O N T R O LL IN G D IM E N S IO N : M ILLIM E T E R .
2. A LL D IM E N S IO N S A R E S H O W N IN M ILL IM E T E R S ( IN C H E S ).
3. O U T L IN E C O N F O R M S T O E IA -4 81 & E IA -54 1.
13 IN C H
16 m m
NOTES :
1. O U T LIN E C O N F O R M S T O E IA -481 .
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/
Data and specifications subject to change without notice. 9/98
10
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